Datasheet MC74VHCT74ADT, MC74VHCT74AD, MC74VHCT74ADR2, MC74VHCT74ADTR2 Datasheet (MOTOROLA)
Page 1
SEMICONDUCTOR TECHNICAL DATA
The MC74VHCT74A is an advanced high speed CMOS D–type flip–flop
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The signal level applied to the D input is transferred to Q output during the
positive going transition of the Clock pulse.
Reset (RD
accomplished by setting the appropriate input Low.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V , because it has full 5V CMOS
level output swings.
The VHCT74A input structures provide protection when voltages between
0V and 5.5V are applied, regardless of the supply voltage. The output
structures also provide protection when VCC=0V. These input and output
structures help prevent device destruction caused by supply voltage –
input/output voltage mismatch, battery backup, hot insertion, etc.
• High Speed: f
• Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 4.5V to 5.5V Operating Range
• Low Noise: V
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 128 FETs or 32 Equivalent Gates
) and Set (SD) are independent of the Clock (CP) and are
= 60MHz (Typ) at VCC = 5V
max
= 0.8V (Max)
OLP
D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
14–LEAD TSSOP PACKAGE
14–LEAD SOIC EIAJ PACKAGE
MC74VHCTXXAD
MC74VHCTXXADT
MC74VHCTXXAM
DT SUFFIX
CASE 948G–01
M SUFFIX
CASE 965–01
ORDERING INFORMATION
SOIC
TSSOP
SOIC EIAJ
PIN ASSIGNMENT
LOGIC DIAGRAM
RD1
D1
CP1
SD1
1
2
3
4
5
Q1
6
Q1
RD2
D2
CP2
SD2
13
12
11
10
9
Q2
8
Q2
FUNCTION TABLE
Inputs Outputs
RD CP D Q Q
SD
LH XX HL
HL XX LH
L L X X H* H*
HH H HL
HH L LH
H H L X No Change
H H H X No Change
H H X No Change
*Both outputs will remain high as long as Set and Reset are low, but the output
states are unpredictable if Set and Reset go high simultaneously.
3/98
Motorola, Inc. 1998
1
REV 0
RD1
D1
CP1
SD1
Q1
Q1
GND
1
2
3
4
6
7
14
13
12
11
105
V
CC
RD2
D2
CP2
SD2
9
Q2
8
Q2
Page 2
MC74VHCT74A
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ОООООООО
V
CC
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
Î
Î
ÎÎÎ
Î
ÎÎÎ
Î
Î
ÎÎÎ
ÎÎÎ
Output Voltage
ÎÎÎ
ÎÎÎ
Î
Î
Î
Î
ÎÎÎ
Î
ÎÎÎ
Î
Î
Î
Output Voltage
Î
Î
ÎÎÎ
Î
ÎÎÎ
Î
Î
ÎÎÎ
ÎÎÎ
Î
Î
Î
Î
ÎÎÎ
Î
ÎÎÎ
Î
Î
Î
Î
Î
Î
ÎÎÎ
Î
ÎÎÎ
Î
Î
ÎÎÎ
ÎÎÎ
MAXIMUM RATINGS*
Symbol
V
V
Î
I
I
I
Î
T
Î
DC Supply Voltage
CC
V
DC Input Voltage
in
DC Output Voltage VCC = 0
out
ОООООООООООО
I
Input Diode Current
IK
Output Diode Current (V
OK
DC Output Current, per Pin
out
DC Supply Current, VCC and GND Pins
CC
P
Power Dissipation in Still Air, SOIC Packages†
D
ОООООООООООО
Storage Temperature
stg
ОООООООООООО
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may adversely
affect device reliability . Functional operation under absolute–maximum–rated conditions is not
implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
Parameter
< GND; V
OUT
High or Low State
> VCC)
OUT
TSSOP Package†
Value
– 0.5 to + 7.0
– 0.5 to + 7.0
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
ÎÎÎÎ
– 20
± 20
± 25
± 50
500
450
ÎÎÎÎ
– 65 to + 150
ÎÎÎÎ
Unit
V
V
V
Î
mA
mA
mA
mA
mW
Î
_
C
Î
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
should be constrained to the
out
range GND v (Vin or V
Unused inputs must always be
) v VCC.
out
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
V
out
ÎÎ
T
A
tr, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage VCC = 0
ОООООООООООО
Operating Temperature
Input Rise and Fall Time VCC =5.0V ±0.5V
Parameter
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IH
V
IL
ÎÎ
V
OH
V
OL
ÎÎ
ÎÎÎООООО
I
in
I
CC
ÎÎ
I
CCT
ÎÎ
I
OPD
ÎÎ
Parameter
Minimum High–Level
Input Voltage
Maximum Low–Level
ООООО
Input Voltage
Minimum High–Level
Vin = VIH or V
Maximum Low–Level
ООООО
Vin = VIH or V
IL
IL
Maximum Input
Leakage Current
Maximum Quiescent
ООООО
Supply Current
Quiescent Supply
Current
ООООО
Output Leakage
Current
ООООО
Test Conditions
ОООООÎÎÎ
ООООО
ООООО
Vin = 5.5 V or GND
Vin = VCC or GND
ООООО
Per Input: VIN = 3.4V
Other Input: VCC or GND
ООООО
V
= 5.5V
OUT
ООООО
High or Low State
IOH = – 50µA
IOH = – 8mA
IOL = 50µA
IOL = 8mA
Min
4.5
0
0
Î
0
– 40
0
V
V
4.5 to
5.5
4.5 to
5.5
4.5
4.5
4.5
ÎÎ
4.5
ÎÎ
0 to 5.5
5.5
ÎÎ
5.5
ÎÎ
0
ÎÎ
Max
Unit
5.5
5.5
5.5
Î
V
+ 85
CC
20
V
V
V
Î
_
C
ns/V
TA = 25°C
Min
Typ
2.0
ÎÎÎÎÎ
4.4
4.5
3.94
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎ
0.0
ÎÎ
Max
0.8
ÎÎ
0.1
ÎÎ
0.36
ÎÎ
± 0.1
2.0
ÎÎ
1.35
ÎÎ
0.5
ÎÎ
TA = – 40 to 85°C
Min
Max
2.0
0.8
ÎÎÎÎÎ
4.4
3.80
ÎÎÎÎÎ
ÎÎÎÎÎ
0.1
0.44
± 1.0
ÎÎÎÎÎ
20.0
1.50
ÎÎÎÎÎ
5.0
ÎÎ
ÎÎ
Unit
V
V
Î
V
V
Î
Î
µA
µA
Î
mA
Î
µA
Î
MOTOROLA VHC Data – Advanced CMOS Logic
2
DL203 — Rev 2
Page 3
MC74VHCT74A
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ООООООООО
Î
Î
Î
ООООО
Î
Î
Î
AC ELECTRICAL CHARACTERISTICS (Input t
Symbol
t
PLH
t
ÎÎ
PHL
t
PLH
t
PHL
ÎÎ
f
max
ÎÎ
C
in
,
Maximum Propagation Delay,
CP to Q or Q
,
Maximum Propagation Delay,
SD
Maximum Clock Frequency
(50% Duty Cycle)
Maximum Input Capacitance
Parameter
ОООООО
or RD to Q or Q
ОООООО
ОООООО
= tf = 3.0ns)
r
Test Conditions
VCC = 5.0 ± 0.5V CL = 15pF
ООООООО
CL = 50pF
VCC = 5.0 ± 0.5V CL = 15pF
ООООООО
VCC = 5.0 ± 0.5V CL = 15pF
ООООООО
CL = 50pF
CL = 50pF
TA = 25°C
Min
Typ
5.8
ÎÎÎÎ
6.3
7.6
ÎÎÎÎ
100
ÎÎ
80
8.1
160
Î
140
4
TA = – 40 to 85°C
Max
7.8
8.8
ÎÎ
10.4
11.4
ÎÎ
ÎÎÎÎ
Min
1.0
1.0
Î
1.0
1.0
Î
80
65
10
Max
9.0
10.0
ÎÎ
12.0
13.0
ÎÎ
ÎÎ
10
Unit
ns
ns
MHz
pF
Typical @ 25°C, VCC = 5.0V
C
PD
Power Dissipation Capacitance (Note NO T AG)
24
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
no–load dynamic power consumption; PD = CPD V
TIMING REQUIREMENTS (Input t
= tf = 3.0ns)
r
CC(OPR
2
fin + ICC VCC.
CC
= CPD VCC fin + ICC/2 (per flip–flop). CPD is used to determine the
)
Guaranteed Limit
Symbol
ÎÎ
t
w
t
w
t
su
t
h
t
rec
ОООООООООООООО
Parameter
Minimum Pulse Width, CP
Minimum Pulse Width, RD or SD
Minimum Setup Time, D to CP
Minimum Hold Time, D to CP
Minimum Recovery Time, SD or RD to CP
V
CC
V
ÎÎÎ
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
TA = 25_C
ÎÎÎÎ
5.0
5.0
5.0
0.0
3.5
TA = – 40 to
85_C
ÎÎÎ
5.0
5.0
5.0
0.0
3.5
Unit
Î
ns
ns
ns
ns
ns
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
3 MOTOROLA
Page 4
MC74VHCT74A
CP
1.5V
Q or Q
SWITCHING WAVEFORMS
SD
or RD
3V
1.5V
GND
t
w
1/f
max
t
PLH
t
PHL
V
OH
V
OL
Q or Q
Q or Q
CP
Figure 1. Figure 2.
1.5V
t
w
t
PHL
1.5V V
t
PLH
1.5V V
CC
CC
t
rec
1.5V
3V
GND
3V
GND
3V
GND
TEST POINT
CP
VALID
D
1.5V
t
su
1.5V
t
h
3V
GND
3V
GND
DEVICE
UNDER
TEST
*Includes all probe and jig capacitance
Figure 3.
INPUT
OUTPUT
CL*
Figure 4.
Figure 5. Input Equivalent Circuit
MOTOROLA VHC Data – Advanced CMOS Logic
4
DL203 — Rev 2
Page 5
SEATING
PLANE
MC74VHCT74A
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
–A–
814
P 7 PL
–B–
M M
1
G
D 14 PL
0.25 (0.010) T B A
7
X 45°
C
R
K
M
S S
B0.25 (0.010)
M
J
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
F
MILLIMETERS INCHES
MIN MINMAX MAX
DIM
A
B
C
D
F
G
J
K
M
P
R
8.75
8.55
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC 0.050 BSC
0.25
0.19
0.25
0.10
7
0
°
°
5.80
6.20
0.25
0.50
0.337
0.150
0.054
0.014
0.016
0.008
0.004
0.228
0.010
0.344
0.157
0.068
0.019
0.049
0.009
0.009
7
0
°
°
0.244
0.019
0.10 (0.004)
SEATING
–T–
PLANE
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
14X REFK
S
U
T
S
N
0.25 (0.010)
U0.15 (0.006) T
S
2X L/2
0.10 (0.004) V
14
M
8
M
L
PIN 1
IDENT.
1
S
U0.15 (0.006) T
A
–V–
B
–U–
N
F
7
DETAIL E
K
K1
J
J1
SECTION N–N
C
D
G
H
DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
INCHESMILLIMETERS
–W–
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
____
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
5 MOTOROLA
Page 6
MC74VHCT74A
14 8
1
Z
e
b
0.13 (0.005)
M
OUTLINE DIMENSIONS
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 965–01
ISSUE O
L
E
Q
1
H
E
E
7
D
VIEW P
A
A
1
0.10 (0.004)
_
M
L
DETAIL P
c
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
DIM MIN MAX MIN MAX
––– 2.05 ––– 0.081
A
A
0.05 0.20 0.002 0.008
1
0.35 0.50 0.014 0.020
b
0.18 0.27 0.007 0.011
c
9.90 10.50 0.390 0.413
D
5.10 5.45 0.201 0.215
E
1.27 BSC 0.050 BSC
e
H
7.40 8.20 0.291 0.323
E
0.50 0.85 0.020 0.033
0.50
L
1.10 1.50 0.043 0.059
E
0
M
_
Q
0.70 0.90 0.028 0.035
1
––– 1.42 ––– 0.056
Z
10
INCHES
10
0
_
_
_
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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MOTOROLA VHC Data – Advanced CMOS Logic
◊
6
MC74VHCT74A/D
DL203 — Rev 2
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