Datasheet MC74VHCT540ADWR2, MC74VHCT540ADT, MC74VHCT540ADTR2, MC74VHCT540ADW Datasheet (MOTOROLA)
Page 1
SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1999
4/99
The MC74VHCT540A is an advanced high speed CMOS inverting octal
bus buffer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHCT540A features inputs and outputs on opposite sides of the
package and two AND–ed active–low output enables. When either OE1
or
OE2
are high, the terminal outputs are in the high impedance state.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V , because it has full 5V CMOS
level output swings.
The VHCT540A input and output (when disabled) structures provide
protection when voltages between 0V and 5.5V are applied, regardless of
the supply voltage. These input and output structures help prevent device
destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: tPD = 3.7ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
• TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: V
OLP
= 1.2V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 124 FETs or 31 Equivalent Gates
18
Y1
2
A1
17
Y2
3
A2
16
Y3
4
A3
15
Y4
5
A4
14
Y5
6
A5
13
Y6
7
A6
12
Y7
8
A7
11
Y8
9
A8
OE1
OE2
1
19
OUTPUT
ENABLES
DATA
INPUTS
INVERTING
OUTPUTS
LOGIC DIAGRAM
PIN ASSIGNMENT
A5
A3
A2
A1
OE1
GND
A8
A7
A6
A4 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Y3
Y2
Y1
OE2
V
CC
Y8
Y7
Y6
Y5
Y4
L
L
H
X
L
L
X
H
L
H
X
X
FUNCTION TABLE
Inputs
Output Y
OE1 OE2 A
H
L
Z
Z
DW SUFFIX
20–LEAD SOIC WIDE PACKAGE
CASE 751D–05
ORDERING INFORMATION
MC74VHCTXXXADW
MC74VHCTXXXADT
MC74VHCTXXXAM
SOIC WIDE
TSSOP
SOIC EIAJ
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
Page 2
MC74VHCT540A
MOTOROLA VHC Data – Advanced CMOS Logic
DL203 — Rev 2
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage
– 0.5 to + 7.0
V
V
in
DC Input Voltage
– 0.5 to + 7.0
V
V
out
DC Output Voltage
– 0.5 to VCC + 0.5
V
I
IK
Input Diode Current
– 20
mA
I
OK
Output Diode Current
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
Î
Î
P
D
ОООООООООООО
Î
Power Dissipation in Still Air, SOIC Packages†
TSSOP Package†
ÎÎÎÎ
Î
500
450
Î
Î
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage
4.5
5.5
V
V
in
DC Input Voltage
0
5.5
V
ÎÎ
Î
V
out
ОООООООООООО
Î
DC Output Voltage Outputs in 3–State
High or Low State
Î
Î
0
0
Î
Î
5.5
V
CC
Î
Î
V
T
A
Operating Temperature
– 40
+ 85
_
C
tr, t
f
Input Rise and Fall Time VCC =5.0V ±0.5V
0
20
ns/V
DC ELECTRICAL CHARACTERISTICS
V
TA = 25°C
TA ≤ 85°C
TA ≤ 125°C
Symbol
Parameter
Test Conditions
V
CC
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
Î
Î
V
IH
ОООООО
Î
Minimum High–Level Input
Voltage
ОООООÎÎ
Î
3.0
4.5
5.5
Î
Î
1.2
2.0
2.0
ÎÎÎÎÎ
Î
1.2
2.0
2.0
ÎÎÎ
Î
1.2
2.0
2.0
ÎÎÎ
V
Î
Î
V
IL
ОООООО
Î
Maximum Low–Level Input
Voltage
ОООООÎÎ
Î
3.0
4.5
5.5
ÎÎÎÎÎ
Î
0.53
0.8
0.8
ÎÎÎ
Î
0.53
0.8
0.8
ÎÎÎ
Î
0.53
0.8
0.8
Î
V
Î
Î
V
OH
ОООООО
Î
Minimum High–Level
Output Voltage
ООООО
Î
VIN = VIH or V
IL
IOH = – 50µA
Î
Î
3.0
4.5
Î
Î
2.9
4.4
Î
Î
3.0
4.5
ÎÎÎ
Î
2.9
4.4
ÎÎÎ
Î
2.9
4.4
ÎÎÎ
V
ÎÎОООООО
Î
VIN = VIH or V
IL
ООООО
Î
VIN = VIH or V
IL
IOH = – 4mA
IOH = – 8mA
Î
Î
3.0
4.5
Î
Î
2.58
3.94
ÎÎÎÎÎ
Î
2.48
3.80
ÎÎÎ
Î
2.34
3.66
ÎÎÎ
V
OL
Maximum Low–Level
Output Voltage
VIN = VIH or V
IL
IOL = 50µA
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
ÎÎОООООО
Î
VIN = VIH or V
IL
ООООО
Î
VIN = VIH or V
IL
IOL = 4mA
IOL = 8mA
Î
Î
3.0
4.5
ÎÎÎÎÎ
Î
0.36
0.36
ÎÎÎ
Î
0.44
0.44
ÎÎÎ
Î
0.52
0.52
Î
Î
Î
I
IN
ОООООО
Î
Maximum Input Leakage
Current
ООООО
Î
Vin = 5.5 V or GND
Î
Î
0 to 5.5
ÎÎÎÎÎ
Î
± 0.1
ÎÎÎ
Î
± 1.0
ÎÎÎ
Î
± 1.0εA
Î
I
CC
ОООООО
Maximum Quiescent Supply
Current
ООООО
Vin = VCC or GND
Î
5.5
Î
Î
Î
2.0
Î
Î20Î
Î40Î
µA
I
CCT
Quiescent Supply Current
Input: VIN = 3.4V
5.5
1.35
1.50
1.65
mA
I
OPD
Output Leakage Current
V
OUT
= 5.5V
0.0
0.5
5.0
10
µA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Page 3
MC74VHCT540A
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
3 MOTOROLA
AC ELECTRICAL CHARACTERISTICS (Input t
r
= tf = 3.0ns)
ÎÎООООООÎОООООООÎООООО
Î
TA = 25°C
ÎÎÎ
Î
TA = – 40 to
85°C
ÎÎÎ
Î
TA ≤ 125°C
Î
Symbol
Parameter
Test Conditions
Min
Typ
Max
Min
Max
Min
Max
Unit
Î
Î
t
PLH
,
t
PHL
ОООООО
Î
Maximum Propagation
Delay, A to Y
ООООООО
Î
VCC = 3.3 ± 0.3V CL = 15pF
CL = 50pF
ÎÎÎ
Î
4.8
7.3
Î
Î
7.0
10.5
Î
Î
1.0
1.0
Î
Î
8.5
12.0
ÎÎÎ
Î
10.5
14.0
Î
ns
ÎÎОООООО
Î
(
Figures 1 and 3
)
ООООООО
Î
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF
ÎÎÎ
Î
3.7
5.2
Î
Î
5.0
7.0
Î
Î
1.0
1.0
Î
Î
6.0
8.0
ÎÎÎ
Î
8.0
10.0
Î
Î
Î
t
PZL
,
t
PZH
ОООООО
Î
Output Enable TIme,
OEn
to Y
ООООООО
Î
VCC = 3.3 ± 0.3V CL = 15pF
RL = 1kΩ CL = 50pF
ÎÎÎ
Î
6.8
9.3
Î
Î
10.5
14.0
Î
Î
1.0
1.0
Î
Î
12.5
16.0
ÎÎÎ
Î
15.0
19.0
Î
ns
ÎÎОООООО
Î
(
Figures 2 and 4
)
ООООООО
Î
VCC = 5.0 ± 0.5V CL = 15pF
RL = 1kΩ CL = 50pF
ÎÎÎ
Î
4.7
6.2
Î
Î
7.2
9.2
Î
Î
1.0
1.0
Î
Î
8.5
10.5
ÎÎÎ
Î
10.5
13.0
Î
t
PLZ
,
t
PHZ
Output Disable Time,
OEn
to Y
VCC = 3.3 ± 0.3V CL = 50pF
RL = 1kΩ
11.2
15.4
1.0
17.5
20.0
ns
ÎÎОООООО
Î
(
Figures 2 and 4
)
ООООООО
Î
VCC = 5.0 ± 0.5V CL = 50pF
RL = 1kΩ
ÎÎÎ
Î
6.0
Î
Î
8.8
Î
Î
1.0
Î
Î
10.0
ÎÎÎ
Î
11.5
Î
Î
Î
t
OSLH
,
t
OSHL
ОООООО
Î
Output to Output Skew
ООООООО
Î
VCC = 3.3 ± 0.3V CL = 50pF
(Note 1.)
ÎÎÎÎÎ
Î
1.5
ÎÎÎ
Î
1.5
ÎÎÎ
Î
2.0Îns
VCC = 5.0 ± 0.5V CL = 50pF
(Note 1.)
1.0
1.0
1.5
ns
Î
Î
C
in
ОООООО
Î
Maximum Input
Capacitance
ОООООООÎÎÎÎ
Î
4
Î
Î
10
ÎÎÎ
Î
10
ÎÎÎ
Î
10ÎpF
Î
Î
C
out
ОООООО
Î
Maximum Three–State
Output Capacitance (Output
in High Impedance State)
ОООООООÎÎÎÎ
Î
6
ÎÎÎÎÎÎÎÎÎÎÎ
pF
Typical @ 25°C, VCC = 5.0V
C
PD
Power Dissipation Capacitance (Note 2.)
17
pF
1. Parameter guaranteed by design. t
OSLH
= |t
PLHm
– t
PLHn
|, t
OSHL
= |t
PHLm
– t
PHLn
|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= CPD VCC fin + ICC/8 (per bit). CPD is used to determine the no–load
dynamic power consumption; PD = CPD V
CC
2
fin + ICC VCC.
NOISE CHARACTERISTICS (Input t
r
= tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25°C
Symbol Parameter
Typ Max
Unit
V
OLP
Quiet Output Maximum Dynamic V
OL
0.9 1.2 V
V
OLV
Quiet Output Minimum Dynamic V
OL
– 0.9 – 1.2 V
V
IHD
Minimum High Level Dynamic Input Voltage 3.5 V
V
ILD
Maximum Low Level Dynamic Input Voltage 1.5 V
Page 4
MC74VHCT540A
MOTOROLA VHC Data – Advanced CMOS Logic
DL203 — Rev 2
4
Figure 1.
3.0V
GND
A
Y
t
PHL
OE1 or OE2
50%
3.0V
GND
Y
t
PZL
Y
t
PZH
HIGH
IMPEDANCE
VOL +0.3V
VOH –0.3V
HIGH
IMPEDANCE
t
PLZ
t
PHZ
1.5V
1.5V
t
PLH
1.5V
Figure 2.
SWITCHING WAVEFORMS
1.5V
1.5V
V
OH
V
OL
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
TEST CIRCUITS
Figure 3. Figure 4.
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
1k
Ω
CONNECT TO VCC WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
Page 5
MC74VHCT540A
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
5 MOTOROLA
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC WIDE PACKAGE
CASE 751D–05
ISSUE F
20
1
11
10
B20X
H10X
C
L
18X
A1
A
SEATING
PLANE
q
h X 45
_
E
D
M
0.25
M
B
M
0.25
SAS
B
T
e
T
B
A
DIM MIN MAX
MILLIMETERS
A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90
q
0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
__
Page 6
MC74VHCT540A
MOTOROLA VHC Data – Advanced CMOS Logic
DL203 — Rev 2
6
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
DIMAMIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B 4.30 4.50 0.169 0.177
C 1.20 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
110
1120
PIN 1
IDENT
A
B
–T–
0.100 (0.004)
C
D
G
H
SECTION N–N
K
K1
JJ1
N
N
M
F
–W–
SEATING
PLANE
–V–
–U–
S
U
M
0.10 (0.004) V
S
T
20X REFK
L
L/2
2X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E
6.40 0.252
––– –––
S
U0.15 (0.006) T
Page 7
MC74VHCT540A
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
7 MOTOROLA
OUTLINE DIMENSIONS
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 967–01
ISSUE O
DIM MIN MAX MIN MAX
INCHES
––– 2.05 ––– 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
12.35 12.80 0.486 0.504
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
––– 0.81 ––– 0.032
A
1
H
E
Q
1
L
E
_
10
_
0
_
10
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MA TERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
H
E
A
1
L
E
Q
1
_
c
A
Z
D
E
20
110
11
b
M
0.13 (0.005)
e
0.10 (0.004)
VIEW P
DETAIL P
M
L
A
b
c
D
E
e
L
M
Z
Page 8
MC74VHCT540A
MOTOROLA VHC Data – Advanced CMOS Logic
DL203 — Rev 2
8
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