Datasheet MC74VHCT132ADTR2, MC74VHCT132ADT, MC74VHCT132AD, MC74VHCT132ADR2 Datasheet (MOTOROLA)

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SEMICONDUCTOR TECHNICAL DATA

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The MC74VHCT132A is an advanced high speed CMOS Schmitt NAND trigger fabricated with silicon gate CMOS technology . It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

Pin configuration and function are the same as the MC74VHC00, but the inputs have hysteresis and, with its Schmitt trigger function, the VHCT132A can be used as a line receiver which will receive slow input signals.

The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3V to 5.0V , because it has full 5V CMOS level output swings.

The VHCT132A input structures provide protection when voltages between 0V and 5.5V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch, battery backup, hot insertion, etc.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.

• High Speed: tPD = 4.9ns (Typ) at VCC = 5V

• Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C

• TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

• Designed for 2V to 5.5V Operating Range

• Low Noise: V

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300mA

• ESD Performance: HBM > 2000V; Machine Model > 200V

• Chip Complexity: 72 FETs or 18 Equivalent Gates

= 0.8V (Max)

OLP

Pinout: 14–Lead Packages (Top View)

VCCB4 A4 Y4

1314 12 11 10 9 8

B3 A3 Y3



D SUFFIX

14–LEAD SOIC PACKAGE

CASE 751A–03

14–LEAD TSSOP PACKAGE

14–LEAD SOIC EIAJ PACKAGE

MC74VHCTXXAD MC74VHCTXXADT MC74VHCTXXAM

DT SUFFIX

CASE 948G–01

M SUFFIX

CASE 965–01

ORDERING INFORMATION

SOIC TSSOP SOIC EIAJ

FUNCTION TABLE

Inputs Output

ABY

LLH

LHH HLH HHL

4/99

 Motorola, Inc. 1999

21 34567

A1 B1 Y1 A2 B2 Y2 GND

1

A1

2

B1

4

A2

5

B2

1

LOGIC DIAGRAM

3

Y1

6

Y2

A3

B3

A4

B4

9

10

12

13

REV 0

8

Y3

11

Y4

MC74VHCT132A

Î

V

CC

Î

OH

Î

MAXIMUM RATINGS*

Symbol

V

I I I

Î

T

DC Supply Voltage

CC

V

DC Input Voltage

in

DC Output Voltage

out

I

Input Diode Current

IK

Output Diode Current

OK

DC Output Current, per Pin

out

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air, SOIC Packages†

D

ОООООООООООО

Storage Temperature

stg

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions

beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.

†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C

TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol

V

T

DC Supply Voltage

CC

DC Input Voltage

in

DC Output Voltage

out

Operating Temperature, All Package Types

A

DC ELECTRICAL CHARACTERISTICS

Symbol

V

T+

Î

V

T–

Î

V

H

Î

V

OH

Î

V

OL

Î

Positive Threshold Voltage

ОООООО

Negative Threshold Voltage

ОООООО

Hysteresis Voltage

ОООООО

Minimum High–Level

ОООООО

Output Voltage IOH = –50µA

ОООООО

Maximum Low–Level Output Voltage

ОООООО

Parameter

– 0.5 to + 7.0 – 0.5 to + 7.0

– 0.5 to VCC + 0.5

TSSOP Package†

ÎÎÎÎ

– 65 to + 150

V

Test Conditions

V

3.0

ОООООÎÎ

4.5

5.5

3.0

ОООООÎÎ

4.5

6.0

3.0

ОООООÎÎ

4.5

5.5

VIN = VIH or V

ООООО

IOH = – 50µA

ООООО

IOH = – 4mA IOH = – 8mA

ООООО

VIN = VIH or V IOL = 50µA

ООООО

IL

2.0

Î

3.0

4.5

Î

4.5

5.5

Î

2.0

3.0

Î

4.5

Value

– 20

± 20 ± 25 ± 50

500 450

Min

Max

4.5

5.5

0

5.5

0

V

CC

– 40

+ 85

TA = 25°C

Min

Typ

ÎÎÎÎÎ

0.35

0.5

Î

ÎÎÎÎÎ

0.6

0.30

0.40

Î

ÎÎÎ

0.50

1.9

2.9

4.4

2.0

Î

3.0

4.5

Î

2.58

3.94

Î

0.0

ÎÎÎ

0.0

Unit

V V

V mA mA mA mA

mW

Î

_

C

Unit

V

_

C

Max

1.7

2.0

1.20

1.40

1.60

Î

0.1

Î

0.1

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

should be constrained to the

out

range GND v (Vin or V

Unused inputs must always be

) v VCC.

out

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

TA ≤ 85°C

Min

Max

1.6

ÎÎÎ

2.0

0.35

0.5

ÎÎÎ

0.6

0.30

1.20

0.40

1.40

Î

0.50

Î

1.60

1.9

Î

2.48

3.80

Î

2.9

4.4

Î

0.1

ÎÎÎ

0.1

TA ≤ 125°C

Min

Max

1.6

ÎÎÎ

2.0

0.35

0.5

0.6

0.30

0.40

Î

0.50

ÎÎÎ

1.20

1.40

Î

1.60

1.9

Î

2.9

4.4

Î

2.34

3.66

Î

0.1

ÎÎÎ

0.1

Unit

V

Î

V

Î

V

Î

V

Î

ÎÎООООООÎООООО

I

Maximum Input Leakage

IN

Current

I

Î

I

CCT

I

OPD

Maximum Quiescent Supply

CC

ОООООО

Current Quiescent Supply Current Output Leakage Current

IOL = 4mA IOL = 8mA

VIN = 5.5V or GND

VIN = VCC or GND

ООООО

Input: VIN = 3.4V V

= 5.5V

OUT

MOTOROLA VHC Data – Advanced CMOS Logic

4.5

Î

5.5

0 to 5.5

5.5

Î

5.5

0.0

2

ÎÎÎÎÎ

0.36

± 0.1

ÎÎÎÎÎ

2.0

1.35

0.5

0.44

ÎÎÎ

0.44

± 1.0

ÎÎÎ

20

1.50

5.0

0.52

ÎÎÎ

0.52

± 1.0

ÎÎÎ

40ÎµA

1.65 10

DL203 — Rev 0

Î

µA

mA

µA

MC74VHCT132A

Î

AC ELECTRICAL CHARACTERISTICS (Input t

= tf = 3.0ns)

r

TA = – 40 to

ÎÎООООООÎОООООООÎООООО

Symbol

t

,

PLH

t

Î

ÎÎООООООÎООООООО

Î

Maximum Propagation Delay, A or B to Y

PHL

ОООООО

C

Maximum Input

in

ОООООО

Capacitance

Parameter

Test Conditions

VCC = 3.3 ± 0.3 V CL = 15pF

ООООООО

CL = 50pF

VCC = 5.0 ± 0.5 V CL = 15pF

CL = 50pF

ОООООООÎÎÎÎ

TA = 25°C

Min

Typ

7.6

ÎÎÎ

10.1

4.9

6.4 4

Max

11.9

15.4

Î

7.7

Î

9.7 10

Î

85°C

ÎÎÎ

Min

Max

1.0

14.0

1.0

17.5

Î

1.0

Î

9.0

Î

11.0 10

ÎÎÎ

TA ≤ 125°C

Min

Max

16.5

20.0

ÎÎÎ

11.0

ÎÎÎ

13.0 10ÎpF

ÎÎÎ

Î

Unit

ns

Î

Typical @ 25°C, VCC = 5.0 V

C

Power Dissipation Capacitance (Note 1.)

PD

16

pF

1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I dynamic power consumption; PD = CPD  V

NOISE CHARACTERISTICS (Input t

= tf = 3.0ns, CL = 50pF, VCC = 5.0 V)

r

2

 fin + ICC  VCC.

CC

CC(OPR

= CPD  VCC  fin + ICC/4 (per gate). CPD is used to determine the no–load

)

TA = 25°C

Symbol Characteristic

V V

V

OLP OLV

IHD

ILD

Quiet Output Maximum Dynamic V Quiet Output Minimum Dynamic V

OL

Minimum High Level Dynamic Input Voltage 3.5 V Maximum Low Level Dynamic Input Voltage 1.5 V

Typ Max

0.3 0.8 V

– 0.3 – 0.8 V

Unit

VHC Data – Advanced CMOS Logic DL203 — Rev 0

3 MOTOROLA

MC74VHCT132A

3.0V

1.5V

A

t

PLH

Y

1.5V

Figure 1. Switching Waveforms

(a) A Schmitt–Trigger Squares Up Inputs With Slow Rise and Fall Times (b) A Schmitt–Trigger Offers Maximum Noise Immunity

V

H

V

in

V

out

t

PHL

GND

V

CC

V

T+

V

T–

GND

V

OH

V

OL

OH

OL

DEVICE UNDER

TEST

*Includes all probe and jig capacitance

Figure 2. T est Circuit

V

H

V

in

V

out

TEST POINT

OUTPUT

CL*

Figure 3. T ypical Schmitt–Trigger Applications

V

CC

V

T+

V

T–

GND

V

OH

V

OL

MOTOROLA VHC Data – Advanced CMOS Logic

4

DL203 — Rev 0

SEATING PLANE

MC74VHCT132A

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

–A–

814

P 7 PL

–B–

M M

1

G

D 14 PL

0.25 (0.010) T B A

7

X 45°

C

R

K

M

S S

B0.25 (0.010)

M

J

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

F

MILLIMETERS INCHES

MIN MINMAX MAX

DIM

A B C D F G J K M P R

8.75

8.55

4.00

3.80

1.75

1.35

0.49

0.35

1.25

0.40

1.27 BSC 0.050 BSC

0.25

0.19

0.25

0.10 7

0

°

5.80

6.20

0.25

0.50

0.337

0.150

0.054

0.014

0.016

0.008

0.004

0.228

0.010

0.344

0.157

0.068

0.019

0.049

0.009

0.009 7

0

°

0.244

0.019

VHC Data – Advanced CMOS Logic DL203 — Rev 0

5 MOTOROLA

MC74VHCT132A

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948G–01

ISSUE O

0.10 (0.004)

SEATING

–T–

PLANE

14X REFK

S

U

T

S

N

0.25 (0.010)

U0.15 (0.006) T

S

2X L/2

0.10 (0.004) V

14

M

8

M

L

PIN 1 IDENT.

1

S

U0.15 (0.006) T

A

–V–

B

–U–

N

F

7

DETAIL E

K

K1

J

J1

SECTION N–N

C

D

G

H

DETAIL E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.

INCHESMILLIMETERS

–W–

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C ––– 1.20 ––– 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030

G 0.65 BSC 0.026 BSC

H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

____

MOTOROLA VHC Data – Advanced CMOS Logic

6

DL203 — Rev 0

14 8

1

Z

D

e

b

0.13 (0.005)

M

H

E

7

A

1

0.10 (0.004)

OUTLINE DIMENSIONS

M SUFFIX

PLASTIC SOIC EIAJ PACKAGE

CASE 965–01

ISSUE O

L

E

VIEW P

_

M

L DETAIL P

MC74VHCT132A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED

Q

1

c

AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

––– 2.05 ––– 0.081

A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

0.50 L

1.10 1.50 0.043 0.059

E

0

M

_

Q

0.70 0.90 0.028 0.035

1

––– 1.42 ––– 0.056

Z

10

INCHES

10

0

_

VHC Data – Advanced CMOS Logic DL203 — Rev 0

7 MOTOROLA

MC74VHCT132A

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MOTOROLA VHC Data – Advanced CMOS Logic

8

Mfax is a trademark of Motorola, Inc.

MC74VHCT132A/D

DL203 — Rev 0

Datasheet MC74VHCT132ADTR2, MC74VHCT132ADT, MC74VHCT132AD, MC74VHCT132ADR2 Datasheet (MOTOROLA)

Specifications and Main Features

Frequently Asked Questions

User Manual