Datasheet MC74VHCT04AMEL, MC74VHCT04AML1, MC74VHCT04AML2, MC74VHCT04ADR2, MC74VHCT04ADT Datasheet (MOTOROLA)



SEMICONDUCTOR TECHNICAL DATA

1

REV 0

 Motorola, Inc. 1997

6/97

 

The MC74VHCT04A is an advanced high speed CMOS inverter
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.

The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.

The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V , because it has full 5V CMOS
level output swings.

The VHCT04A input structures provide protection when voltages between
0V and 5.5V are applied, regardless of the supply voltage. The output
structures also provide protection when VCC = 0V. These input and output
structures help prevent device destruction caused by supply voltage –
input/output voltage mismatch, battery backup, hot insertion, etc.

• High Speed: tPD = 4.7ns (Typ) at VCC = 5V

• Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C

• TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V

• Power Down Protection Provided on Inputs and Outputs

• Balanced Propagation Delays

• Designed for 4.5V to 5.5V Operating Range

• Low Noise: V

OLP

= 1.0V (Max)

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300mA

• ESD Performance: HBM > 2000V; Machine Model > 200V

• Chip Complexity: 48 FETs or 12 Equivalent Gates

LOGIC DIAGRAM

Y1A1

A2

A3

A4

A5

A6

Y2

Y3

Y4

Y5

Y6

1

3

5

9

11

13

2

4

6

8

10

12

Y = A

Pinout: 14–Lead Packages (Top View)

1314 12 11 10 9 8

21 34567

VCCA6 Y6

A5 Y5 A4 Y4

A1 Y1 A2 Y2 A3 Y3 GND



L
H

FUNCTION TABLE

Inputs Outputs

A

H
L

Y

D SUFFIX

14–LEAD SOIC PACKAGE

CASE 751A–03

DT SUFFIX

14–LEAD TSSOP PACKAGE

CASE 948G–01

ORDERING INFORMATION

MC74VHCTXXAD
MC74VHCTXXADT
MC74VHCTXXAM

SOIC
TSSOP
SOIC EIAJ

M SUFFIX

14–LEAD SOIC EIAJ PACKAGE

CASE 965–01

MC74VHCT04A

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 1

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage

– 0.5 to + 7.0

V

V

in

DC Input Voltage

– 0.5 to + 7.0

V

Î

Î

V

out

ОООООООООООО

Î

DC Output Voltage VCC = 0

High or Low State

ÎÎÎÎ

Î

– 0.5 to + 7.0

– 0.5 to VCC + 0.5

Î

Î

V

I

IK

Input Diode Current

– 20

mA

I

OK

Output Diode Current (V

OUT

< GND; V

OUT

> VCC)

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

Î

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air, SOIC Packages†

TSSOP Package†

ÎÎÎÎ

Î

500
450

Î

Î

mW

Î

Î

T

stg

ОООООООООООО

Î

Storage Temperature

ÎÎÎÎ

Î

– 65 to + 150

Î

Î

_

C

* Absolute maximum continuous ratings are those values beyond which damage to the device

may occur. Exposure to these conditions or conditions beyond those indicated may adversely

affect device reliability . Functional operation under absolute–maximum–rated conditions is not

implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C

TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage

4.5

5.5

V

V

in

DC Input Voltage

0

5.5

V

ÎÎ

Î

V

out

ОООООООООООО

Î

DC Output Voltage VCC = 0

High or Low State

Î

Î

0
0

Î

Î

5.5

V

CC

Î

Î

V

T

A

Operating Temperature

– 40

+ 85

_

C

tr, t

f

Input Rise and Fall Time VCC =5.0V ±0.5V

0

20

ns/V

DC ELECTRICAL CHARACTERISTICS

V

ОООООООО

TA = 25°C

TA = – 40 to 85°C

Symbol

Parameter

Test Conditions

V

CC

V

ÎÎÎ

Min

Typ

ÎÎÎ

Max

Min

Max

Unit

V

IH

Minimum High–Level
Input Voltage

4.5 to

5.5

ÎÎÎ

2.0

ÎÎÎ

2.0

V

ÎÎ

Î

V

IL

ООООО

Î

Maximum Low–Level
Input Voltage

ОООООÎÎÎ

Î

4.5 to

5.5

ÎÎÎ

ÎÎÎÎÎ

Î

ÎÎÎ

ÎÎ

Î

0.8

ÎÎÎÎÎ

Î

0.8

Î

V

V

OH

Minimum High–Level

IOH = – 50µA

4.5

ÎÎÎ

4.4

4.5

ÎÎÎ

4.4

V

Output Voltage

Vin = VIH or V

IL

IOH = – 8mA

4.5

ÎÎÎ

3.94

ÎÎÎ

3.80

ÎÎ

Î

V

OL

ООООО

Î

Maximum Low–Level

ООООО

Î

IOL = 50µA

ÎÎ

Î

4.5

ÎÎÎ

ÎÎÎÎÎ

Î

0.0

ÎÎÎ

ÎÎ

Î

0.1

ÎÎÎÎÎ

Î

0.1

Î

V

ÎÎÎООООО

Î

Output Voltage

Vin = VIH or V

IL

ООООО

Î

IOL = 8mA

ÎÎ

Î

4.5

ÎÎÎ

ÎÎÎÎÎ

Î

ÎÎÎ

ÎÎ

Î

0.36

ÎÎÎÎÎ

Î

0.44

Î

I

in

Maximum Input
Leakage Current

Vin = 5.5 V or GND

0 to 5.5

ÎÎÎ

ÎÎÎ

± 0.1

± 1.0

µA

ÎÎ

Î

I

CC

ООООО

Î

Maximum Quiescent
Supply Current

ООООО

Î

Vin = VCC or GND

ÎÎ

Î

5.5

ÎÎÎ

ÎÎÎÎÎ

Î

ÎÎÎ

ÎÎ

Î

2.0

ÎÎÎÎÎ

Î

20.0

Î

µA

ÎÎ

Î

I

CCT

ООООО

Î

Quiescent Supply
Current

ООООО

Î

Per Input: VIN = 3.4V
Other Input: VCC or GND

ÎÎ

Î

5.5

ÎÎÎ

ÎÎÎÎÎ

Î

ÎÎÎ

ÎÎ

Î

1.35

ÎÎÎÎÎ

Î

1.50ÎmA

ÎÎ

I

OPD

ООООО

Output Leakage
Current

ООООО

V

OUT

= 5.5V

ÎÎ

0

ÎÎÎ

ÎÎ

ÎÎ

ÎÎÎ

ÎÎ

0.5

ÎÎ

ÎÎ

5.0

Î

µA

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74VHCT04A

VHC Data – Advanced CMOS Logic
DL203 — Rev 1

3 MOTOROLA

AC ELECTRICAL CHARACTERISTICS (Input t

r

= tf = 3.0ns)

TA = 25°C

TA = – 40 to 85°C

Symbol

Parameter

Test Conditions

Min

Typ

Max

Min

Max

Unit

ÎÎ

Î

t

PLH

,

t

PHL

ООООООО

Maximum Propagation Delay,
A to Y

ООООООО

Î

VCC = 5.0 ± 0.5V CL = 15pF

CL = 50pF

ÎÎÎÎ

Î

4.7

5.5

ÎÎ

Î

6.7

7.7

Î

Î

1.0

1.0

ÎÎ

Î

7.5

8.5

Î

ns

C

in

Maximum Input Capacitance

4

10

10

pF

Typical @ 25°C, VCC = 5.0V

C

PD

Power Dissipation Capacitance (Note 1.)

11

pF

1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I

CC(OPR

)

= CPD  VCC  fin + ICC/6 (per buffer). CPD is used to determine the no–load

dynamic power consumption; PD = CPD  V

CC

2

 fin + ICC  VCC.

NOISE CHARACTERISTICS (Input t

r

= tf = 3.0ns, CL = 50pF, VCC = 5.0V)

TA = 25°C

Symbol Characteristic

Typ Max

Unit

V

OLP

Quiet Output Maximum Dynamic V

OL

0.8 1.0 V

V

OLV

Quiet Output Minimum Dynamic V

OL

–0.8 –1.0 V

V

IHD

Minimum High Level Dynamic Input Voltage 2.0 V

V

ILD

Maximum Low Level Dynamic Input Voltage 0.8 V

Figure 1. Switching Waveforms

*Includes all probe and jig capacitance

Figure 2. Test Circuit

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

3V

GND

1.5V

1.5V

A

Y

t

PHL

t

PLH

V

OH

V

OL

MC74VHCT04A

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 1

4

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F
G
J
K
M
P
R

8.55

3.80

1.35

0.35

0.40

0.19

0.10
0

°

5.80

0.25

8.75

4.00

1.75

0.49

1.25

0.25

0.25
7

°

6.20

0.50

0.337

0.150

0.054

0.014

0.016

0.008

0.004
0

°

0.228

0.010

0.344

0.157

0.068

0.019

0.049

0.009

0.009
7

°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

P 7 PL

G

C

K

SEATING
PLANE

D 14 PL

M

J

R

X 45°

1

7

814

0.25 (0.010) T B A

M

S S

B0.25 (0.010)

M M

F

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948G–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006

F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024

J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V

S

T

L

–U–

SEATING
PLANE

0.10 (0.004)

–T–

SECTION N–N

DETAIL E

J

J1

K

K1

DETAIL E

F

M

–W–

0.25 (0.010)

8

14

7

1

PIN 1
IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

–V–

14X REFK

N

N

MC74VHCT04A

VHC Data – Advanced CMOS Logic
DL203 — Rev 1

5 MOTOROLA

OUTLINE DIMENSIONS

M SUFFIX

PLASTIC SOIC EIAJ PACKAGE

CASE 965–01

ISSUE O

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035

––– 1.42 ––– 0.056

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MA TERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

0.13 (0.005)

M

0.10 (0.004)

D

Z

E

1

14 8

7

e

A

b

VIEW P

c

L
DETAIL P

M

A

b
c
D
E
e

0.50

M

Z

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