Datasheet MC74VHC595 Datasheet

MC74HC595A

8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs

High–Performance Silicon–Gate CMOS

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The MC74HC595A consists of an 8–bit shift register and an 8–bit D–type latch with three–state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8–bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register.

The HC595A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 328 FET s or 82 Equivalent Gates

• Improvements over HC595

— Improved Propagation Delays — 50% Lower Quiescent Power — Improved Input Noise and Latchup Immunity

SERIAL

DATA

INPUT

OUTPUT

ENABLE

SHIFT

CLOCK

RESET

LATCH

CLOCK

14

A

11

10

12 13

LOGIC DIAGRAM

SHIFT

REGISTER

LATCH

15

Q

A

1

Q

B

2

Q

C

3

Q

D

4

Q

E

5

Q

F

6

Q

G

7

Q

H

9

SQ

H

VCC = PIN 16 GND = PIN 8

PARALLEL

DATA

OUTPUTS

SERIAL

DATA

OUTPUT

MARKING

DIAGRAMS

16

PDIP–16

16

1

16

1

16

N SUFFIX

CASE 648

SO–16

D SUFFIX

CASE 751B

TSSOP–16

DT SUFFIX

1

CASE 948F

A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week

MC74HC595AN

AWLYYWW

1

16

HC595A

AWLYWW

1

16

HC

595A

ALYW

1

PIN ASSIGNMENT

Q Q Q Q Q

Q

GND

1

B

2

C

3

D

4

E F

6

G

7

H

8

V

16

CC

Q

15

A

14

OUTPUT ENABLE

13

LATCH CLOCK

125

SHIFT CLOCK

11

RESET

10

SQ

9

H

ORDERING INFORMATION

Device Package Shipping

MC74HC595AN PDIP–16 2000 / Box MC74HC595AD SOIC–16 MC74HC595ADR2 SOIC–16 2500 / Reel MC74HC595ADT TSSOP–16 96 / Rail MC74HC595ADTR2 TSSOP–16

48 / Rail

2500 / Reel

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev . 8

1 Publication Order Number:

MC74HC595A/D

MC74HC595A

Î

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MAXIMUM RATINGS*

Symbol

V

I I

ÎÎ

T

ÎÎ

DC Supply Voltage (Referenced to GND)

CC

V

DC Input Voltage (Referenced to GND)

in

DC Output Voltage (Referenced to GND)

out

I

DC Input Current, per Pin

in

DC Output Current, per Pin

out

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air, Plastic DIP†

D

ОООООООООООО

Storage Temperature

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

ОООООООООООО

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Parameter

SOIC Package†

TSSOP Package†

(Plastic DIP, SOIC or TSSOP Package)

Value

– 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5

± 20 ± 35 ± 75

750 500

ÎÎÎ

450

– 65 to + 150

260

ÎÎÎ

Unit

mA mA mA

mW

Î

_

Î

This device contains protection

V V V

circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

should be constrained to the

out

range GND v (Vin or V

Unused inputs must always be

) v VCC.

out

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

C C

RECOMMENDED OPERATING CONDITIONS

Symbol

V

CC

Vin, V

ÎÎ

T

A

tr, t

ÎÎ

DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage

out

(Referenced to GND)

ООООООООООООО

Operating Temperature, All Package Types Input Rise and Fall Time VCC = 2.0 V

f

(Figure 1) VCC = 4.5 V

ООООООООООООО

Parameter

VCC = 6.0 V

Min

2.0 0

Î

– 55

0 0

Î

0

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎ

Symbol

V

ÎÎ

V

ÎÎ

V

ÎÎ

ÎÎÎОООООООÎООООООО

V

ÎÎ

ÎÎÎОООООООÎООООООО

ООООООО

Minimum High–Level Input

IH

Voltage

ООООООО

Maximum Low–Level Input

IL

Voltage

ООООООО

OH

OL

Minimum High–Level Output Voltage, QA – Q

ООООООО

Maximum Low–Level Output

ООООООО

Voltage, QA – Q

ООООООО

Parameter

ООООООО

Test Conditions

V

= 0.1 V or VCC – 0.1 V

out

|I

| v 20 µA

out

ООООООО

V

= 0.1 V or VCC – 0.1 V

out

|I

| v 20 µA

out

ООООООО

Vin = VIH or V |I

H

| v 20 µA

out

ООООООО

Vin = VIH or VIL|I

Vin = VIH or V

ООООООО

|I

H

| v 20 µA

out

ООООООО

Vin = VIH or VIL|I

IL

| v 2.4 mA

out

|I

| v 6.0 mA

out

|I

| v 7.8 mA

out

| v 2.4 mA

out

|I

| v 6.0 mA

out

|I

| v 7.8 mA

out

Max

6.0

V

CC

+ 125

1000

500 400

ÎÎ

V

CC V

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

4.5

6.0

3.0

4.5

6.0

2.0

4.5

6.0

3.0

4.5

6.0

Unit

Î

_

Î

ns

V V

C

Guaranteed Limit

– 55 to

ÎÎ

25_C

1.5

2.1

ÎÎ

3.15

4.2

ÎÎ

0.5

0.9

ÎÎ

1.35

1.8

ÎÎ

1.9

4.4

ÎÎ

5.9

2.48

3.98

ÎÎ

5.48

0.1

ÎÎ

0.1

ÎÎ

0.26

ÎÎ

0.26

v

Î

85_C

1.5

2.1

Î

3.15

4.2

Î

0.5

0.9

Î

1.35

1.8

Î

1.9

4.4

Î

5.9

2.34

3.84

Î

5.34

0.1

Î

0.1

Î

0.33

Î

0.33

ÎÎ

v

125_C

1.5

2.1

ÎÎ

3.15

4.2

ÎÎ

0.5

0.9

ÎÎ

1.35

1.8

ÎÎ

1.9

4.4

ÎÎ

5.9

2.2

3.7

ÎÎ

5.2

0.1

ÎÎ

0.1

ÎÎ

0.4

ÎÎ

0.4

Î

Unit

Î

V

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2

MC74HC595A

ÎÎÎ

Î

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Î

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Î

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Î

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Î

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Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

V

Symbol

V

OH

ÎÎ

ÎÎÎОООООООÎООООООО

V

OL

ÎÎ

ÎÎÎОООООООÎООООООО

I

in

ÎÎ

I

OZ

ÎÎ

I

CC

ÎÎ

Minimum High–Level Output

ООООООО

Voltage, SQ

ООООООО

Maximum Low–Level Output Voltage, SQ

ООООООО

Maximum Input Leakage

ООООООО

Current Maximum Three–State

Leakage

ООООООО

Current, QA – Q Maximum Quiescent Supply

Current (per Package)

ООООООО

Parameter

H

Test Conditions

Vin = VIH or V

ООООООО

II

I v 20 µA

out

ООООООО

Vin = VIH or VIL|I II

Vin = VIH or V II

I v 20 µA

out

ООООООО

Vin = VIH or VIL|I II

IL

| v 2.4 mA

out

II

outI v

out

| v 2.4 mA

out

II

outI v

out

4.0 mA

Iv 5.2 mA

4.0 mA

Iv 5.2 mA

Vin = VCC or GND

ООООООО

Output in High–Impedance State Vin = VIL or V

ООООООО

V

= VCC or GND

out

IH

Vin = VCC or GND l

= 0 µA

ООООООО

out

2.0

ÎÎ

4.5

6.0

ÎÎ

3.0

4.5

6.0

ÎÎ

2.0

4.5

ÎÎ

6.0

3.0

4.5

ÎÎ

6.0

ÎÎ

6.0

ÎÎ

6.0

ÎÎ

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

CC

V

– 55 to

25_C

1.9

ÎÎ

4.4

5.9

ÎÎ

2.98

3.98

5.48

ÎÎ

0.1

ÎÎ

0.1

0.26

ÎÎ

0.26

± 0.1

ÎÎ

± 0.5

ÎÎ

4.0

ÎÎ

v

85_C

1.9

Î

4.4

5.9

Î

2.34

3.84

5.34

Î

0.1

Î

0.1

0.33

Î

0.33

± 1.0

Î

± 5.0

Î

40

Î

v

125_C

1.9

ÎÎ

4.4

5.9

ÎÎ

2.2

3.7

5.2

ÎÎ

0.1

ÎÎ

0.1

0.4

ÎÎ

0.4

± 1.0

ÎÎ

± 10

ÎÎ

160

ÎÎ

Unit

Î

µA

Î

µA

Î

µA

Î

V

AC ELECTRICAL CHARACTERISTICS (C

ÎÎÎ

Symbol

f

max

ÎÎÎ

t

,

PLH

t

PHL

ÎÎÎ

t

PHL

ÎÎÎ

t

,

PLH

t

ÎÎÎ

PHL

ÎÎÎ

t

,

PLZ

t

PHZ

ÎÎÎ

t

,

PZL

t

PZH

ÎÎÎ

t

,

TLH

t

THL

ÎÎÎ

ОООООООООООООО

Parameter

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 7)

ОООООООООООООО

Maximum Propagation Delay, Shift Clock to SQ

(Figures 1 and 7)

ОООООООООООООО

Maximum Propagation Delay, Reset to SQ

ОООООООООООООО

(Figures 2 and 7)

ОООООООООООООО

Maximum Propagation Delay, Latch Clock to QA – Q

(Figures 3 and 7)

ОООООООООООООО

Maximum Propagation Delay, Output Enable to QA – Q

(Figures 4 and 8)

ОООООООООООООО

Maximum Propagation Delay, Output Enable to QA – Q

(Figures 4 and 8)

ОООООООООООООО

Maximum Output Transition Time, QA – Q

(Figures 3 and 7)

ОООООООООООООО

= 50 pF, Input tr = tf = 6.0 ns)

L

H

V

CC

ÎÎ

V

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

ÎÎ

3.0

4.5

ÎÎ

6.0

2.0

3.0

ÎÎ

4.5

ÎÎ

6.0

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

4.5

ÎÎ

6.0

Guaranteed Limit

– 55 to

ÎÎ

25_C

6.0 15

ÎÎ

30 35

ÎÎ

140 100

ÎÎ

28 24

ÎÎ

145

ÎÎ

100

29

ÎÎ

25

140 100

ÎÎ

28

ÎÎ

24

150 100

ÎÎ

30 26

ÎÎ

135

90

ÎÎ

27 23

ÎÎ

60 23 12

ÎÎ

10

v

Î

85_C

4.8 10

Î

24 28

Î

175 125

Î

35 30

Î

180

Î

125

36

Î

31

175 125

Î

35

Î

30

190 125

Î

38 33

Î

170 110

Î

34 29

Î

75 27 15

Î

13

ÎÎ

v

125_C

4.0

8.0

ÎÎ

20 24

ÎÎ

210 150

ÎÎ

42 36

ÎÎ

220

ÎÎ

150

44

ÎÎ

38

210 150

ÎÎ

42

ÎÎ

36

225 150

ÎÎ

45 38

ÎÎ

205 130

ÎÎ

41 35

ÎÎ

90 31 18

ÎÎ

15

Î

Unit

MHz

Î

ns

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3

MC74HC595A

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

AC ELECTRICAL CHARACTERISTICS (C

= 50 pF, Input tr = tf = 6.0 ns)

L

Guaranteed Limit

Symbol

t

,

TLH

t

ÎÎÎ

THL

ÎÎÎ

C

in

C

out

Parameter

Maximum Output Transition Time, SQ

(Figures 1 and 7)

ОООООООООООООО

H

Maximum Input Capacitance Maximum Three–State Output Capacitance (Output in

High–Impedance State), QA – Q

H

V

2.0

3.0

ÎÎ

4.5

ÎÎ

6.0 — —

CC

V

– 55 to

25_C

75 27

ÎÎ

15

ÎÎ

13 10 15

v

85_C

95 32

Î

19

Î

16 10 15

v

125_C

110

36

ÎÎ

22

ÎÎ

19 10 15

Unit

Î

pF pF

ns

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Package)*

*Used to determine the no–load dynamic power consumption: PD = CPD V

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (Input t

= tf = 6.0 ns)

r

2

f + ICC VCC. For load considerations, see Chapter 2 of the

CC

300

pF

Guaranteed Limit

Symbol

ÎÎÎ

t

su

ÎÎÎ

t

su

ÎÎÎ

t

h

ÎÎÎ

t

rec

ÎÎÎ

t

w

ÎÎÎ

t

w

ÎÎÎ

t

w

ÎÎÎ

tr, t

f

ÎÎÎ

ОООООООООООООО

Parameter

Minimum Setup Time, Serial Data Input A to Shift Clock

(Figure 5)

ОООООООООООООО

Minimum Setup Time, Shift Clock to Latch Clock

(Figure 6)

ОООООООООООООО

Minimum Hold Time, Shift Clock to Serial Data Input A

ОООООООООООООО

(Figure 5)

ОООООООООООООО

Minimum Recovery Time, Reset Inactive to Shift Clock

ОООООООООООООО

(Figure 2)

ОООООООООООООО

Minimum Pulse Width, Reset

(Figure 2)

ОООООООООООООО

Minimum Pulse Width, Shift Clock

(Figure 1)

ОООООООООООООО

Minimum Pulse Width, Latch Clock

(Figure 6)

ОООООООООООООО

Maximum Input Rise and Fall Times

(Figure 1)

ОООООООООООООО

V

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

4.5

ÎÎ

6.0

2.0

ÎÎ

3.0

4.5

ÎÎ

6.0

2.0

ÎÎ

3.0

4.5

ÎÎ

6.0

2.0

3.0

ÎÎ

4.5

ÎÎ

6.0

2.0

3.0

ÎÎ

4.5

ÎÎ

6.0

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

CC V

25_C to

– 55_C

ÎÎ

50 40

ÎÎ

10

9.0

ÎÎ

75 60 15

ÎÎ

13

5.0

ÎÎ

5.0

ÎÎ

5.0 50

ÎÎ

40 10

ÎÎ

9.0 60

45

ÎÎ

12

ÎÎ

10 50

40

ÎÎ

10

ÎÎ

9.0 50

40

ÎÎ

10

9.0

ÎÎ

1000

800

ÎÎ

500 400

ÎÎ

v

85_C

Î

65 50

Î

13 11

Î

95 70 19

Î

16

5.0

Î

5.0

Î

5.0 65

Î

50 13

Î

11 75

60

Î

15

Î

13 65

50

Î

13

Î

11 65

50

Î

13 11

Î

1000

800

Î

500 400

Î

v

125_C

ÎÎ

75 60

ÎÎ

15 13

ÎÎ

110

80 22

ÎÎ

19

5.0

ÎÎ

5.0

ÎÎ

5.0 75

ÎÎ

60 15

ÎÎ

13 90

70

ÎÎ

18

ÎÎ

15 75

60

ÎÎ

15

ÎÎ

13 75

60

ÎÎ

15 13

ÎÎ

1000

800

ÎÎ

500 400

ÎÎ

Unit

Î

ns

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4

MC74HC595A

FUNCTION TABLE

Inputs Resulting Function

Serial

Operation

Reset shift register L X X L, H, ↓ L L U L U Shift data into shift

register Shift register remains

unchanged Transfer shift register

contents to latch register

Latch register remains unchanged

Enable parallel outputs X X X X L * ** * Enabled Force outputs into high

impedance state

SR = shift register contents D = data (L, H) logic level ↑ = Low–to–High * = depends on Reset and Shift Clock inputs LR = latch register contents U = remains unchanged ↓ = High–to–Low ** = depends on Latch Clock input

Reset

Input

A

H D ↑ L, H, ↓ L D SRA;

H X L, H, ↓ L, H, ↓ L U U U U

H X L, H, ↓ ↑ L U SRN LR

X X X L, H, ↓ L * U * U

X X X X H * ** * Z

Shift

Clock

Latch Clock

Output Enable

Shift

Register

Contents

SRN SR

N+1

Latch

Register

Contents

U SRG SR

N

Serial

Output

SQ

H

U SR

Parallel

Outputs

QA – Q

U

N

H

PIN DESCRIPTIONS

INPUTS A (Pin 14)

Serial Data Input. The data on this pin is shifted into the

8–bit serial shift register.

CONTROL INPUTS Shift Clock (Pin 11)

Shift Register Clock Input. A low– to–high transition on this input causes the data at the Serial Input pin to be shifted into the 8–bit shift register.

Reset (Pin 10)

Active–low , Asynchronous, Shift Register Reset Input. A low on this pin resets the shift register portion of this device only. The 8–bit latch is not affected.

Latch Clock (Pin 12)

Storage Latch Clock Input. A low–to–high transition on this input latches the shift register data.

Output Enable (Pin 13)

Active–low Output Enable. A low on this input allows the data from the latches to be presented at the outputs. A high on this input forces the outputs (QA–QH) into the high–impedance state. The serial output is not affected by this control unit.

OUTPUTS QA – QH (Pins 15, 1, 2, 3, 4, 5, 6, 7)

Noninverted, 3–state, latch outputs.

SQH (Pin 9)

Noninverted, Serial Data Output. This is the output of the eighth stage of the 8–bit shift register. This output does not have three–state capability .

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5

MC74HC595A

SWITCHING WAVEFORMS

SHIFT

CLOCK

OUTPUT

SQ

CLOCK

QA–Q

OUTPUTS

H

LATCH

50%

t

w

50%

t

rec

50%

V

CC

GND

V

CC

GND

50%

10%

90%

50%

90%

t

r

t

w

1/f

t

PLH

t

TLH

max

t

PHL

f

V

t

THL

CC

GND

RESET

OUTPUT

SQ

SHIFT

CLOCK

t

PHL

H

Figure 1. Figure 2.

V

50%

t

PLHtPHL

90%

H

50%

10%

t

TLHtTHL

CC

GND

Figure 3.

OUTPUT

ENABLE

OUTPUT Q

50%

t

PZL

50%

t

PZHtPHZ

50%

t

PLZ

Figure 4.

10%

90%

CC

GND HIGH

IMPEDANCE V

OL

V

OH

HIGH IMPEDANCE

VALID

SERIAL

INPUT A

SWITCH

CLOCK

50%

t

su

50%

Figure 5.

TEST POINT

OUTPUT

DEVICE UNDER

TEST

*Includes all probe and jig capacitance

Figure 7. Figure 8.

V

SHIFT

V

CC

GND

t

h

V

CC

GND

CLOCK

LATCH

CLOCK

50%

t

su

50%

t

w

CC

GND

V

CC

GND

Figure 6.

TEST CIRCUITS

TEST POINT

CONNECT TO VCC WHEN TESTING t CONNECT TO GND WHEN TESTING t

PLZ

PHZ

AND t

PZL

PZH

.

CL*

DEVICE UNDER

TEST

OUTPUT

*Includes all probe and jig capacitance

1 kΩ

CL*

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6

MC74HC595A

EXPANDED LOGIC DIAGRAM

OUTPUT ENABLE

LATCH

CLOCK

SERIAL

DATA

INPUT A

13

12

14

D

Q

SR

A

R

Q

D

SR

B

R

Q

D

SR

C

R

Q

D

SR

D

R

Q

D

SR

E

R

DQ

LR

A

DQ

LR

B

DQ

LR

C

DQ

LR

D

DQ

LR

E

15

Q

A

1

Q

B

2

Q

C

3

Q

D

PARALLEL

DATA

OUTPUTS

4

Q

E

SHIFT

CLOCK

RESET

Q

D

SR

F

R

Q

D

SR

G

R

Q

D

11

10

SR

H

R

DQ

LR

F

DQ

LR

G

DQ

LR

H

5

Q

F

6

Q

G

7

Q

H

9

OUTPUT SQ

SERIAL

DATA

H

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7

SHIFT

CLOCK

SERIAL DATA

INPUT A

RESET

LATCH

CLOCK

OUTPUT

ENABLE

Q

MC74HC595A

TIMING DIAGRAM

A

B

C

D

Q

SERIAL DATA

OUTPUT SQ

Q

E

Q

F

G

H

NOTE: implies that the output is in a high–impedance

state.

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8

–A

–

916

B

18

F

C

S

H

G

1

–A

–

D

16 PL

K

M M

916

–B

–

8

G

K

–T

SEATING

–

PLANE

16 PL

D

0.25 (0.010) T B A

M

MC74HC595A

P ACKAGE DIMENSIONS

PDIP–16

N SUFFIX

CASE 648–08

ISSUE R

L

SEATING

–T

PLANE

–

J

TA0.25 (0.010)

SOIC–16

D SUFFIX

CASE 751B–05

ISSUE J

P 8 PL

0.25 (0.010) B

C

S S

M M

R X 45°

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

INCHES MILLIMETERS

MIN MINMAX MAX

DIM

A B C D F G

M

H J K L M S

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

5. DIMENSION D DOES NOT INCLUDE DAMBAR

F

J

0.770

0.740

0.270

0.250

0.175

0.145

0.021

0.015

0.070

0.040

0.100 BSC

0.050 BSC

0.015

0.008

0.130

0.110

0.305

0.295 10°

0°

0.040

0.020

Y14.5M, 1982.

MOLD PROTRUSION. PER SIDE. PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES

MIN MINMAX MAX

DIM

A

9.80

B

3.80

C

1.35

D

0.35

F

0.40

1.27 BSC 0.050 BSC

G J

0.19

K

0.10

M

0°

P

5.80

R

0.25

18.80

10.00

4.00

1.75

0.49

1.25

0.25

6.20

0.50

6.35

3.69

0.39

1.02

0.21

2.80

7.50

0.51

7°

0°

19.55

6.85

4.44

0.53

1.77

2.54 BSC

1.27 BSC

0.38

3.30

7.74 10°

1.01

0.386

0.150

0.054

0.014

0.016

0.008

0.004 0°

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.244

0.019

7°

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9

0.10 (0.004)

–T–

SEATING PLANE

L

U0.15 (0.006) T

PIN 1 IDENT.

U0.15 (0.006) T

D

S

2X L/2

S

MC74HC595A

P ACKAGE DIMENSIONS

TSSOP–16

DT SUFFIX

CASE 948F–01

T

U

B

–U–

ISSUE O

S

J

N

H

J1

F

DETAIL E

K

K1

SECTION N–N

0.25 (0.010)

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.

INCHESMILLIMETERS

–W–

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C ––– 1.20 ––– 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

____

16X REFK

0.10 (0.004) V

16

1

M

9

8

A

–V–

C

G

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10

Notes

MC74HC595A

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11

MC74HC595A

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

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