Datasheet MC74VHC4052D, MC74VHC4052DR2, MC74VHC4052DT, MC74VHC4052DTR2, MC74VHC4051DR2 Datasheet (MOTOROLA)

MC74VHC4051, MC74VHC4052, MC74VHC4053

Analog Multiplexers / Demultiplexers

High–Performance Silicon–Gate CMOS

The MC74VHC4051, MC74VHC4052 and MC74VHC4053 utilize silicon–gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE).

The VHC4051, VHC4052 and VHC4053 are identical in pinout to the high–speed HC4051A, HC4052A and HC4053A, and the metal–gate MC14051B, MC14052B and MC14053B. The Channel–Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off.

The Channel–Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs.

These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal–gate CMOS analog switches.

• Fast Switching and Propagation Speeds

• Low Crosstalk Between Switches

• Diode Protection on All Inputs/Outputs

• Analog Power Supply Range (V

• Digital (Control) Power Supply Range (V

• Improved Linearity and Lower ON Resistance Than Metal–Gate

Counterparts

• Low Noise

• Chip Complexity: VHC4051 — 184 FET s or 46 Equivalent Gates

VHC4052 — 168 FET s or 42 Equivalent Gates VHC4053 — 156 FET s or 39 Equivalent Gates

– VEE) = 2.0 to 12.0 V

CC

– GND) = 2.0 to 6.0 V

CC

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MARKING

DIAGRAMS

16

SO–16

16

1

16

See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet.

D SUFFIX

CASE 751B

TSSOP–16

DT SUFFIX

1

ORDERING INFORMATION

CASE 948F

A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week

VHC405x

AWLYWW

1

16

VHC 405x

ALYW

1

 Semiconductor Components Industries, LLC, 1999

March, 2000 – Rev . 3

1 Publication Order Number:

MC74VHC4051/D

MC74VHC4051, MC74VHC4052, MC74VHC4053

LOGIC DIAGRAM

MC74VHC4051

Single–Pole, 8–Position Plus Common Off

13

X0

14

X1

15

ANALOG

INPUTS/

OUTPUTS

CHANNEL

SELECT

INPUTS

X2 X3 X4 X5 X6 X7

ENABLE

12

1 5 2 4

11

A

10

B

9

C

6

PIN 16 = V PIN 7 = V PIN 8 = GND

MULTIPLEXER/

DEMULTIPLEXER

CC

EE

3

COMMON

X

OUTPUT/ INPUT

FUNCTION TABLE – MC74VHC4051

Control Inputs

Select

Enable

L L L L L L L L

H

CBA

L

L L L L

H H H H X

L

H

L

H

L

H

L

H

X

ON Channels

X0 X1 X2 X3 X4 X5 X6 X7

NONE

X = Don’t Care

Pinout: MC74VHC4051 (Top View)

V

X2 X1 X0 X3 A B C

CC

1516 14 13 12 11 10

21 34567

9

8

Double–Pole, 4–Position Plus Common Off

ANALOG

INPUTS/OUTPUTS

CHANNEL-SELECT

INPUTS

X0 X1 X2 X3

Y0 Y1 Y2 Y3

ENABLE

LOGIC DIAGRAM

MC74VHC4052

12 14 15 11

1 5 2 4

10

A

9

B

6

X SWITCH

Y SWITCH

13

X

3

Y

PIN 16 = V PIN 7 = V

EE

PIN 8 = GND

COMMON OUTPUTS/INPUTS

CC

FUNCTION TABLE – MC74VHC4052

Control Inputs

Select

Enable

L L L L

H

BA

L

H H H X

L H X

ON Channels

Y0 Y1 Y2 Y3

NONE

X = Don’t Care

Pinout: MC74VHC4052 (Top View)

X2 X1 X X0 X3 A B

V

CC

1516 14 13 12 11 10

21 34567

Y0 Y2 Y Y3 Y1 Enable VEEGND

X0 X1 X2 X3

9

8

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2

MC74VHC4051, MC74VHC4052, MC74VHC4053

LOGIC DIAGRAM

MC74VHC4053

Triple Single–Pole, Double–Position Plus Common Off

12

X0

ANALOG

INPUTS/OUTPUTS

CHANNEL-SELECT

INPUTS

X1

Y0 Y1

ENABLE

13

2 1

5

Z0

3

Z1

11

A

10

B

9

C

6

X SWITCH

Y SWITCH

Z SWITCH

NOTE: This device allows independent control of each switch. Channel–Select Input A controls the X–Switch, Input B controls the Y–Switch and Input C controls the Z–Switch

14

X

15

Y

4

Z

PIN 16 = V PIN 7 = V

EE

PIN 8 = GND

CC

COMMON OUTPUTS/INPUTS

FUNCTION TABLE – MC74VHC4053

Control Inputs

Select

Enable

L L L L L L L L

H

CBA

L

L L L L

H H H H

X

L

H

L

H

L

H

L

H

X

ON Channels

Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1

X = Don’t Care

Pinout: MC74VHC4053 (Top View)

Y X X1 X0 A B C

V

CC

1516 14 13 12 11 10

Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1

NONE

X0 X1 X0 X1 X0 X1 X0 X1

9

21 34567

8

Y1 Y0 Z1 Z Z0 Enable VEEGND

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3

MC74VHC4051, MC74VHC4052, MC74VHC4053

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î ÎÎ ÎÎ

ÎÎ

Î

ÎÎ

Î

MAXIMUM RATINGS*

Symbol

V

ÎÎ

V

ÎÎ

Positive DC Supply Voltage (Referenced to GND)

CC

ОООООООООООО

Negative DC Supply Voltage (Referenced to GND)

EE

V

Analog Input Voltage

IS

V

Digital Input Voltage (Referenced to GND)

in I

DC Current, Into or Out of Any Pin

P

Power Dissipation in Still Air, SOIC Package†

D

ОООООООООООО

T

Storage Temperature Range

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C

TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol

V

ÎÎ

V

ÎÎ

V

VIO*

T

tr, t

ÎÎ

*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be

drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

Positive DC Supply Voltage (Referenced to GND)

CC

ООООООООООООО

Negative DC Supply Voltage, Output (Referenced to

EE

GND)

ООООООООООООО

Analog Input Voltage

IS

Digital Input Voltage (Referenced to GND)

in

Static or Dynamic Voltage Across Switch Operating Temperature Range, All Package Types

A

Input Rise/Fall Time VCC = 2.0 V

f

(Channel Select or Enable Inputs) VCC = 3.0 V

ООООООООООООО

Parameter

(Referenced to VEE)

TSSOP Package†

(Referenced to VEE)

VCC = 4.5 V VCC = 6.0 V

Value

– 0.5 to + 7.0

– 0.5 to + 14.0

ÎÎÎ

– 7.0 to + 5.0 VEE – 0.5 to

VCC + 0.5

– 0.5 to VCC + 0.5

± 25

500

ÎÎÎ

450

– 65 to + 150

260

Min

Max

2.0

6.0

Î

2.0

12.0

– 6.0

GND

Î

V

EE

CC

GND

V

CC

1.2

– 55

+ 125

0

1000

0

800

Î

0

500

0

400

Î

Unit

Î

mA

mW

Î

_

Unit

Î

_

ns

Î

This device contains protection

V

circuitry to guard against damage due to high static voltages or electric fields. However, precautions must

V V

be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

V

should be constrained to the

out

range GND v (Vin or V

Unused inputs must always be

) v VCC.

out

tied to an appropriate logic voltage level (e.g., either GND or VCC).

C

Unused outputs must be left open.

C

V

V V V

C

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4

MC74VHC4051, MC74VHC4052, MC74VHC4053

V

CC

Î

DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) V

Symbol Parameter Condition

V

Minimum High–Level Input

IH

Voltage, Channel–Select or

Ron = Per Spec 2.0

Enable Inputs

V

Maximum Low–Level Input

IL

Voltage, Channel–Select or

Ron = Per Spec 2.0

Enable Inputs

I

CC

Maximum Input Leakage Current,

in

Channel–Select or Enable Inputs Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND, VEE = – 6.0 V

Channel Select, Enable and VIS = VCC or GND; VEE = GND VIO = 0 V VEE = – 6.0

DC ELECTRICAL CHARACTERISTICS Analog Section

V

CC

Symbol

ÎÎ

R

on

ÎÎ

∆R

on

ÎÎ

I

off

I

on

ООООООО

Parameter

Maximum “ON” Resistance

ООООООО

Maximum Difference in “ON”

ООООООО

Resistance Between Any Two Channels in the Same Package

ООООООО

Maximum Off–Channel Leakage Current, Any One Channel

Maximum Off–ChannelVHC4051 Leakage Current, VHC4052 Common Channel VHC4053

Maximum On–ChannelVHC4051 Leakage Current, VHC4052 Channel–to–Channel VHC4053

Test Conditions

ОООООО

Vin = VIL or V VIS = VCC to V

ОООООО

IS v 2.0 mA (Figures 1, 2)

Vin = VIL or V

ОООООО

VIS = VCC or V (Endpoints)

ОООООО

IS v 2.0 mA (Figures 1, 2) Vin = VIL or V

ОООООО

VIS = 1/2 (VCC – VEE) IS v 2.0 mA

ОООООО

IH

EE

IH

EE

IH

Vin = VIL or VIH; VIO = VCC – VEE; Switch Off (Figure 3)

Vin = VIL or VIH; VIO = VCC – VEE; Switch Off (Figure 4)

Vin = VIL or VIH; Switch–to–Switch = VCC – VEE; (Figure 5)

V

Î

3.0

4.5

Î

4.5

6.0

3.0

Î

4.5

Î

6.0

3.0

Î

4.5

Î

6.0

6.0 – 6.0 0.1 0.5 1.0

6.0

= GND, Except Where Noted

EE

V

3.0

4.5

6.0

3.0

4.5

6.0

Guaranteed Limit

–55 to 25°C ≤85°C ≤125°C

1.50

2.10

3.15

4.20

0.5

0.9

1.35

1.8

1.50

2.10

3.15

4.20

0.5

0.9

1.35

1.8

6.0 ± 0.1 ± 1.0 ± 1.0 µA

6.0

1 4

10 40

Guaranteed Limit

V

Î

– 4.5 – 6.0

Î

– 4.5

Î

– 6.0

Î

– 4.5

Î

– 6.0

– 6.0 – 6.0 – 6.0

EE V

0.0

– 55 to

25_C

ÎÎ

200 160

ÎÎ

120 100

150

ÎÎ

110

90

ÎÎ

80 40

ÎÎ

20 10

ÎÎ

10

0.2

0.1

0.2

0.1

v

85_C

ÎÎ

240 200

ÎÎ

150 125

180

ÎÎ

140 120

ÎÎ

100

50

ÎÎ

25 15

ÎÎ

12

2.0

1.0

2.0

1.0

v

125_C

ÎÎ

1.50

2.10

3.15

4.20

0.5

0.9

1.35

1.8

40 80

320 280 170 140

230 190 140 115

80 40 18 14

4.0

2.0

4.0

2.0

Unit

V

µA

Unit

Ω

µA

5

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MC74VHC4051, MC74VHC4052, MC74VHC4053

V

CC

AC CHARACTERISTICS (C

Symbol Parameter

t

,

PLH

t

PHL

t

PLH

t

PHL

t

PLZ

t

PHZ

t

PZL

t

PZH

C

Maximum Propagation Delay , Channel–Select to Analog Output (Figure 9)

,

Maximum Propagation Delay , Analog Input to Analog Output (Figure 10)

,

Maximum Propagation Delay , Enable to Analog Output (Figure 11)

,

Maximum Propagation Delay , Enable to Analog Output (Figure 11)

Maximum Input Capacitance, Channel–Select or Enable Inputs 10 10 10 pF

in

Maximum Capacitance Analog I/O 35 35 35 pF

I/O

(All Switches Off) Common O/I: VHC4051

= 50 pF, Input tr = tf = 6 ns)

L

V

–55 to 25°C ≤85°C ≤125°C

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

VHC4052 VHC4053

Feedthrough 1.0 1.0 1.0

Guaranteed Limit

270

90 59 45

40 25 12 10

160

70 48 39

245

115

49 39

130

80 50

320 110

79 65

60 30 15 13

200

95 63 55

315 145

69 58

130

80 50

350 125

85 75

70 32 18 15

220

110

76 63

345 155

83 67

130

80 50

Unit

ns

C

PD

*Used to determine the no–load dynamic power consumption: PD = CPD V

Power Dissipation Capacitance (Figure 13)* VHC4051

VHC4052 VHC4053

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

45 80 45

2

f + ICC VCC.

CC

pF

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6

MC74VHC4051, MC74VHC4052, MC74VHC4053

V

CC

V

EE

Obtain 0dB

V

f

R

,

ON

RESISTANCE

OHMS

180

ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)

Symbol Parameter Condition

BW Maximum On–Channel Bandwidth

or Minimum Frequency Response (Figure 6)

— Off–Channel Feedthrough Isolation

(Figure 7)

— Feedthrough Noise.

Channel–Select Input to Common I/O (Figure 8)

— Crosstalk Between Any Two

Switches (Figure 12) (Test does not apply to VHC4051)

THD Total Harmonic Distortion

(Figure 14)

*Limits not tested. Determined by design and verified by qualification.

fin = 1MHz Sine Wave; Adjust fin Voltage to

Frequency Until dB Meter Reads –3dB; RL = 50Ω, CL = 10pF

fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at V

Vin ≤ 1MHz Square Wave (tr = tf = 6ns); Adjust RL at Setup so that IS = 0A; Enable = GND RL = 600Ω, CL = 50pF

fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at V

fin = 1kHz, RL = 10kΩ, CL = 50pF THD = THD

m at

fin = 10kHz, RL = 600Ω, CL = 50pF

fin = 1.0MHz, RL = 50Ω, CL = 10pF

fin = 10kHz, RL = 600Ω, CL = 50pF

fin = 1.0MHz, RL = 50Ω, CL = 10pF

measured

; Increase

OS

IS

RL = 10kΩ, CL = 10pF

IS

– THD VIS = 4.0VPP sine wave VIS = 8.0VPP sine wave

VIS = 11.0VPP sine wave

in

source

V

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

V

–2.25 –4.50 –6.00

Limit*

25°C

‘51 ‘52 ‘53 80

95 95 95

–50 –50 –50

–40 –40 –40

25 105 135

35 145 190

–50 –50 –50

–60 –60 –60

0.10

0.08

0.05

120 120 120

80 80

Unit

MHz

mV

dB

PP

dB

%

300

)

250

(

200

150

100

on

50

0

0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V

125°C

25°C

–55°C

EE

160 140

120 100

80 60

, ON RESISTANCE (OHMS)

on

40

R

20

0

0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.25

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V

2.0

125°C

25°C

–55°C

2.5 2.75 3.0 EE

Figure 1a. T ypical On Resistance, VCC – VEE = 2.0 V Figure 1b. Typical On Resistance, VCC – VEE = 3.0 V

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7

120

R

,

ON

RESISTANCE

OHMS

105

0

60

MC74VHC4051, MC74VHC4052, MC74VHC4053

)

100

(

80

60

40

on

20

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V

125°C

25°C

–55°C

EE

90

75

60

45

, ON RESISTANCE (OHMS)

30

on

R

15

0

0 1.0 2.0 3.0 4.0 5.0 6.03.5 4.5 5.5

0.5 1.5 2.5 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V

125°C

25°C

–55°C

EE

Figure 1c. T ypical On Resistance, VCC – VEE = 4.5 V Figure 1d. T ypical On Resistance, VCC – VEE = 6.0 V

8 70 60 50 40 30

, ON RESISTANCE (OHMS)

20

on

R

10

0

–4.5 –3.5

–2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V

125°C

25°C

–55°C

EE

50

40

30

20

, ON RESISTANCE (OHMS)

on

R

10

0

–6.0 –5.0

125°C

25°C

–55°C

–4.0 –3.0 –2.0 2.0 3.0 4.0 5.0 6.0

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V

–1.0

1.00 EE

Figure 1e. T ypical On Resistance, VCC – VEE = 9.0 V Figure 1f. Typical On Resistance, VCC – VEE = 12.0 V

PLOTTER

PROGRAMMABLE

POWER SUPPLY

+–

ANALOG IN COMMON OUT

MINI COMPUTER

UNDER TEST

GND

DEVICE

DC ANALYZER

V

CC

V

EE

Figure 1. On Resistance T est Set–Up

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MC74VHC4051, MC74VHC4052, MC74VHC4053

T

V

CC

V

EE

V

CC

A

NC

V

IH

V

EE

6 7 8

16

OFF OFF

CC

COMMON O/I

Figure 2. Maximum Off Channel Leakage Current,

Any One Channel, Test Set–Up

V

CC

V

EE

V

CC

A

ON

OFF

ANALOG I/O

16

COMMON O/I

V

CC

N/C

V

CC

V

CC

OFF OFF

16

COMMON O/I

V

EE

V

CC

ANALOG I/O

V

IH

V

EE

6 7 8

Figure 3. Maximum Off Channel Leakage Current,

Common Channel, Test Set–Up

V

CC

0.1µF

f

in

16

ON

OS

CL*

dB

METER R

L

V

IL

V

EE

6 7 8

Figure 4. Maximum On Channel Leakage Current,

Channel to Channel, T est Set–Up

V

f

in

VIL or V

0.1µF

V

IH

EE

V

IS

R

L

6 7 8

CHANNEL SELECT

*Includes all probe and jig capacitance

OFF

CC

16

OS

CL*

dB

METER R

L

Figure 6. Off Channel Feedthrough Isolation,

T est Set–Up

6 7 8

V

EE

*Includes all probe and jig capacitance

Figure 5. Maximum On Channel Bandwidth,

T est Set–Up

V

CC

16

11

V

CC

GND

Vin ≤ 1 MHz tr = tf = 6 ns

R

L

ANALOG I/O

R

L

V

EE

ON/OFF OFF/ON

6 7 8

CHANNEL SELECT

*Includes all probe and jig capacitance

Figure 7. Feedthrough Noise, Channel Select to

Common Out, Test Set–Up

COMMON O/I

R

L

V

CC

TEST POIN

CL*

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9

CHANNEL

SELECT

ANALOG

OUT

t

PLH

50%

MC74VHC4051, MC74VHC4052, MC74VHC4053

V

CC

V

CC

ANALOG I/O

GND

t

PHL

50%

*Includes all probe and jig capacitance

V

CC

16

ON/OFF OFF/ON

6 7 8

CHANNEL SELECT

COMMON O/I

TEST POINT

CL*

Figure 9a. Propagation Delays, Channel Select

to Analog Out

ANALOG

OUT

IN

t

PLH

50%

Figure 10a. Propagation Delays, Analog In

to Analog Out

t

ENABLE

ANALOG

OUT

ANALOG

OUT

f

50%

t

PZL

t

PZH

t

PHZ

t

r

PLZ

Figure 11a. Propagation Delays, Enable to

Analog Out

90% 50% 10%

10%

90%

t

PHL

V

CC

GND HIGH

IMPEDANCE

V

OL

V

OH

HIGH IMPEDANCE

Figure 8b. Propagation Delay , Test Set–Up Channel

Select to Analog Out

V

CC

16

V

CC

GND

ANALOG I/O

ON

6 7 8

*Includes all probe and jig capacitance

COMMON O/I

Figure 9b. Propagation Delay , Test Set–Up

Analog In to Analog Out

POSITION 1 WHEN TESTING t

1 2

V

CC

1 2

POSITION 2 WHEN TESTING t

ANALOG I/O

ENABLE

ON/OFF

6 7 8

V

CC

16

Figure 10b. Propagation Delay , Test Set–Up

Enable to Analog Out

PHZ PLZ

AND t

1kΩ

TEST POINT

CL*

PZH

PZL

TEST POINT

CL*

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10

MC74VHC4051, MC74VHC4052, MC74VHC4053

V

IS

R

0.1µF

V

EE

L

R

L

6 7 8

*Includes all probe and jig capacitance

f

in

Figure 11. Crosstalk Between Any Two

ON

OFF

16

R

L

CL*

V

OS

R

L

CL*

Figure 12. Power Dissipation Capacitance,

Switches, T est Set–Up

V

CC

ANALOG I/O

V

EE

ON/OFF OFF/ON

6 7 8

CHANNEL SELECT

Test Set–Up

CC

A

16

COMMON O/I

11

NC

V

CC

dB

–100

0 –10 –20 –30 –40 –50

–60 –70 –80 –90

FUNDAMENTAL FREQUENCY

DEVICE SOURCE

1.0 2.0 3.125 FREQUENCY (kHz)

V

IS

0.1µF

f

in

6 7 8

V

EE

V

CC

16

ON

*Includes all probe and jig capacitance

V

OS

TO

DISTORTION

CL*

METER

R

L

Figure 14a. T otal Harmonic Distortion, Test Set–Up Figure 13b. Plot, Harmonic Distortion

APPLICATIONS INFORMATION

The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example:

VCC = +5V = logic high

GND = 0V = logic low

The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is ten volts. Therefore, using the configuration of Figure 15, a maximum analog signal of ten volts peak–to–peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and

outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch.

Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that:

VCC – GND = 2 to 6 volts

VEE – GND = 0 to –6 volts

VCC – VEE = 2 to 12 volts

and VEE ≤ GND

When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure

16. These diodes should be able to absorb the maximum anticipated current surges during clipping.

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11

MC74VHC4051, MC74VHC4052, MC74VHC4053

+5V

–5V

+5V

V

EE

V

16

CC

D

x

D

x

V

EE

V

ANALOG

SIGNAL

–5V

V

+5V

16

ANALOG

ON

6 7 8

SIGNAL

11 10

TO EXTERNAL CMOS CIRCUITRY 0 to 5V DIGITAL SIGNALS

9

+5V

–5V

CC

D

x

ON/OFF

D

x

V

EE

7 8

V

EE

Figure 14. Application Example Figure 15. External Germanium or

Schottky Clipping Diodes

ANALOG

V

EE

SIGNAL

ON/OFF

6 7 8

+5V

16

ANALOG

SIGNAL

R*R R

11 10

9

* 2K ≤ R ≤ 10K

+5V

V

EE

LSTTL/NMOS

CIRCUITRY

+5V

V

EE

ANALOG

V

EE

SIGNAL

ON/OFF

6 7 8

16

11

10

9

+5V

ANALOG

SIGNAL

HCT

BUFFER

a. Using Pull–Up Resistors b. Using HCT Interface

+5V

V

EE

+5V

LSTTL/NMOS

CIRCUITRY

ENABLE

Figure 16. Interfacing LSTTL/NMOS to CMOS Inputs

11

A

10

B

9

C

6

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

13

X0

14

X1

15

X2

12

X3

1

X4

5

X5

2

X6

4

X7

Figure 18. Function Diagram, VHC4051

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12

3

X

MC74VHC4051, MC74VHC4052, MC74VHC4053

ENABLE

10

A

9

B

6

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

12

X0

14

X1

15

X2

11

X3

13

X

1

Y0

5

Y1

2

Y2

4

Y3

3

Y

ENABLE

Figure 19. Function Diagram, VHC4052

11

A

10

B

9

C

6

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

13

X1

12

X0

14

X

1

Y1

2

Y0

15

Y

3

Z1

5

Z0

4

Z

Figure 20. Function Diagram, VHC4053

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13

MC74VHC4051, MC74VHC4052, MC74VHC4053

ORDERING & SHIPPING INFORMATION

Device Package Shipping

MC74VHC4051D SOIC–16 48 Units / Rail MC74VHC4051DR2 SOIC–16 2500 Units / Tape & Reel MC74VHC4051DT TSSOP–16 96 Units / Rail MC74VHC4051DTR2 TSSOP–16 2500 Units / Tape & Reel MC74VHC4052D SOIC–16 48 Units / Rail MC74VHC4052DR2 SOIC–16 2500 Units / Tape & Reel MC74VHC4052DT TSSOP–16 96 Units / Rail MC74VHC4052DTR2 TSSOP–16 2500 Units / Tape & Reel MC74VHC4053D SOIC–16 48 Units / Rail MC74VHC4053DR2 SOIC–16 2500 Units / Tape & Reel MC74VHC4053DT TSSOP–16 96 Units / Rail MC74VHC4053DTR2 TSSOP–16 2500 Units / Tape & Reel

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14

–T

SEATING

–

PLANE

MC74VHC4051, MC74VHC4052, MC74VHC4053

P ACKAGE DIMENSIONS

SOIC–16

D SUFFIX

CASE 751B–05

ISSUE J

–A

–

916

–B

P 8 PL

1

–

8

0.25 (0.010) B

M M

G

K

R X 45°

F

C

J

16 PL

D

0.25 (0.010) T B A

M

S S

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES

MIN MINMAX MAX

DIM

A

9.80

B

3.80

C

1.35

D

0.35

F

0.40

G J

0.19

K

0.10

M

0°

P

5.80

R

0.25

1.27 BSC 0.050 BSC

10.00

4.00

1.75

0.49

1.25

0.25

6.20

0.50

0.386

0.393

0.150

0.157

0.054

0.068

0.014

0.019

0.016

0.049

0.008

0.009

0.004

0.009

0°

0.229

0.010

0.244

0.019

7°

0.10 (0.004)

–T–

SEATING PLANE

L

U0.15 (0.006) T

PIN 1 IDENT.

U0.15 (0.006) T

D

S

2X L/2

S

TSSOP–16 DT SUFFIX

CASE 948F–01

ISSUE O

16X REFK

T

U

B

–U–

S

H

N

S

J

N

DETAIL E

J1

0.25 (0.010)

F

K

K1

SECTION N–N

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.

INCHESMILLIMETERS

–W–

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C ––– 1.20 ––– 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC M 0 8 0 8

____

0.10 (0.004) V

16

1

M

9

8

A

–V–

C

G

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15

MC74VHC4051, MC74VHC4052, MC74VHC4053

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

PUBLICATION ORDERING INFORMATION

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ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local Sales Representative.

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MC74VHC4051/D

Datasheet MC74VHC4052D, MC74VHC4052DR2, MC74VHC4052DT, MC74VHC4052DTR2, MC74VHC4051DR2 Datasheet (MOTOROLA)

Specifications and Main Features

Frequently Asked Questions

User Manual