Datasheet MC74VHC157MEL, MC74VHC157ML1, MC74VHC157DTR2, MC74VHC157D, MC74VHC157DR2 Datasheet (MOTOROLA)

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Page 1



SEMICONDUCTOR TECHNICAL DATA

REV 1

 Motorola, Inc. 1997

6/97

  

The MC74VHC157 is an advanced high speed CMOS quad 2–channel multiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

It consists of four 2–input digital multiplexers with common select (S) and enable (E

) inputs. When E is held High, selection of data is inhibited and all

the outputs go Low.

The select decoding determines whether the A or B inputs get routed to the corresponding Y outputs.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.

• High Speed: tPD = 4.1ns (Typ) at VCC = 5V

• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C

• High Noise Immunity: V

NIH

= V

NIL

= 28% V

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

• Designed for 2V to 5.5V Operating Range

• Low Noise: V

OLP

= 0.8V (Max)

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300mA

• ESD Performance: HBM > 2000V; Machine Model > 200V

• Chip Complexity: 82 FETs or 20 Equivalent Gates

EXPANDED LOGIC DIAGRAM

13 15

E S

DATA OUTPUTS

NIBBLE

INPUTS

FUNCTION TABLE

E S Y0 – Y3

A0 – A3, B0 – B3 = the levels of the respective Data–Word Inputs.

L L

X L H

L A0–A3 B0–B3

Inputs

Outputs



PIN ASSIGNMENT

125

GND

D SUFFIX

16–LEAD SOIC PACKAGE

CASE 751B–05

DT SUFFIX

16–LEAD TSSOP PACKAGE

CASE 948F–01

ORDERING INFORMATION

MC74VHCXXXD MC74VHCXXXDT MC74VHCXXXM

SOIC TSSOP SOIC EIAJ

M SUFFIX

16–LEAD SOIC EIAJ PACKAGE

CASE 966–01

Page 2

MC74VHC157

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 1

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

DC Supply Voltage

– 0.5 to + 7.0

DC Input Voltage

– 0.5 to + 7.0

out

DC Output Voltage

– 0.5 to VCC + 0.5

Input Diode Current

– 20

Output Diode Current

± 20

out

DC Output Current, per Pin

± 25

DC Supply Current, VCC and GND Pins

± 50

ОООООООООООО

Power Dissipation in Still Air, SOIC Packages†

TSSOP Package†

ÎÎÎÎ

500 450

stg

Storage Temperature

– 65 to + 150

* Absolute maximum continuous ratings are those values beyond which damage to the device

may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability . Functional operation under absolute–maximum–rated conditions is not implied.

†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C

TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

DC Supply Voltage

2.0

5.5

DC Input Voltage

5.5

out

DC Output Voltage

Operating Temperature

– 40

+ 85

tr, t

Input Rise and Fall Time VCC = 3.3V

VCC = 5.0V00

10020ns/V

DC ELECTRICAL CHARACTERISTICS

ÎÎÎ

TA = 25°C

TA = – 40 to 85°C

Symbol

Parameter

Test Conditions

ÎÎÎ

Min

Typ

Max

Min

Max

Unit

ÎÎ

ÎÎÎÎ

Minimum High–Level Input Voltage

ОООООО

ÎÎÎ

ÎÎ

2.0

3.0 to

5.5

ÎÎ

1.50

VCC x 0.7

ÎÎÎÎÎÎÎ

1.50

VCC x 0.7

ÎÎ

ÎÎÎÎ

Maximum Low–Level Input Voltage

ОООООО

ÎÎÎ

ÎÎ

2.0

3.0 to

5.5

ÎÎ

0.50

VCC x 0.3

ÎÎ

0.50

VCC x 0.3

ÎÎ

ÎÎÎÎ

Minimum High–Level Output Voltage

ОООООО

Vin = VIH or V

IOH = – 50µA

ÎÎÎ

ÎÎ

2.0

3.0

4.5

ÎÎ

1.9

2.9

4.4

2.0

3.0

4.5

ÎÎ

1.9

2.9

4.4

ÎÎ

ÎÎÎÎÎÎÎÎОООООО

Vin = VIH or V

IOH = – 4mA

IOH = – 8mA

ÎÎÎ

ÎÎ

3.0

4.5

ÎÎ

2.58

3.94

ÎÎÎÎÎÎÎ

2.48

3.80

ÎÎ

ÎÎÎÎ

Maximum Low–Level Output Voltage

ОООООО

Vin = VIH or V

IOL = 50µA

ÎÎÎ

ÎÎ

2.0

3.0

4.5

ÎÎ

0.0

ÎÎ

0.1

ÎÎ

0.1

ÎÎ

ÎÎÎÎ

ОООООО

Vin = VIH or V

IOL = 4mA IOL = 8mA

ÎÎÎ

ÎÎ

3.0

4.5

ÎÎ

0.36

ÎÎ

0.44

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Page 3

MC74VHC157

VHC Data – Advanced CMOS Logic DL203 — Rev 1

3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS

Unit

TA = – 40 to 85°C

TA = 25°C

ÎÎÎ

CC V

Test Conditions

Parameter

Symbol

Unit

Max

Min

Max

Typ

Min

ÎÎÎ

CC V

Test Conditions

Parameter

Symbol

ÎÎ

ÎÎÎÎ

Maximum Input Leakage Current

ОООООО

Vin = 5.5 V or GND

ÎÎÎ

ÎÎ

0 to 5.5

ÎÎÎÎÎÎÎ

± 0.1

ÎÎÎÎÎ

± 1.0

µA

ÎÎ

ÎÎÎÎ

Maximum Quiescent Supply Current

ОООООО

Vin = VCC or GND

ÎÎÎ

ÎÎ

5.5

ÎÎÎÎÎÎÎ

4.0

ÎÎÎÎÎ

40.0

µA

AC ELECTRICAL CHARACTERISTICS (Input t

= tf = 3.0ns)

TA = 25°C

TA = – 40 to 85°C

Symbol

Parameter

Test Conditions

Min

Typ

Max

Min

Max

Unit

ÎÎ

PLH

PHL

ОООООО

Maximum Propagation Delay, A or B to Y

ООООООО

VCC = 3.3 ± 0.3 V CL = 15pF

CL = 50pF

ÎÎÎÎ

6.2

8.7

ÎÎ

9.7

13.2

1.0

ÎÎ

11.5

15.0

ÎÎÎООООООÎООООООО

VCC = 5.0 ± 0.5 V CL = 15pF

CL = 50pF

ÎÎÎÎ

4.1

5.6

ÎÎ

6.4

8.4

1.0

ÎÎ

7.5

9.5

PLH

PHL

Maximum Propagation Delay, S to Y

VCC = 3.3 ± 0.3 V CL = 15pF

CL = 50pF

8.4

10.9

13.2

16.7

1.0

15.5

19.0

ÎÎÎООООООÎООООООО

VCC = 5.0 ± 0.5 V CL = 15pF

CL = 50pF

ÎÎÎÎ

5.3

6.8

ÎÎ

8.1

10.1

1.0

ÎÎ

9.5

11.5

ÎÎ

PLH

PHL

ОООООО

Maximum Propagation Delay, E

to Y

ООООООО

VCC = 3.3 ± 0.3 V CL = 15pF

CL = 50pF

ÎÎÎÎ

8.7

11.2

ÎÎ

13.6

17.1

1.0

ÎÎ

16.0

19.5

VCC = 5.0 ± 0.5 V CL = 15pF

CL = 50pF

5.6

7.1

8.6

10.6

1.0

10.0

12.0

Maximum Input Capacitance

Typical @ 25°C, VCC = 5.0V

Power Dissipation Capacitance (Note 1.)

1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I

CC(OPR

)

= CPD  VCC  fin + ICC. CPD is used to determine the no–load dynamic

power consumption; PD = CPD  V

 fin + ICC  VCC.

NOISE CHARACTERISTICS (Input t

= tf = 3.0ns, CL = 50pF, VCC = 5.0V)

TA = 25°C

Symbol Characteristic

Typ Max

Unit

OLP

Quiet Output Maximum Dynamic V

0.3 0.8 V

OLV

Quiet Output Minimum Dynamic V

– 0.3 – 0.8 V

IHD

Minimum High Level Dynamic Input Voltage 3.5 V

ILD

Maximum Low Level Dynamic Input Voltage 1.5 V

Page 4

MC74VHC157

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 1

SWITCHING W AVEFORMS

A, B or S

Figure 1. Switching Waveform

PLH

PHL

GND

50%

50% V

Figure 2. Inverting Switching

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 3. Test Circuit

GND

PHL

PLH

50%

50% V

INPUT

Figure 4. Input Equivalent Circuit

Page 5

MC74VHC157

VHC Data – Advanced CMOS Logic DL203 — Rev 1

5 MOTOROLA

OUTLINE DIMENSIONS

0.25 (0.010) T B A

S S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A B C D F G J K M P R

9.80

3.80

1.35

0.35

0.40

0.19

0.10 0

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

0.25 7

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004 0

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.009 7

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

916

–A

–

–B

–

D 16 PL

–T

–

SEATING

PLANE

R X 45°

P 8 PL

0.25 (0.010) B

M M

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

ÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C ––– 1.20 ––– 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MA TERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.

____

SECTION N–N

SEATING PLANE

IDENT.

PIN 1

DETAIL E

2X L/2

–U–

U0.15 (0.006) T

0.10 (0.004) V

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

Page 6

MC74VHC157

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 1

OUTLINE DIMENSIONS

M SUFFIX

PLASTIC SOIC EIAJ PACKAGE

CASE 966–01

ISSUE O

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059 0

0.70 0.90 0.028 0.035

––– 0.78 ––– 0.031

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MA TERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).

DETAIL P

VIEW P

0.13 (0.005)

0.10 (0.004)

16 9

c D E

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MC74VHC157/D

◊

Datasheet MC74VHC157MEL, MC74VHC157ML1, MC74VHC157DTR2, MC74VHC157D, MC74VHC157DR2 Datasheet (MOTOROLA)

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