Datasheet MC74VHC126D, MC74VHC126MEL, MC74VHC126ML1, MC74VHC126ML2, MC74VHC126DTR2 Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

April, 2000 – Rev. 1

1 Publication Order Number:

MC74VHC126/D

MC74VHC126

Quad Bus Buffer

with 3–State Control Inputs

The MC74VHC126 is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It achieves noninverting high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

The MC74VHC126 requires the 3–state control input (OE) to be set Low to place the output into high impedance.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.

• High Speed: t

PD

= 3.8ns (Typ) at VCC = 5V

• Low Power Dissipation: I

CC

= 4µA (Max) at TA = 25°C

• High Noise Immunity: V

NIH

= V

NIL

= 28% V

CC

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

• Designed for 2V to 5.5V Operating Range

• Low Noise: V

OLP

= 0.8V (Max)

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300mA

• ESD Performance: HBM > 2000V ; Machine Model > 200V

• Chip Complexity: 72 FETs or 18 Equivalent Gates

LOGIC DIAGRAM

Active–High Output Enables

FUNCTION TABLE

VHC126

Inputs Output

AOE Y

HH H LH L XL Z

Y1

Y2

Y4

3

6

8

11

13

12

10

9

4

5

1

2

A1

OE1

A2

OE2

A3

OE3

A4

OE4

Y3

14–LEAD SOIC

D SUFFIX

CASE 751A

http://onsemi.com

14–LEAD TSSOP

DT SUFFIX

CASE 948G

PIN CONNECTION AND

MARKING DIAGRAM (Top View)

Device Package Shipping

ORDERING INFORMATION

MC74VHC126D SOIC 55 Units/Rail MC74VHC126DT TSSOP

96 Units/Rail

14–LEAD SOIC EIAJ

M SUFFIX CASE 965

MC74VHC126M SOIC EIAJ

50 Units/Rail

For detailed package marking information, see the Marking Diagram section on page 5 of this data sheet.

11

12

13

14

8

9

105

4

3

2

1

7

6

OE3

Y4

A4

OE4

V

CC

Y3

A3

OE2

Y1

A1

OE1

GND

Y2

A2

MC74VHC126

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2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage

– 0.5 to + 7.0

V

in

DC Input Voltage

– 0.5 to + 7.0

V

out

DC Output Voltage

– 0.5 to VCC + 0.5

V

I

IK

Input Diode Current

– 20

mA

I

OK

Output Diode Current

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air, SOIC Packages†

TSSOP Package†

ÎÎÎ

Î

500 450

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

* Absolute maximum continuous ratings are those values beyond which damage to the device

may occur. Exposure to these conditions or conditions beyond those indicated may

adversely affect device reliability. Functional operation under absolute–maximum–rated

conditions is not implied. †Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C

TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage

2.0

ÎÎ

5.5

V

in

DC Input Voltage

0

ÎÎ

5.5

V

out

DC Output Voltage

0

ÎÎ

V

CC

V

T

A

Operating Temperature, All Package Types

– 40

ÎÎ

+ 85

_

C

tr, t

f

Input Rise and Fall Time VCC = 3.3V ±0.3V

VCC =5.0V ±0.5V00

ÎÎ

10020ns/V

DC ELECTRICAL CHARACTERISTICS

V

CC

TA = 25°C TA ≤ 85°C TA ≤ 125°C

Symbol Parameter Test Conditions (V) Min Typ Max Min Max Min Max Unit

V

IH

Minimum High–Level Input Voltage

2.0

3.0

4.5

5.5

1.5

2.1

3.15

3.85

1.5

2.1

3.15

3.85

1.5

2.1

3.15

3.85

V

IL

Maximum Low–Level Input Voltage

2.0

3.0

4.5

5.5

0.5

0.9

1.35

1.65

0.5

0.9

1.35

1.65

0.5

0.9

1.35

1.65

V

OH

Minimum High–Level Output Voltage VIN = VIH or V

IL

VIN = VIH or V

IL

IOH = –50µA

2.0

3.0

4.5

1.9

2.9

4.4

2.0

3.0

4.5

1.9

2.9

4.4

1.9

2.9

4.4

V

VIN = VIH or V

IL

IOH = –4mA IOH = –8mA

3.0

4.5

2.58

3.94

2.48

3.80

2.34

3.66

V

OL

Maximum Low–Level Output Voltage VIN = VIH or V

IL

VIN = VIH or V

IL

IOL = 50µA

2.0

3.0

4.5

0.0

0.1

V

VIN = VIH or V

IL

IOL = 4mA IOL = 8mA

3.0

4.5

0.36

0.44

0.52

V

I

OZ

Maximum 3–State Leakage Current

VIN = VIH or V

IL

V

OUT

= VCC or GND

5.5 ±0.25 ±2.5 ±2.5 µA

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

MC74VHC126

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3

I

IN

Maximum Input Leakage Current

VIN = 5.5V or GND 0 to

5.5

±0.1 ±1.0 ±1.0 µA

I

CC

Maximum Quiescent Supply Current

VIN = VCC or GND 5.5 4.0 40 40 µA

AC ELECTRICAL CHARACTERISTICS (Input t

r

= tf = 3.0ns)

TA = 25°C

TA = ≤ 85°C

TA = ≤ 125°C

Symbol

Parameter

Test Conditions

Min

Typ

Max

Min

Max

Min

Max

Unit

ÎÎ

Î

t

PLH

,

t

PHL

ООООО

Î

Maximum Propagation Delay,

ООООООО

Î

VCC = 3.3 ± 0.3V CL = 15pF

CL = 50pF

ÎÎÎ

Î

5.6

8.1

Î

8.0

11.5

Î

1.0

Î

9.5

13.0

Î

1.0

Î

12.0

15.0

ns

A to Y

VCC = 5.0 ± 0.5V CL = 15pF

CL = 50pF

3.8

5.3

5.5

7.5

1.0

6.5

8.5

1.0

8.5

10.5

ÎÎ

Î

t

PZL

,

t

PZH

ООООО

Î

Maximum Output Enable TIme,

ООООООО

Î

VCC = 3.3 ± 0.3V CL = 15pF RL = 1kΩ CL = 50pF

ÎÎÎ

Î

5.4

7.9

Î

8.0

11.5

Î

1.0

Î

9.5

13.0

Î

1.0

Î

11.5

15.0

ns

ÎÎÎООООО

Î

OE to Y

ООООООО

Î

VCC = 5.0 ± 0.5V CL = 15pF RL = 1kΩ CL = 50pF

ÎÎÎ

Î

3.6

5.1

Î

5.1

7.1

Î

1.0

Î

6.0

8.0

Î

1.0

Î

7.5

9.5

t

PLZ

,

t

PHZ

Maximum Output Disable Time,

VCC = 3.3 ± 0.3V CL = 50pF RL = 1kΩ

9.5

13.2

1.0

15.0

1.0

18.0

ns

ÎÎÎООООО

Î

OE to Y

ООООООО

Î

VCC = 5.0 ± 0.5V CL = 50pF RL = 1kΩ

ÎÎÎ

Î

6.1

Î

8.8

Î

1.0

Î

10.0

Î

1.0

Î

12.0

ÎÎ

Î

t

OSLH

,

t

OSHL

ООООО

Î

Output–to–Output Skew

ООООООО

Î

VCC = 3.3 ± 0.3V CL = 50pF (Note 1.)

ÎÎÎÎÎ

Î

1.5

ÎÎÎ

Î

1.5

ÎÎÎ

Î

1.5

ns

VCC = 5.0 ± 0.5V CL = 50pF (Note 1.)

1.0

ÎÎ

Î

C

in

ООООО

Î

Maximum Input Capacitance

ОООООООÎÎÎÎ

Î

4

Î

10

ÎÎÎ

Î

10

ÎÎÎ

Î

10

pF

ÎÎ

Î

ÎÎ

Î

C

out

ООООО

Î

ООООО

Î

Maximum Three–State Output Capacitance (Output in High Impedance State)

ООООООО

Î

ООООООО

Î

6

Î

pF

Typical @ 25°C, VCC = 5.0V

C

PD

Power Dissipation Capacitance (Note 2.)

15

pF

1. Parameter guaranteed by design. t

OSLH

= |t

PLHm

– t

PLHn

|, t

OSHL

= |t

PHLm

– t

PHLn

|.

2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I

CC(OPR

)

= CPD  VCC  fin + ICC/4 (per buf fer). CPD is used to determine the

no–load dynamic power consumption; PD = CPD  V

CC

2

 fin + ICC  VCC.

NOISE CHARACTERISTICS (Input t

r

= tf = 3.0ns, CL = 50pF, VCC = 5.0V)

TA = 25°C

Symbol Characteristic

Typ Max

Unit

V

OLP

Quiet Output Maximum Dynamic V

OL

0.3 0.8 V

V

OLV

Quiet Output Minimum Dynamic V

OL

– 0.3 – 0.8 V

V

IHD

Minimum High Level Dynamic Input Voltage 3.5 V

V

ILD

Maximum Low Level Dynamic Input Voltage 1.5 V

MC74VHC126

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4

SWITCHING W AVEFORMS

Figure 1. Figure 2.

Y

50%

50% V

CC

50% V

CC

V

CC

GND HIGH

IMPEDANCE

VOL + 0.3V VOH – 0.3V

Y

OE

t

PZLtPLZ

t

PZHtPHZ

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE UNDER

TEST

OUTPUT

Figure 3. Test Circuit

*Includes all probe and jig capacitance

Figure 4. Test Circuit

OUTPUT

TEST POINT

CL *

1 kΩ

CONNECT TO VCC WHEN TESTING t

PLZ

AND t

PZL.

CONNECT TO GND WHEN TESTING t

PHZ

AND t

PZH.

DEVICE

UNDER

TEST

HIGH IMPEDANCE

50%

50% V

CC

V

CC

GND

t

PLH

t

PHL

A

Figure 5. Input Equivalent Circuit

INPUT

MC74VHC126

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5

MARKING DIAGRAMS

(Top View)

14–LEAD SOIC

D SUFFIX

CASE 751A

14–LEAD TSSOP

DT SUFFIX

CASE 948G

1314 12 11 10 9 8

21 34567

1314 12 11 10 9 8

21 34567

14–LEAD SOIC EIAJ

M SUFFIX CASE 965

1314 12 11 10 9 8

21 34567

VHC126

VHC

AWLYWW*

126

ALYW*

*See Applications Note #AND8004/D for date code and traceability information.

VHC126

AWLYWW*

MC74VHC126

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6

P ACKAGE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A B C D F G J K M P R

8.55

3.80

1.35

0.35

0.40

0.19

0.10 0°

5.80

0.25

8.75

4.00

1.75

0.49

1.25

0.25

0.25 7°

6.20

0.50

0.337

0.150

0.054

0.014

0.016

0.008

0.004 0°

0.228

0.010

0.344

0.157

0.068

0.019

0.049

0.009

0.009 7°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

–A–

–B–

P 7 PL

G

C

K

SEATING PLANE

D 14 PL

M

J

R

X 45°

1

7

814

0.25 (0.010) T B A

M

S S

B0.25 (0.010)

M M

F

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948G–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C ––– 1.20 ––– 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V

S

T

L

–U–

SEATING PLANE

0.10 (0.004)

–T–

SECTION N–N

DETAIL E

J

J1

K

K1

ÉÉ

DETAIL E

F

M

–W–

0.25 (0.010)

8

14

7

1

PIN 1 IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

–V–

14X REFK

N

MC74VHC126

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7

P ACKAGE DIMENSIONS

M SUFFIX

PLASTIC SOIC EIAJ PACKAGE

CASE 965–01

ISSUE O

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059 0

0.70 0.90 0.028 0.035

––– 1.42 ––– 0.056

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).

0.13 (0.005)

M

0.10 (0.004)

D

Z

E

1

14 8

7

e

A

b

VIEW P

c

L DETAIL P

M

A

b c D E e

0.50

M

Z

MC74VHC126

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8

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without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

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MC74VHC126/D

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Datasheet MC74VHC126D, MC74VHC126MEL, MC74VHC126ML1, MC74VHC126ML2, MC74VHC126DTR2 Datasheet (MOTOROLA)

Specifications and Main Features

Frequently Asked Questions

User Manual