Datasheet MC74LVX573M, MC74LVX573DTR2, MC74LVX573DW, MC74LVX573DT, MC74LVX573DWR2 Datasheet (Motorola)

Page 1

SEMICONDUCTOR TECHNICAL DATA
 "  !    
The MC74LVX573 is an advanced high speed CMOS octal latch with 3–state outputs. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.
This 8–bit D–type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state.

LVX
LOW–VOLTAGE CMOS
High Speed: t
Low Power Dissipation: I
= 6.4ns (Typ) at VCC = 3.3V
PD
= 4µA (Max) at TA = 25°C
CC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Low Noise: V
= 0.8V (Max)
OLP
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
O0 O1 O2 O3 O4 O5 O6 O7 LE
V
CC
1920 18 17 16 15 14
21 34567
OE
D0 D1 D2 D3 D4 D5 D6 D7 GND
Figure 1. 20–Lead Pinout (Top View)
13
12
11
9
8
10
20–LEAD TSSOP PACKAGE
20–LEAD SOIC EIAJ PACKAGE
PIN NAMES
Pins
OE LE D0–D7 O0–O7
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
DT SUFFIX
CASE 948E–02
M SUFFIX
CASE 967–01
Function
Output Enable Input Latch Enable Input Data Inputs 3–State Latch Outputs
6/97
Motorola, Inc. 1997
1
REV 0
Page 2
MC74LVX573
OE
LE
D0
1
11
2
nLE D
Q
19
O0
D1
D2
D3
D4
D5
D6
D7
3
4
5
6
7
8
9
nLE D
nLE D
nLE D
nLE D
nLE D
nLE D
nLE D
Q
Q
Q
Q
Q
Q
Q
18
O1
17
O2
16
O3
15
O4
14
O5
13
O6
12
O7
Figure 2. Logic Diagram
INPUTS OUTPUTS
OE LE Dn On
L L
L L
L L X NC Hold; Read Latch H L X Z Hold; Disabled Outputs H
H H
H
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Latch Enable High–to–Low Transition; L = Low V oltage Level; l = Low Voltage Level One Setup T ime Prior to the Latch Enable High–to–Low Transition; NC = No Change, State Prior to the Latch Enable High–to–Low T ransition; X = High or Low V oltage Level or Transitions are Acceptable; Z = High Impedance State; For ICC Reasons DO NOT FLOAT Inputs
H H
L L
H H
L L
H
L h
l
H
L h
l
H
L
H
L
Z Z
Z Z
Transparent (Latch Disabled); Read Latch
Transparent (Latch Disabled); Disabled Outputs
Latched (Latch Enabled); Disabled Outputs
OPERATING MODE
Latched (Latch Enabled) Read Latch
MOTOROLA LCX DATA
2
BR1339 — REV 3
Page 3
MC74LVX573
ОООООО
ОООООО
V
CC
Î
Î
ОООООО
Î
Î
Î
Î
Î
ОООООО
Î
Î
Î
Î
Î
Î
Î
ОООООО
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ОООООО
Î
Î
Î
Î
Î
ОООООО
Î
Î
ОООООО
Î
Î
Î
Î
ОООООО
MAXIMUM RATINGS*
Symbol
V V V I I I I P T
CC in
out IK OK out CC
D
stg
DC Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation Storage Temperature
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
V
out
T
A
t/V
DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time
Parameter
Parameter
Value
–0.5 to +7.0 –0.5 to +7.0
–0.5 to VCC +0.5
–20
±20 ±25 ±75
180
–65 to +150
Min
2.0 0 0
–40
0
Max
3.6
5.5
V
CC
+85 100
Unit
V V
V mA mA mA mA
mW
_
C
Unit
V
V
V
_
C
ns/V
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IH
ÎÎ
V
IL
ÎÎ
V
OH
ÎÎ
ÎÎ
V
OL
ÎÎ
I
in
I
OZ
ÎÎ
I
CC
Parameter
High–Level Input Voltage
ОООООО
Low–Level Input Voltage
ОООООО
High–Level Output Voltage
ОООООО
(Vin = VIH or VIL)
ОООООО
Low–Level Output Voltage (Vin = VIH or VIL)
ОООООО
Input Leakage Current Maximum Three–State
Leakage Current
ОООООО
Quiescent Supply Current
ОООООÎÎ
ОООООÎÎ
IOH = –50µA
ООООО
IOH = –50µA IOH = –4mA
ООООО
IOL = 50µA IOL = 50µA
ООООО
IOL = 4mA Vin = 5.5V or GND Vin = VIL or V
V
ООООО
Vin = VCC or GND
Test Conditions
= VCC or GND
out
IH
V
2.0
3.0
3.6
2.0
3.0
3.6
2.0
3.0
3.0
2.0
3.0
3.0
3.6
3.6
3.6
V
Î
Î
Î
Î
TA = 25°C
Min
Typ
Max
1.5
2.0
ÎÎ
2.4
ÎÎÎÎÎÎÎ
0.5
ÎÎÎÎÎÎÎ
1.9
ÎÎ
2.9
2.58
ÎÎ
2.0
Î
3.0
Î
0.0
0.0
ÎÎÎÎ
0.8
0.8
ÎÎ
ÎÎ
0.1
0.1
ÎÎ
0.36
±0.1
±0.25
ÎÎÎÎÎÎÎ
4.0
TA = – 40 to 85°C
Min
Max
1.5
2.0
2.4
ÎÎÎÎ
0.5
ÎÎÎÎÎ
0.8
0.8
1.9
ÎÎ
2.9
2.48
ÎÎ
ÎÎ
ÎÎ
0.1
0.1
ÎÎÎÎÎ
0.44
±1.0 ±2.5
ÎÎÎÎÎ
40.0
Unit
V
V
Î
V
Î
Î
V
Î
µA µA
Î
µA
LCX DATA BR1339 — REV 3
3 MOTOROLA
Page 4
MC74LVX573
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
AC ELECTRICAL CHARACTERISTICS (Input t
Symbol
t
PLH
t
ÎÎ
PHL
ÎÎÎООООООÎООООООО
t
PLH
ÎÎ
t
PHL
ÎÎÎООООООÎООООООО
t
PZL
t
PZH
ÎÎ
t
PLZ
ÎÎ
t
PHZ
ÎÎÎООООООÎООООООО
t
OSHL
t
OSLH
Propagation Delay
,
LE to O
,
Propagation Delay D to O
Output Enable Time
,
OE
Output Disable Time
,
OE
Output–to–Output Skew (Note NO TAG)
Parameter
ОООООО
ОООООО
to O
ОООООО
ОООООО
to O
= tf = 3.0ns)
r
Test Conditions
VCC = 2.7V CL = 15pF
ООООООО
CL = 50pF
VCC = 3.3 ± 0.3V CL = 15pF
CL = 50pF
VCC = 2.7V CL = 15pF
ООООООО
CL = 50pF
VCC = 3.3 ± 0.3V CL = 15pF
CL = 50pF
VCC = 2.7V CL = 15pF RL = 1k CL = 50pF
ООООООО
VCC = 3.3 ± 0.3V CL = 15pF RL = 1k CL = 50pF
VCC = 2.7V CL = 50pF
ООООООО
RL = 1k VCC = 3.3 ± 0.3V CL = 50pF
RL = 1k VCC = 2.7V CL = 50pF
VCC = 3.3 ±0.3V CL = 50pF
TA = 25°C
Min
Typ
8.2
ÎÎÎÎ
10.7
6.4
ÎÎÎÎ
ÎÎÎÎ
8.9
7.6
10.1
5.9
ÎÎÎÎ
8.4
7.8
ÎÎÎÎ
10.3
6.1
8.6
12.1
ÎÎÎÎ
10.1
ÎÎÎÎ
Max
15.6
19.1
ÎÎ
10.1
13.6
ÎÎ
14.5
ÎÎ
18.0
9.3
ÎÎ
12.8
15.0
18.5
ÎÎ
9.7
13.2
19.1
ÎÎ
13.6
ÎÎ
1.5
1.5
TA = – 40 to 85°C
Min
1.0
1.0
Î
1.0
1.0
Î
1.0
Î
1.0
1.0
Î
1.0
1.0
1.0
Î
1.0
1.0
1.0
Î
1.0
Î
Max
18.5
22.0
ÎÎ
12.0
15.5
ÎÎ
17.5
ÎÎ
21.0
11.0
ÎÎ
14.5
18.5
22.0
ÎÎ
12.0
15.5
22.0
ÎÎ
15.5
ÎÎ
1.5
1.5
Unit
ns
ns
ns
ns
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (t guaranteed by design.
) or LOW–to–HIGH (t
OSHL
OSLH
); parameter
CAPACITIVE CHARACTERISTICS
TA = 25°C
Symbol
C
in
C
out
C
PD
Input Capacitance Maximum Three–State Output Capacitance Power Dissipation Capacitance (Note NO T AG)
Parameter
Min
Typ
4 6
29
Max
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I dynamic power consumption; PD = CPD V
NOISE CHARACTERISTICS (Input t
= tf = 3.0ns, CL = 50pF, VCC = 3.3V , Measured in SOIC Package)
r
CC
2
fin + ICC VCC.
CC(OPR
= CPD VCC fin + ICC/8 (per latch). CPD is used to determine the no–load
)
Symbol Characteristic
V V
V V
OLP OLV
IHD
Quiet Output Maximum Dynamic V Quiet Output Minimum Dynamic V
OL
OL
Minimum High Level Dynamic Input Voltage 2.0 V Maximum Low Level Dynamic Input Voltage 0.8 V
ILD
TA = – 40 to 85°C
Min
10
TA = 25°C
Typ Max
0.5 0.8 V
–0.5 –0.8 V
Max
10
Unit
pF pF pF
Unit
MOTOROLA LCX DATA
4
BR1339 — REV 3
Page 5
MC74LVX573
TIMING REQUIREMENTS (Input t
Symbol Parameter Test Conditions
t
w(h)
t
su
t
Minimum Pulse Width, LE VCC = 2.7V
Minimum Setup Time, D to LE VCC = 2.7V
Minimum Hold Time, D to LE VCC = 2.7V
h
= tf = 3.0ns)
r
VCC = 3.3 ±0.3V
VCC = 3.3 ±0.3V
VCC = 3.3 ±0.3V
SWITCHING WAVEFORMS
V
t
PHL
CC
GND
D
t
PLH
O
50%
50% VCC
Figure 3. Figure 4.
LE
TA = – 40
TA = 25°C
Typ Limit Limit
6.5
5.0
5.0
3.5
1.5
1.5
t
w
50%
t
PLH
O
50% VCC
t
PHL
to 85°C
7.5
5.0
5.0
3.5
1.5
1.5
V
CC
GND
Unit
ns
ns
ns
OE
50%
t
t
PLZ
PZL
O
O
50% VCC
t
PZHtPHZ
50% VCC
Figure 5. Figure 6.
TEST POINT
OUTPUT
DEVICE UNDER
TEST
*Includes all probe and jig capacitance
VOL +0.3V
VOL –0.3V
CL*
V
CC
GND HIGH
IMPEDANCE
HIGH IMPEDANCE
TEST CIRCUITS
DEVICE
UNDER
TEST
VALID
D
LE
OUTPUT
*Includes all probe and jig capacitance
50%
t
su
TEST POINT
1 k
CL*
t
h
50%
CONNECT TO VCC WHEN TESTING t CONNECT TO GND WHEN TESTING t
PLZ
PHZ
AND t
AND t
V
CC
GND
V
CC
GND
PZL
PZH
.
.
Figure 7. Propagation Delay T est Circuit Figure 8. Three–State T est Circuit
LCX DATA BR1339 — REV 3
5 MOTOROLA
Page 6
MC74LVX573
20
1
18X
–A–
11
–B–
10
D20X
0.010 (0.25) B
M
S
A
T
C
G
K
S
–T–
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
P10X
M
M
0.010 (0.25)
SEATING PLANE
B
J
F
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.
DIM MIN MAX MIN MAX
A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
R
X 45
_
J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 M 0 7 0 7
__
P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029
INCHESMILLIMETERS
__
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X REFK
S
U0.15 (0.006) T
0.10 (0.004) V
M
S
U
T
S
K
2X
L/2
L
PIN 1 IDENT
110
1120
B
JJ1
–U–
N
S
U0.15 (0.006) T
A
K1
SECTION N–N
0.25 (0.010)
M
–V–
N
F
DETAIL E
C
G
H
DETAIL E
0.100 (0.004)
SEATING
–T–
PLANE
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.
INCHES
6.60 0.260
–W–
MILLIMETERS
DIMAMIN MAX MIN MAX
6.40 0.252
B 4.30 4.50 0.169 0.177 C 1.20 0.047
––– –––
D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC M 0 8 0 8
____
MOTOROLA LCX DATA
6
BR1339 — REV 3
Page 7
OUTLINE DIMENSIONS
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 967–01
ISSUE O
20
110
11
H
E
E
Z
D
e
0.13 (0.005)
A
b
M
A
0.10 (0.004)
VIEW P
1
L
E
_
M
L
DETAIL P
MC74LVX573
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
Q
1
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE. 4 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY. 5 THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
c
DIM MIN MAX MIN MAX
––– 2.05 ––– 0.081
A
A
0.05 0.20 0.002 0.008
1
0.35 0.50 0.014 0.020
b
0.18 0.27 0.007 0.011
c
12.35 12.80 0.486 0.504
D
5.10 5.45 0.201 0.215
E
1.27 BSC 0.050 BSC
e
H
7.40 8.20 0.291 0.323
E
0.50 0.85 0.020 0.033
L
L
1.10 1.50 0.043 0.059
E
0
M
_
Q
0.70 0.90 0.028 0.035
1
––– 0.81 ––– 0.032
Z
10
INCHES
0
_
_
10
_
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MC74LVX573/D
LCX DATA
7 MOTOROLA
BR1339 — REV 3
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