Datasheet MC74LVX240DWR2, MC74LVX240DTR2, MC74LVX240DW Datasheet (MOTOROLA)

Page 1

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SEMICONDUCTOR TECHNICAL DATA

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#! ! ! "!

The MC74L VX240 is an advanced high speed CMOS inverting 3–state octal bus buffer and has two active low output enables. It is also designed to work with 3–state memory address drivers, etc. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.

• High Speed: t

• Low Power Dissipation: I

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

• Low Noise: V

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300mA

• ESD Performance: HBM > 2000V; Machine Model > 200V

= 4.3ns (Typ) at VCC = 3.3V

= 4µA (Max) at TA = 25°C

= 0.8V (Max)

OLP

2OE

1O0 2D0 1O1 2D1 1O2 2D2 1O3 2D3

1920 18 17 16 15 14



LVX

LOW–VOLTAGE CMOS

DW SUFFIX

20–LEAD SOIC PACKAGE

CASE 751D–04

1OE

1D0

1D1

1D2

1D3

21 34567

1D0 2O0 1D1 2O1 1D2 2O2 1D3 2O3 GND

1OE

Figure 1. 20–Lead Pinout (Top View)

1O0

1O1

1O2

1O3

Figure 2. Logic Diagram

2OE

2D0

2D1

2D2

2D3

20–LEAD TSSOP PACKAGE

20–LEAD SOIC EIAJ PACKAGE

2O0

2O1

2O2

2O3

PIN NAMES

Pins

nOE

1Dn, 2Dn

1On

, 2On

FUNCTION TABLE

INPUTS OUTPUTS

1OE, 2OE 1Dn, 2Dn 1On, 2On

L L

DT SUFFIX

CASE 948E–02

M SUFFIX

CASE 967–01

Function

Output Enable Inputs Data Inputs 3–State Outputs

L H X

L H Z

6/97

 Motorola, Inc. 1997

REV 0

Page 2

MC74LVX240

ОООООО

MAXIMUM RATINGS*

Symbol

V V V I I I I P T

CC in

out IK OK out CC

stg

DC Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation Storage Temperature

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or

conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is

not implied.

RECOMMENDED OPERATING CONDITIONS

Symbol

out

∆t/∆V

DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time

Parameter

Value

–0.5 to +7.0 –0.5 to +7.0

–0.5 to VCC +0.5

–20

±20 ±25 ±75

180

–65 to +150

Min

2.0 0 0

–40

Max

3.6

5.5

+85 100

Unit

V V

V mA mA mA mA

Unit

ns/V

DC ELECTRICAL CHARACTERISTICS

Symbol

ÎÎ

High–Level Output Voltage

Low–Level Output Voltage

Parameter

High–Level Input Voltage

ОООООО

Low–Level Input Voltage

ОООООО

(Vin = VIH or VIL)

ОООООО

(Vin = VIH or VIL)

ОООООО

Input Leakage Current Maximum Three–State

Leakage Current

ОООООО

Quiescent Supply Current

ОООООÎÎ

IOH = –50µA

ООООО

IOH = –50µA IOH = –4mA

ООООО

IOL = 50µA IOL = 50µA

ООООО

IOL = 4mA Vin = 5.5V or GND Vin = VIL or V

ООООО

Vin = VCC or GND

Test Conditions

= VCC or GND

out

2.0

3.0

3.6

2.0

3.0

3.6

2.0

3.0

2.0

3.0

3.6

TA = 25°C

Min

Typ

Max

1.5

2.0

ÎÎ

2.4

ÎÎÎÎÎÎÎ

0.5

ÎÎÎÎÎÎÎ

1.9

ÎÎ

2.9

2.58

ÎÎ

2.0

3.0

0.0

ÎÎÎÎ

0.8

ÎÎ

0.1

ÎÎ

0.36

±0.1

±0.25

ÎÎÎÎÎÎÎ

4.0

TA = – 40 to 85°C

Min

Max

1.5

2.0

2.4

ÎÎÎÎ

0.5

ÎÎÎÎÎ

0.8

1.9

ÎÎ

2.9

2.48

ÎÎ

0.1

ÎÎÎÎÎ

0.44

±1.0 ±2.5

ÎÎÎÎÎ

40.0

Unit

µA µA

µA

MOTOROLA LVX Data — Low–Voltage CMOS Logic

BR1492 — Rev 0

Page 3

MC74LVX240

AC ELECTRICAL CHARACTERISTICS (Input t

Symbol

PLH

ÎÎ

PHL

ÎÎÎООООООÎООООООО

PZL

ÎÎ

PZH

ÎÎÎООООООÎООООООО

PLZ

PHZ

ÎÎ

Propagation Delay

Input to Output

Output Enable Time to

High and Low Level

Output Disable Time From

High and Low Level

Parameter

ОООООО

= tf = 3.0ns)

Test Conditions

VCC = 2.7V CL = 15pF

ООООООО

CL = 50pF

VCC = 3.3 ± 0.3V CL = 15pF

CL = 50pF

VCC = 2.7V CL = 15pF

ООООООО

RL = 1kΩ CL = 50pF VCC = 3.3 ± 0.3V CL = 15pF

RL = 1kΩ CL = 50pF VCC = 2.7V CL = 50pF

RL = 1kΩ

ООООООО

VCC = 3.3 ± 0.3V CL = 50pF

TA = 25°C

Min

Typ

5.7

ÎÎÎÎ

8.2

4.3

ÎÎÎÎ

6.8

7.1

9.6

5.5

ÎÎÎÎ

8.0

11.6

ÎÎÎÎ

9.7

Max

10.1

13.6

ÎÎ

6.2

9.7

ÎÎ

13.8

ÎÎ

17.3

8.8

ÎÎ

12.3

16.0

ÎÎ

11.4

TA = – 40 to 85°C

Min

1.0

Max

12.5

16.0

ÎÎ

7.5

11.0

ÎÎ

16.5

ÎÎ

20.0

10.5

ÎÎ

14.0

19.0

ÎÎ

13.0

Unit

RL = 1kΩ

OSHL

ÎÎ

OSLH

Output–to–Output Skew

ОООООО

(Note 1.)

VCC = 2.7V CL = 50pF

ООООООО

VCC = 3.3 ±0.3V CL = 50pF

ÎÎÎÎÎÎÎ

1.5

ÎÎÎÎ

1.5

1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (t guaranteed by design.

) or LOW–to–HIGH (t

OSHL

OSLH

); parameter

CAPACITIVE CHARACTERISTICS

TA = 25°C

Symbol

out

Input Capacitance Maximum Three–State Output Capacitance Power Dissipation Capacitance (Note 2.)

Parameter

Min

Typ

4 6

Max

2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I dynamic power consumption; PD = CPD  V

 fin + ICC  VCC.

CC(OPR

= CPD  VCC  fin + ICC/8 (per bit). CPD is used to determine the no–load

)

TA = – 40 to 85°C

Min

Max

Unit

pF pF pF

NOISE CHARACTERISTICS (Input t

= tf = 3.0ns, CL = 50pF, VCC = 3.3V , Measured in SOIC Package)

Symbol Characteristic

V V

OLP OLV

IHD

Quiet Output Maximum Dynamic V Quiet Output Minimum Dynamic V

Minimum High Level Dynamic Input Voltage 2.0 V Maximum Low Level Dynamic Input Voltage 0.8 V

ILD

TA = 25°C

Typ Max

Unit

0.5 0.8 V

–0.5 –0.8 V

LVX Data — Low–Voltage CMOS Logic BR1492 — Rev 0

3 MOTOROLA

Page 4

MC74LVX240

1Dn, 2Dn

PHL

1On

, 2On

SWITCHING WAVEFORMS

50%

50% V

PLH

GND

1OE, 2OE

1On, 2On

50%

Figure 3. Figure 4.

TEST CIRCUITS

PZL

50% V

PZHtPHZ

50% V

PLZ

GND HIGH

IMPEDANCE

VOL +0.3V VOH –0.3V

HIGH IMPEDANCE

TEST POINT

OUTPUT

DEVICE UNDER

TEST

*Includes all probe and jig capacitance

CL*

DEVICE

UNDER

TEST

TEST POINT

OUTPUT

*Includes all probe and jig capacitance

1 k

CL*

CONNECT TO VCC WHEN

Ω

TESTING t

CONNECT TO GND WHEN

TESTING t

Figure 5. Propagation Delay T est Circuit Figure 6. Three–State T est Circuit

PLZ

PHZ

AND t

PZL

PZH

MOTOROLA LVX Data — Low–Voltage CMOS Logic

BR1492 — Rev 0

Page 5

MC74LVX240

OUTLINE DIMENSIONS

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D–04

ISSUE E

–A–

D20X

0.010 (0.25) B

18X

P10X

0.010 (0.25)

–B–

X 45

SEATING

–T–

PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019

F 0.50 0.90 0.020 0.035

G 1.27 BSC 0.050 BSC

J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 M 0 7 0 7

P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029

INCHESMILLIMETERS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948E–02

ISSUE A

20X REFK

U0.15 (0.006) T

0.10 (0.004) V

L/2

PIN 1 IDENT

110

1120

JJ1

–U–

U0.15 (0.006) T

SECTION N–N

0.25 (0.010)

–V–

DETAIL E

0.100 (0.004)

SEATING

–T–

PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.

INCHES

6.60 0.260

–W–

MILLIMETERS

DIMAMIN MAX MIN MAX

6.40 0.252

B 4.30 4.50 0.169 0.177 C 1.20 0.047

––– –––

D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC M 0 8 0 8

____

LVX Data — Low–Voltage CMOS Logic BR1492 — Rev 0

5 MOTOROLA

Page 6

MC74LVX240

110

0.13 (0.005)

OUTLINE DIMENSIONS

M SUFFIX

PLASTIC SOIC EIAJ PACKAGE

CASE 967–01

ISSUE O

NOTES:

1 DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DIMENSIONS D AND E DO NOT INCLUDE MOLD

DETAIL P

0.10 (0.004)

VIEW P

FLASH OR PROTRUSIONS AND ARE MEASURED

AT THE PARTING LINE. MOLD FLASH OR

PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)

PER SIDE. 4 TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY. 5 THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

––– 2.05 ––– 0.081

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

12.35 12.80 0.486 0.504

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0.70 0.90 0.028 0.035

––– 0.81 ––– 0.032

INCHES

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MOTOROLA LVX Data — Low–Voltage CMOS Logic

◊

MC74LVX240/D

BR1492 — Rev 0

Datasheet MC74LVX240DWR2, MC74LVX240DTR2, MC74LVX240DW Datasheet (MOTOROLA)

Specifications and Main Features

Frequently Asked Questions

User Manual