Datasheet MC74LVQ646DT, MC74LVQ646DW, MC74LVQ646SD Datasheet (Motorola)



SEMICONDUCTOR TECHNICAL DATA

1

REV 0

 Motorola, Inc. 1995

12/95

%" #" 
"  !$ !" 
 !$

"" $ "

The MC74LVQ646 is a high performance, non–inverting octal
transceiver/registered transceiver operating from a 2.7 to 3.6V supply.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. The MC74LVQ646 is suitable for memory
address driving and all TTL level bus oriented transceiver applications.

Data on the A or B bus will be clocked into the registers as the
appropriate clock pin goes from a LOW–to–HIGH logic level. Output
Enable (OE

) and DIR pins are provided to control the transceiver outputs.
In the transceiver mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select controls (SBA,
SAB) can multiplex stored and real–time (transparent mode) data. The
direction control (DIR) determines which bus will receive data when the
enable OE

is active LOW. In the isolation mode (OE HIGH), A data may
be stored in the B register or B data may be stored in the A register. Only
one of the two buses, A or B, may be driven at one time.

• Designed for 2.7 to 3.6V V

CC

Operation – Ideal for Low Power/Low

Noise Applications

• Guaranteed Simultaneous Switching Noise Level and Dynamic

Threshold Performance

• Guaranteed Skew Specifications

• Guaranteed Incident Wave Switching into 75Ω

• Low Static Supply Current (10µA) Substantially Reduces System Power

Requirements

• Latchup Performance Exceeds 500mA

• ESD Performance: Human Body Model >2000V

Pinout: 24–Lead Package (Top View)

2324 22 21 20 19 18

21 3 4 5 6 7

V

CC

17

8

16

9

15

10

CBA SBA OE

B0 B1 B2 B3 B4 B5

CAB SAB DIR A0 A1 A2 A3 A4 A5 A6

14

11

13

12

B6 B7

A7 GND



LVQ

DW SUFFIX

PLASTIC SOIC
CASE 751E–04

DT SUFFIX

PLASTIC TSSOP

CASE 948H–01

24

1

24

1

SD SUFFIX

PLASTIC SSOP

CASE 940D–03

24

1

LOW–VOLTAGE CMOS

OCTAL TRANSCEIVER/

REGISTERED TRANSCEIVER

PIN NAMES

Function

Side A Inputs/Outputs
Side B Inputs/Outputs
Clock Pulse Inputs
Select Control Inputs
Output Enable Inputs

Pins

A0–A7
B0–B7
CAB, CBA
SAB, SBA
DIR, OE

LOGIC DIAGRAM

C

D

Q

OE

DIR

CBA

SBA

SAB

CAB

C

D

Q

A0

B0

1 of 8 Channels

To 7 Other Channels

1
3

21

22

2

23

MC74LVQ646

MOTOROLA LVQ DATA

BR1478

2

FUNCTION TABLE

Inputs

Storage

Registers

Data

Ports

Operating Mode

OE DIR CAB CBA SAB SBA QA QB An Bn Operating Mode

H X Input Input

↑ ↑ X X NC NC X X Isolation, Hold Storage
↑ ↑ X X L

H
X
X

X
X
L
H

L
H
X
X

X
X
L
H

Store A and/or B Data

L H Input Output

↑ X* L X NCNCNC

NC

L
H

L
H

Real Time A Data to B Bus

H X NC NC X QA Stored A Data to B Bus

↑ X* L X L

H

NC
NC

L
H

L
H

Real Time A Data to B Bus;
Store A Data

H X L

H

NC
NC

L
H

QA
QA

Stored A Data to B Bus;
Store A Data

L L Output Input

X* ↑ X L NCNCNC

NC

L
H

L
H

Real Time B Data to A Bus

X H NC NC QB X Stored B Data to A Bus

X* ↑ X L NC

NC

L
H

L
H

L
H

Real Time B Data to A Bus;
Store B Data

X H NC

NC

L
H

QB
QB

L
H

Stored B Data to A Bus;
Store B Data

H = High Voltage Level; L = Low V oltage Level; X = Don’t Care; ↑ = Low–to–High Clock T ransition; ↑ = NOT Low–to–High Clock Transition; NC = No Change; * = The
clocks are not internally gated with either the Output Enables or the Source Inputs. Therefore, data at the A or B ports may be clocked into the storage registers, at any
time. For ICC reasons, Do Not Float Inputs.

MC74LVQ646

LCX DATA
BR1478

3 MOTOROLA

BUS APPLICATIONS

BUS A

BUS B

OELDIRLCABXCBAXSABXSBA

L

Real Time Transfer – Bus B to

Bus A

BUS A

BUS B

OELDIRHCABXCBAXSABLSBA

X

Real Time Transfer – Bus A to

Bus B

BUS B

OE

X
X
H

DIR

X
X
X

CAB

↑

X

↑

CBA

X

↑
↑

SAB

X
X
X

SBA

X
X
X

Store Data from Bus A, Bus B or

Busses A and B

BUS A

BUS B

OE

L
L

DIR

L
H

CAB

X

H or L

CBA

H or L

X

SAB

X
H

SBA

H
X

Transfer Storage Data to Bus A

or Bus B

BUS A

MC74LVQ646

MOTOROLA LVQ DATA

BR1478

4

ABSOLUTE MAXIMUM RATINGS*

Symbol Parameter Value Condition Unit

V

CC

DC Supply Voltage –0.5 to +7.0 V

V

I

DC Input Voltage –0.5 ≤ VI ≤ VCC + 0.5V V

V

O

DC Output Voltage –0.5 ≤ VO ≤ VCC + 0.5 Output in HIGH or LOW State V

I

IK

DC Input Diode Current –20 VI = –0.5V mA

+20 VI = VCC + 0.5V mA

I

OK

DC Output Diode Current –20 VO = –0.5V mA

+20 VI = VCC + 0.5V mA

I

O

DC Output Source/Sink Current ±50 mA

I

CC

DC Supply Current ±400 mA

I

GND

DC Ground Current ±400 mA

T

STG

Storage Temperature Range –65 to +150 °C

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or

conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Typ Max Unit

V

CC

Supply Voltage 2.0 3.3 3.6 V

V

I

Input Voltage 0 V

CC

V

V

O

Output Voltage 0 V

CC

V

T

A

Operating Free–Air Temperature –40 +85 °C

∆V/∆t Input Transition Rise or Fall Rate, VIN from 0.8V to 2.0V, VCC = 3.0V 0 125 mV/ns

DC ELECTRICAL CHARACTERISTICS

TA = –40°C to +85°C

Symbol Characteristic Condition Min Max Unit

V

IH

HIGH Level Input Voltage (Note 1) 2.7V ≤ VCC ≤ 3.6V,

VO = 0.1V or VCC – 0.1V

2.0 V

V

IL

LOW Level Input Voltage (Note 1) 2.7V ≤ VCC ≤ 3.6V,

VO = 0.1V or VCC – 0.1V

0.8 V

V

OH

HIGH Level Output Voltage 2.7V ≤ VCC ≤ 3.6V; IOH = –50µA VCC– 0.1 V

VCC = 2.7V; IOH = –12mA 2.2
VCC = 3.0V; IOH = –12mA 2.48

V

OL

LOW Level Output Voltage 2.7V ≤ VCC ≤ 3.6V; IOL = 50µA 0.1 V

2.7V ≤ VCC ≤ 3.6V; IOL= 12mA 0.4

I

I

Input Leakage Current 2.7V ≤ VCC ≤3.6V; VI= VCC, GND ±1.0 µA

I

OZT

Maximum I/O Leakage Current VI(OE) = VIL, VIH; VI, VO= VCC, GND ±3 µA

I

OLD

Minimum Dynamic Output Current (Note 2) VCC = 3.6V; V

OLD

= 0.8V Max 36 mA

I

OHD

VCC = 3.6V; V

OHD

= 2.0V Min –25 mA

I

CC

Quiescent Supply Current 2.7V ≤ VCC ≤3.6V; VI = VCC, GND 10 µA

1. These values of VI are used to test DC electrical characteristics only. Functional test should use VIH ≥ 2.4V, VIL ≤ 0.5V.

2. Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed. Maximum test
duration is 2ms, one output loaded at a time.

MC74LVQ646

LCX DATA
BR1478

5 MOTOROLA

DYNAMIC SWITCHING CHARACTERISTICS (VCC = 3.3V)

TA = +25°C

Symbol Characteristic Condition Min Typ Max Unit

V

OLP

Dynamic LOW Peak Voltage (Note 1) CL = 50pF, VIH = 3.3V, VIL = 0V 0.6 1.0 V

V

OLV

Dynamic LOW Valley Voltage (Note 1) CL = 50pF, VIH = 3.3V, VIL = 0V –0.5 –1.0 V

V

IHD

High Level Dynamic Input Voltage
(Note 2)

Input–Under–Test Switching 0V to Threshold,

f=1MHz

1.5 2.0 V

V

ILD

Low Level Dynamic Input Voltage
(Note 2)

Input–Under–Test Switching 3.3V to Threshold,

f=1MHz

1.5 0.8 V

1. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW. The remaining output is measured in the
LOW state.

2. Number of data inputs is defined as “n” switching, “n–1” inputs switching 0V to 3.3V.

AC CHARACTERISTICS1 (tR = tF = 2.5ns; CL = 50pF; RL = 500Ω)

Limits

TA = +25°C TA = –40°C to +85°C

VCC = 3.0V to 3.6V VCC = 2.7V VCC = 3.0V to 3.6V VCC = 2.7V

Symbol Parameter Min Typ Max Min Typ Max Min Max Max Unit

f

max

Clock Pulse Frequency 150 150 MHz

t

PLH

t

PHL

Propagation Delay
Clock to Output

1.5

1.5

12.5

10.0

15.0

13.0

1.5

1.5

14.0

12.0

18.0

15.0

1.5

1.5

17.0

14.5

20.0

17.0

ns

t

PLH

t

PHL

Propagation Delay
Input to Output

1.5

1.5

9.5

8.0

12.0

11.0

1.5

1.5

11.0

9.5

13.5

12.5

1.5

1.5

13.5

12.0

14.5

14.0

ns

t

PLH

t

PHL

Propagation Delay
Select to Output

1.5

1.5

9.5

8.5

12.0

11.0

1.5

1.5

11.0

10.0

13.0

12.5

1.5

1.5

13.0

12.5

14.5

14.0

ns

t

PZH

t

PZL

Output Enable Time
OE

to An, Bn

1.5

1.5

8.0

9.0

10.5

11.0

1.5

1.5

9.5

10.0

12.0

12.5

1.5

1.5

11.0

12.0

13.0

14.0

ns

t

PHZ

t

PLZ

Output Disable Time
OE

to An, Bn

1.5

1.5

9.0

8.5

11.0

10.5

1.5

1.5

10.5

9.5

12.5

12.5

1.5

1.5

12.0

12.0

14.0

14.0

ns

t

PZH

t

PZL

Output Enable Time
DIR to An, Bn

1.5

1.5

9.0

10.0

12.0

12.0

1.5

1.5

12.0

11.0

14.0

14.0

1.5

1.5

13.0

12.5

16.0

16.0

ns

t

PHZ

t

PLZ

Output Disable Time
DIR to An, Bn

1.5

1.5

9.0

10.0

11.0

12.5

1.5

1.5

10.0

13.0

13.0

15.5

1.5

1.5

12.0

14.0

15.0

18.0

ns

t

OSHL

t

OSLH

Output–to–Output Skew
(Note 2)

1.0

1.0

1.5

1.5

1.0

1.0

1.5

1.5

1.5

1.5

ns

1. These AC parameters are preliminary and may be modified prior to release. The maximum AC limits are design targets. Actual performance
will be specified upon completion of characterization.

2. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (t

OSHL

) or LOW–to–HIGH (t

OSLH

); parameter

guaranteed by design.

AC OPERATING REQUIREMENTS (tR = tF = 2.5ns; CL = 50pF; RL = 500Ω)

Limits

TA = +25°C TA = –40°C to +85°C

VCC = 3.0V to 3.6V VCC = 2.7V VCC = 3.0V to 3.6V VCC = 2.7V

Symbol Parameter Min Min Min Min Unit

t

s

Setup TIme, HIGH or LOW Dn to LE 2.5 4.0 2.5 4.5 ns

t

h

Hold TIme, HIGH or LOW Dn to LE 1.5 1.5 1.5 1.5 ns

t

w

LE Pulse Width, HIGH 3.3 5.0 3.3 6.0 ns

MC74LVQ646

MOTOROLA LVQ DATA

BR1478

6

CAPACITIVE CHARACTERISTICS

Symbol Parameter Condition Typical Unit

C

PD

Power Dissipation Capacitance 10MHz, VCC = 3.3V, VI = 0V or V

CC

50 pF

C

IN

Input Capacitance VCC = Open, VI = 0V or V

CC

4.5 pF

C

I/O

Input/Output Capacitance VCC = 3.3V, VI = 0V or V

CC

15 pF

WAVEFORM 2 – OE/DIR to An/Bn OUTPUT ENABLE AND DISABLE TIMES

tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns

V

CC

0V

VOH – 0.3V

≈

0V

OE

An, Bn

t

PZH

≈

3.0V

VOL + 0.3V

50% V

CC

50% V

CC

t

PHZ

t

PZL

t

PLZ

An, Bn

50% V

CC

50% V

CC

Figure 1. AC Waveforms

WAVEFORM 1 – SAB to B and SBA to A, An to Bn PROPAGATION DELAYS

tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns

V

CC

0V

An, Bn,

SBA, SAB

Bn, An

50% V

CC

V

OH

V

OL

t

PLH

, t

PHL

50% V

CC

DIR

MC74LVQ646

LCX DATA
BR1478

7 MOTOROLA

Figure 2. AC Waveforms

WAVEFORM 4 – INPUT PULSE DEFINITION

tR = tF = 2.5ns, 10% to 90% of 0V to V

CC

POSITIVE
PULSE

NEGATIVE
PULSE

50% V

CC

50% V

CC

t

w

50% V

CC

50% V

CC

t

w

WAVEFORM 3 – CLOCK to Bn/An PROPAGATION DELAYS, CLOCK MINIMUM PULSE WIDTH,

An/Bn to CLOCK SETUP AND HOLD TIMES

tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted

V

CC

0V

An, Bn

CAB,

CBA

50% V

CC

Bn, An

V

CC

0V

V

OH

V

OL

t

PLH

, t

PHL

t

w

50% V

CC

50% V

CC

50% V

CC

t

h

t

s

f

max

OPEN

PULSE

GENERATOR

R

T

DUT

V

CC

R

L

R

1

C

L

6V
GND

TEST SWITCH

t

PLH

, t

PHL

Open

t

PZL

, t

PLZ

6V

Open Collector/Drain t

PLH

and t

PHL

6V

t

PZH

, t

PHZ

GND

CL = 50pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = Z

OUT

of pulse generator (typically 50Ω)

Figure 3. Test Circuit

MC74LVQ646

MOTOROLA LVQ DATA

BR1478

8

OUTLINE DIMENSIONS

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751E–04

ISSUE E

T

0.010 (0.25) A B

M

S S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F
G

J
K
M
P
R

15.25

7.40

2.35

0.35

0.41

0.23

0.13
0

°

10.05

0.25

15.54

7.60

2.65

0.49

0.90

0.32

0.29
8°

10.55

0.75

0.601

0.292

0.093

0.014

0.016

0.009

0.005
0°

0.395

0.010

0.612

0.299

0.104

0.019

0.035

0.013

0.011
8°

0.415

0.029

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.

–A

–

–B

–

1 12

24 13

–T

–

C

K

SEATING
PLANE

R X 45°

G 22 PL

P 12 PL

0.010 (0.25)

B

M M

F

J

M

D 24 PL

SD SUFFIX

PLASTIC SSOP PACKAGE

CASE 940D–03

ISSUE B

24 13

121

DIMAMIN MAX MIN MAX

INCHES

8.07 8.33 0.317 0.328

MILLIMETERS

B 5.20 5.38 0.205 0.212
C 1.73 1.99 0.068 0.078
D 0.05 0.21 0.002 0.008

F 0.63 0.95 0.024 0.037
G 0.65 BSC 0.026 BSC
H 0.44 0.60 0.017 0.024

J 0.09 0.20 0.003 0.008

J1 0.09 0.16 0.003 0.006

K 0.25 0.38 0.010 0.015

K1 0.25 0.33 0.010 0.013

_ _ _ _

NOTES:

4 DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.
5 CONTROLLING DIMENSION: MILLIMETER.
6 DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.
7 DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.15 (0.006)

PER SIDE.
8 DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION/INTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN

EXCESS OF K DIMENSION AT MAXIMUM

MATERIAL CONDITION. DAMBAR INTRUSION

SHALL NOT REDUCE DIMENSION K BY MORE

THAN 0.07 (0.002) AT LEAST MATERIAL

CONDITION.
9 TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

10 DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE –W–.

L 7.65 7.90 0.301 0.311

M 0 8 0 8

F

M

DETAIL E

N

N

0.25 (0.010)

K

J

J1

K1

SECTION N–N

A

B

K24X REF

S

U

M

0.12 (0.005) V

S

T

L

L/2

PIN 1
IDENT

S

U

M

0.20 (0.008) T

–V–

–U–

H

D

C

0.076 (0.003)

G

–T–

SEATING
PLANE

DETAIL E

–W–

MC74LVQ646

LCX DATA
BR1478

9 MOTOROLA

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948H–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 7.70 7.90 0.303 0.311
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

NOTES:

1 DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.
4 DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5 DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.
6 TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.
7 DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE –W–.

_ _ _ _

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V

S

T

L

–U–

SEATING
PLANE

0.10 (0.004)

–T–

SECTION N–N

DETAIL E

J

J1

K

K1

DETAIL E

F

M

–W–

0.25 (0.010)

13

24

12

1

PIN 1
IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

–V–

24X REFK

N

N

MC74LVQ646

MOTOROLA LVQ DATA

BR1478

10

How to reach us:
USA/EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

MFAX: [e-mail] –TOUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

MC74LVQ646/D

*MC74LVQ646/D*

◊