Datasheet MC74LCX652DTR2, MC74LCX652DWR2 Datasheet (MOTOROLA)



SEMICONDUCTOR TECHNICAL DATA

1

REV 1

 Motorola, Inc. 1997

3/97

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(%) #, ( !#)* ( 
(%) #, ( #*" +$ %$

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**  &%%, (*#%!

The MC74LCX652 is a high performance, non–inverting octal
transceiver/registered transceiver operating from a 2.7 to 3.6V supply.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5V allows
MC74LCX652 inputs to be safely driven from 5V devices. The
MC74LCX652 is suitable for memory address driving and all TTL level
bus oriented transceiver applications.

Data on the A or B bus will be clocked into the registers as the
appropriate clock pin goes from a LOW–to–HIGH logic level. Two Output
Enable pins (OEBA

, OEAB) are provided to control the transceiver
outputs. In the transceiver mode, data present at the high impedance port
may be stored in either the A or the B register or in both. The select
controls (SBA, SAB) can multiplex stored and real–time (transparent
mode) data. In the isolation mode (both outputs disabled), A data may be
stored in the B register or B data may be stored in the A register. When in
the real–time mode, it is possible to store data without using the internal
registers by simultaneously enabling OEAB and OEBA

. In this
configuration, each output reinforces its input (data retention is not
guaranteed in this mode).

• Designed for 2.7 to 3.6V V

CC

Operation

• 5V T olerant — Interface Capability With 5V TTL Logic

• Supports Live Insertion and Withdrawal

• I

OFF

Specification Guarantees High Impedance When VCC = 0V

• LVTTL Compatible

• LVCMOS Compatible

• 24mA Balanced Output Sink and Source Capability

• Near Zero Static Supply Current in All Three Logic States (10µA)

Substantially Reduces System Power Requirements

• Latchup Performance Exceeds 500mA

• ESD Performance: Human Body Model >2000V; Machine Model >200V

Figure 1. 24–Lead Pinout (Top View)

2324 22 21 20 19 18

21 34567

V

CC

17

8

16

9

15

10

CBA SBA OEBA B0 B1 B2 B3 B4 B5

CAB SAB OEAB A0 A1 A2 A3 A4 A5 A6

14

11

13

12

B6 B7

A7 GND



LOW–VOLTAGE CMOS

OCTAL TRANSCEIVER/

REGISTERED TRANSCEIVER

WITH DUAL ENABLE

PIN NAMES

Function

Side A Inputs/Outputs
Side B Inputs/Outputs
Clock Pulse Inputs
Select Control Inputs
Output Enable Inputs

Pins

A0–A7
B0–B7
CAB, CBA
SAB, SBA
OEBA

, OEAB

DW SUFFIX

24–LEAD PLASTIC SOIC PACKAGE

CASE 751E–04

DT SUFFIX

24–LEAD PLASTIC TSSOP PACKAGE

CASE 948H–01

SD SUFFIX

24–LEAD PLASTIC SSOP PACKAGE

CASE 940D–03

Figure 2. Logic Diagram

C

D

Q

OEBA

OEAB

CBA

SBA

SAB

CAB

C

D

Q

A0

B0

1 of 8 Channels

To 7 Other Channels

1
3

21

22

2

23

MC74LCX652

MOTOROLA LCX DATA

BR1339 — REV 3

2

FUNCTION TABLE

Inputs

Data Ports

OEAB OEBA CAB CBA SAB SBA An Bn

O

perating Mode

L H Input Input

↑ ↑ X X X X Isolation, Hold Storage
↑ ↑ X X l

h

l

h

Store A and/or B Data

H H Input Output

↑ X* L X L

H

L
H

Real Time A Data to B Bus

H X X QA Stored A Data to B Bus

↑ X* L X l

h

L
H

Real Time A Data to B Bus; Store A Data

H X L

H

QA
QA

Clock A Data to B Bus; Store A Data

L L Output Input

X* ↑ X L L

H

L
H

Real Time B Data to A Bus

X H QB X Stored B Data to A Bus

X* ↑ X L L

H

l

h

Real Time B Data to A Bus; Store B Data

X H QB

QB

L
H

Clock B Data to A Bus; Store B Data

H L Output Output

↑ ↑ H H QB QA Stored A Data to B Bus,

Stored B Data to A Bus

H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Low–to–High Clock Transition; L = Low Voltage Level; l = Low Voltage Level One Setup
Time Prior to the Low–to–High Clock T ransition; X = Don’t Care; ↑ = Low–to–High Clock Transition; ↑

= NOT Low–to–High Clock Transition; QA = A input storage register;
QB = B input storage register; * = The clocks are not internally gated with either the Output Enables or the Source Inputs. Therefore, data at the A or B ports may be
clocked into the storage registers, at any time. For ICC reasons, Do Not Float Inputs.

MC74LCX652

LCX DATA
BR1339 — REV 3

3 MOTOROLA

Figure 3. Bus Applications

BUS A

BUS B

OEABLOEBA

L

CABXCBAXSABXSBA

L

Real Time Transfer – Bus B to

Bus A

BUS A

BUS B

OEABHOEBA

H

CABXCBAXSABLSBA

X

Real Time Transfer – Bus A to

Bus B

BUS B

OEAB

X
L
L

OEBA

H
X
H

CAB

↑

X

↑

CBA

X

↑
↑

SAB

X
X
X

SBA

X
X
X

Store Data from Bus A, Bus B or

Bus A and Bus B

BUS A

BUS B

OEAB

H

L

H

OEBA

H
L
L

CAB

H or L

X

H or L

CBA

X
H or L
H or L

SAB

H
X
H

SBA

X
H
H

Transfer A Stored Data to Bus B

or B Stored Data to Bus A or

Both at the Same Time

BUS A

OEAB

H

L

OEBA

H

L

CAB

↑
↑

CBA

↑
↑

SAB

L
X

SBA

X

L

Store Bus A in Both Registers or

Store Bus B in Both Registers

BUS A

BUS B

OEABLOEBA

H

CAB

H or L

CBA

H or L

SABXSBA

X

Isolation

BUS A

BUS B

MC74LCX652

MOTOROLA LCX DATA

BR1339 — REV 3

4

ABSOLUTE MAXIMUM RATINGS*

Symbol Parameter Value Condition Unit

V

CC

DC Supply Voltage –0.5 to +7.0 V

V

I

DC Input Voltage –0.5 ≤ VI ≤ +7.0 V

V

O

DC Output Voltage –0.5 ≤ VO ≤ +7.0 Output in 3–State V

–0.5 ≤ VO ≤ VCC + 0.5 Note 1. V

I

IK

DC Input Diode Current –50 VI < GND mA

I

OK

DC Output Diode Current –50 VO < GND mA

+50 VO > V

CC

mA

I

O

DC Output Source/Sink Current ±50 mA

I

CC

DC Supply Current Per Supply Pin ±100 mA

I

GND

DC Ground Current Per Ground Pin ±100 mA

T

STG

Storage Temperature Range –65 to +150 °C

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions

beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.

1. Output in HIGH or LOW State. IO absolute maximum rating must be observed.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Typ Max Unit

V

CC

Supply Voltage Operating

Data Retention Only

2.0

1.5

3.3

3.3

3.6

3.6

V

V

I

Input Voltage 0 5.5 V

V

O

Output Voltage (HIGH or LOW State)

(3–State)

0
0

V

CC

5.5

V

I

OH

HIGH Level Output Current, VCC = 3.0V – 3.6V –24 mA

I

OL

LOW Level Output Current, VCC = 3.0V – 3.6V 24 mA

I

OH

HIGH Level Output Current, VCC = 2.7V – 3.0V –12 mA

I

OL

LOW Level Output Current, VCC = 2.7V – 3.0V 12 mA

T

A

Operating Free–Air Temperature –40 +85 °C

∆t/∆V Input Transition Rise or Fall Rate, VIN from 0.8V to 2.0V ,

VCC = 3.0V

0 10 ns/V

DC ELECTRICAL CHARACTERISTICS

TA = –40°C to +85°C

Symbol Characteristic Condition Min Max Unit

V

IH

HIGH Level Input Voltage (Note 2.) 2.7V ≤ VCC ≤ 3.6V 2.0 V

V

IL

LOW Level Input Voltage (Note 2.) 2.7V ≤ VCC ≤ 3.6V 0.8 V

V

OH

HIGH Level Output Voltage 2.7V ≤ VCC ≤ 3.6V; IOH = –100µA VCC– 0.2 V

VCC = 2.7V; IOH = –12mA 2.2
VCC = 3.0V; IOH = –18mA 2.4
VCC = 3.0V; IOH = –24mA 2.2

V

OL

LOW Level Output Voltage 2.7V ≤ VCC ≤ 3.6V; IOL = 100µA 0.2 V

VCC = 2.7V; IOL= 12mA 0.4
VCC = 3.0V; IOL = 16mA 0.4
VCC = 3.0V; IOL = 24mA 0.55

2. These values of VI are used to test DC electrical characteristics only.

MC74LCX652

LCX DATA
BR1339 — REV 3

5 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (continued)

TA = –40°C to +85°C

Symbol Characteristic Condition Min Max Unit

I

I

Input Leakage Current 2.7V ≤ VCC ≤ 3.6V; 0V ≤ VI ≤ 5.5V ±5.0 µA

I

OZ

3–State Output Current 2.7 ≤ VCC ≤ 3.6V; 0V ≤ VO ≤ 5.5V;

VI = VIH or V

IL

±5.0 µA

I

OFF

Power–Off Leakage Current VCC = 0V; VI or VO = 5.5V 10 µA

I

CC

Quiescent Supply Current

2.7 ≤ VCC ≤ 3.6V; VI = GND or V

CC

10 µA

2.7 ≤ VCC ≤ 3.6V; 3.6 ≤ VI or VO ≤ 5.5V ±10 µA

∆I

CC

Increase in ICC per Input 2.7 ≤ VCC ≤ 3.6V; VIH = VCC – 0.6V 500 µA

AC CHARACTERISTICS (tR = tF = 2.5ns; CL = 50pF; RL = 500Ω)

Limits

TA = –40°C to +85°C

VCC = 3.0V to 3.6V VCC = 2.7V

Symbol Parameter Waveform Min Max Min Max Unit

f

max

Clock Pulse Frequency 3 150 MHz

t

PLH

t

PHL

Propagation Delay
Input to Output

1 1.5

1.5

7.0

7.0

1.5

1.5

8.0

8.0

ns

t

PLH

t

PHL

Propagation Delay
Clock to Output

3 1.5

1.5

8.5

8.5

1.5

1.5

9.5

9.5

ns

t

PLH

t

PHL

Propagation Delay
Select to Output

1 1.5

1.5

8.5

8.5

1.5

1.5

9.5

9.5

ns

t

PZH

t

PZL

Output Enable Time to
High and Low Level

2 1.5

1.5

8.5

8.5

1.5

1.5

9.5

9.5

ns

t

PHZ

t

PLZ

Output Disable Time From
High and Low Level

2 1.5

1.5

8.5

8.5

1.5

1.5

9.5

9.5

ns

t

s

Setup Time, HIGH or LOW Data to Clock 3 2.5 2.5 ns

t

h

Hold Time, HIGH or LOW Data to Clock 3 1.5 1.5 ns

t

w

Clock Pulse Width, HIGH or LOW 3 3.3 3.3 ns

t

OSHL

t

OSLH

Output–to–Output Skew
(Note 3.)

1.0

1.0

ns

3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (t

OSHL

) or LOW–to–HIGH (t

OSLH

); parameter

guaranteed by design.

DYNAMIC SWITCHING CHARACTERISTICS

TA = +25°C

Symbol Characteristic Condition Min Typ Max Unit

V

OLP

Dynamic LOW Peak Voltage (Note 4.) VCC = 3.3V , CL = 50pF, VIH = 3.3V , VIL = 0V 0.8 V

V

OLV

Dynamic LOW Valley Voltage (Note 4.) VCC = 3.3V , CL = 50pF, VIH = 3.3V , VIL = 0V 0.8 V

4. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is
measured in the LOW state. The LCX652 is characterized with 7 outputs switching with 1 output held LOW.

MC74LCX652

MOTOROLA LCX DATA

BR1339 — REV 3

6

CAPACITIVE CHARACTERISTICS

Symbol Parameter Condition Typical Unit

C

IN

Input Capacitance VCC = 3.3V , VI = 0V or V

CC

7 pF

C

I/O

Input/Output Capacitance VCC = 3.3V , VI = 0V or V

CC

8 pF

C

PD

Power Dissipation Capacitance 10MHz, VCC = 3.3V , VI = 0V or V

CC

25 pF

WAVEFORM 2 – OEBA/OEAB to An/Bn OUTPUT ENABLE AND DISABLE TIMES

tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns

2.7V

0V

VOH – 0.3V

≈

0V

OEBA

An, Bn

t

PZH

≈

3.0V

VOL + 0.3V

1.5V1.5V

t

PHZ

t

PZL

t

PLZ

An, Bn

1.5V

1.5V

Figure 4. AC Waveforms

WAVEFORM 1 – SAB to B and SBA to A, An to Bn PROPAGATION DELAYS

tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns

2.7V

0V

An, Bn,

SBA, SAB

Bn, An

1.5V

V

OH

V

OL

t

PLH

, t

PHL

1.5V

OEAB

MC74LCX652

LCX DATA
BR1339 — REV 3

7 MOTOROLA

Figure 5. AC Waveforms (continued)

WAVEFORM 4 – INPUT PULSE DEFINITION

tR = tF = 2.5ns, 10% to 90% of 0V to 2.7V

POSITIVE
PULSE

NEGATIVE
PULSE

1.5V

1.5V

t

w

1.5V

1.5V

t

w

WAVEFORM 3 – CLOCK to Bn/An PROPAGATION DELAYS, CLOCK MINIMUM PULSE WIDTH,

An/Bn to CLOCK SETUP AND HOLD TIMES

tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted

2.7V

0V

An, Bn

CAB,

CBA

1.5V

Bn, An

2.7V

0V

V

OH

V

OL

t

PLH

, t

PHL

t

w

1.5V

1.5V

1.5V

t

h

t

s

f

max

OPEN

PULSE

GENERATOR

R

T

DUT

V

CC

R

L

R

1

C

L

6V
GND

TEST SWITCH

t

PLH

, t

PHL

Open

t

PZL

, t

PLZ

6V

Open Collector/Drain t

PLH

and t

PHL

6V

t

PZH

, t

PHZ

GND

CL = 50pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = Z

OUT

of pulse generator (typically 50Ω)

Figure 6. Test Circuit

MC74LCX652

MOTOROLA LCX DATA

BR1339 — REV 3

8

OUTLINE DIMENSIONS

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751E–04

ISSUE E

T

0.010 (0.25) A B

M

S S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F

G

J
K

M

P
R

15.25

7.40

2.35

0.35

0.41

0.23

0.13
0

°

10.05

0.25

15.54

7.60

2.65

0.49

0.90

0.32

0.29
8

°

10.55

0.75

0.601

0.292

0.093

0.014

0.016

0.009

0.005
0

°

0.395

0.010

0.612

0.299

0.104

0.019

0.035

0.013

0.011
8

°

0.415

0.029

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D
DIMENSION AT MAXIMUM MA TERIAL
CONDITION.

–A

–

–B

–

112

24 13

–T

–

C

K

SEATING
PLANE

R X 45°

G 22 PL

P 12 PL

0.010 (0.25)

B

M M

F

J

M

D 24 PL

SD SUFFIX

PLASTIC SSOP PACKAGE

CASE 940D–03

ISSUE B

24 13

121

DIMAMIN MAX MIN MAX

INCHES

8.07 8.33 0.317 0.328

MILLIMETERS

B 5.20 5.38 0.205 0.212
C 1.73 1.99 0.068 0.078
D 0.05 0.21 0.002 0.008
F 0.63 0.95 0.024 0.037
G 0.65 BSC 0.026 BSC
H 0.44 0.60 0.017 0.024
J 0.09 0.20 0.003 0.008

J1 0.09 0.16 0.003 0.006

K 0.25 0.38 0.010 0.015

K1 0.25 0.33 0.010 0.013

____

NOTES:

1 DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.
4 DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.15 (0.006)

PER SIDE.
5 DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION/INTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN

EXCESS OF K DIMENSION AT MAXIMUM

MATERIAL CONDITION. DAMBAR INTRUSION

SHALL NOT REDUCE DIMENSION K BY MORE

THAN 0.07 (0.002) AT LEAST MATERIAL

CONDITION.
6 TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.
7 DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE –W–.

L 7.65 7.90 0.301 0.311

M 0 8 0 8

F

M

DETAIL E

N

N

0.25 (0.010)

K

J

J1

K1

SECTION N–N

A

B

K24X REF

S

U

M

0.12 (0.005) V

S

T

L

L/2

PIN 1
IDENT

S

U

M

0.20 (0.008) T

–V–

–U–

H

D

C

0.076 (0.003)

G

–T–

SEATING
PLANE

DETAIL E

–W–

MC74LCX652

LCX DATA
BR1339 — REV 3

9 MOTOROLA

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948H–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 7.70 7.90 0.303 0.311
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

NOTES:

1 DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.
4 DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5 DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.
6 TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.
7 DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE –W–.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V

S

T

L

–U–

SEATING
PLANE

0.10 (0.004)

–T–

SECTION N–N

DETAIL E

J

J1

K

K1

DETAIL E

F

M

–W–

0.25 (0.010)

13

24

12

1

PIN 1
IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

–V–

24X REFK

N

N

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MC74LCX652/D

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