Datasheet MC74LCX646SD, MC74LCX646DT, MC74LCX646DW Datasheet (Motorola)

Page 1
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SEMICONDUCTOR TECHNICAL DATA
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The MC74LCX646 is a high performance, non–inverting octal transceiver/registered transceiver operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5V allows MC74LCX646 inputs to be safely driven from 5V devices. The MC74LCX646 is suitable for memory address driving and all TTL level bus oriented transceiver applications.
Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes from a LOW–to–HIGH logic level. Output Enable (OE In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls (SBA, SAB) can multiplex stored and real–time (transparent mode) data. The direction control (DIR) determines which bus will receive data when the enable OE be stored in the B register or B data may be stored in the A register. Only one of the two buses, A or B, may be driven at one time.
Designed for 2.7 to 3.6V V
5V Tolerant — Interface Capability With 5V TTL Logic
Supports Live Insertion and Withdrawal
I
OFF
LVTTL Compatible
LVCMOS Compatible
24mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10µA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 500mA
ESD Performance: Human Body Model >2000V; Machine Model >200V
) and DIR pins are provided to control the transceiver outputs.
is active LOW. In the isolation mode (OE HIGH), A data may
Operation
CC
Specification Guarantees High Impedance When VCC = 0V
V
CBA SBA OE
CC
2324 22 21 20 19 18
Pinout: 24–Lead Package (Top View)
B0 B1 B2 B3 B4 B5
17
16
15
B6 B7 14
13

LOW–VOLTAGE CMOS
OCTAL TRANSCEIVER/
REGISTERED TRANSCEIVER
DW SUFFIX
24
1
24
24
PIN NAMES
Pins
A0–A7 B0–B7 CAB, CBA SAB, SBA DIR, OE
1
1
Function
Side A Inputs/Outputs Side B Inputs/Outputs Clock Pulse Inputs Select Control Inputs Output Enable Inputs
PLASTIC SOIC CASE 751E–04
SD SUFFIX
PLASTIC SSOP
CASE 940D–03
DT SUFFIX
PLASTIC TSSOP
CASE 948H–01
21 34567
CAB SAB DIR A0 A1 A2 A3 A4 A5 A6
11/96
Motorola, Inc. 1996
9
8
1
10
11
12
A7 GND
REV 2
Page 2
MC74LCX646
O
1
CBA
3
DIR
21
OE
22
SBA
2
SAB
23
CAB
A0
1 of 8 Channels
LOGIC DIAGRAM
C
Q
D
C
Q
D
B0
To 7 Other Channels
FUNCTION TABLE
Inputs
OE DIR CAB CBA SAB SBA An Bn
H X Input Input
X X X X Isolation, Hold Storage X X l
L H Input Output
X* L X L
H X X QA Stored A Data to B Bus
X* L X l
H X L
L L Output Input
X* X L L
X H QB X Stored B Data to A Bus
X* X L L
X H QB
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Low–to–High Clock Transition; L = Low Voltage Level; l = Low Voltage Level One Setup Time Prior to the Low–to–High Clock T ransition; X = Don’t Care; = Low–to–High Clock Transition; QB = B input storage register; * = The clocks are not internally gated with either the Output Enables or the Source Inputs. Therefore, data at the A or B ports may be clocked into the storage registers, at any time. For ICC reasons, Do Not Float Inputs.
Data Ports
h X X
H
h
H
H
H
QB
perating Mode
X X
l
h
L
H
L
H
QA QA
L
H
l
h L
H
= NOT Low–to–High Clock Transition; QA = A input storage register;
Store A and/or B Data
Real Time A Data to B Bus
Real Time A Data to B Bus; Store A Data
Clock A Data to B Bus; Store A Data
Real Time B Data to A Bus
Real Time B Data to A Bus; Store B Data
Clock B Data to A Bus; Store B Data
MOTOROLA LCX DATA
2
BR1339 — REV 3
Page 3
BUS APPLICATIONS
MC74LCX646
Real Time Transfer – Bus B to
Bus A
BUS A
OELDIR
CABXCBAXSABXSBA
L
Store Data from Bus A, Bus B or
Busses A and B
BUS B
L
Real Time Transfer – Bus A to
Bus B
BUS A
OELDIR
CABXCBAXSABLSBA
H
Transfer Storage Data to Bus A
or Bus B
BUS B
X
OE
X X H
BUS A
DIR
OE
L L
BUS A
DIR
BUS B
CAB
CBA
SAB
SBA
L
X
H
H or L
H or L
X
X
H
H
X
BUS B
CAB
CBA
X
X X
X
X
↑ ↑
SAB
X X X
SBA
X X X
LCX DATA BR1339 — REV 3
3 MOTOROLA
Page 4
MC74LCX646
ABSOLUTE MAXIMUM RATINGS*
Symbol Parameter Value Condition Unit
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
1. Output in HIGH or LOW State. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
V
CC
V
I
V
O
I
OH
I
OL
I
OH
I
OL
T
A
t/V Input Transition Rise or Fall Rate, VIN from 0.8V to 2.0V ,
DC Supply Voltage –0.5 to +7.0 V DC Input Voltage –0.5 VI +7.0 V DC Output Voltage –0.5 VO +7.0 Output in 3–State V
–0.5 VO VCC + 0.5 Note 1. V DC Input Diode Current –50 VI < GND mA DC Output Diode Current –50 VO < GND mA
+50 VO > V DC Output Source/Sink Current ±50 mA DC Supply Current Per Supply Pin ±100 mA DC Ground Current Per Ground Pin ±100 mA Storage Temperature Range –65 to +150 °C
Supply Voltage Operating
Data Retention Only Input Voltage 0 5.5 V Output Voltage (HIGH or LOW State)
(3–State) HIGH Level Output Current, VCC = 3.0V – 3.6V –24 mA LOW Level Output Current, VCC = 3.0V – 3.6V 24 mA HIGH Level Output Current, VCC = 2.7V – 3.0V –12 mA LOW Level Output Current, VCC = 2.7V – 3.0V 12 mA Operating Free–Air Temperature –40 +85 °C
VCC = 3.0V
2.0
1.5
0 0
0 10 ns/V
3.3
3.3
CC
V
3.6
3.6
CC
5.5
mA
V
V
DC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C
Symbol Characteristic Condition Min Max Unit
V
IH
V
IL
V
OH
V
OL
2. These values of VI are used to test DC electrical characteristics only.
MOTOROLA LCX DATA
HIGH Level Input Voltage (Note 2.) 2.7V VCC 3.6V 2.0 V LOW Level Input Voltage (Note 2.) 2.7V VCC 3.6V 0.8 V HIGH Level Output Voltage 2.7V VCC 3.6V; IOH = –100µA VCC– 0.2 V
VCC = 2.7V; IOH = –12mA 2.2 VCC = 3.0V; IOH = –18mA 2.4 VCC = 3.0V; IOH = –24mA 2.2
LOW Level Output Voltage 2.7V VCC 3.6V; IOL = 100µA 0.2 V
VCC = 2.7V; IOL= 12mA 0.4 VCC = 3.0V; IOL = 16mA 0.4 VCC = 3.0V; IOL = 24mA 0.55
4
BR1339 — REV 3
Page 5
MC74LCX646
DC ELECTRICAL CHARACTERISTICS (continued)
TA = –40°C to +85°C
Symbol Characteristic Condition Min Max Unit
I
I
I
OZ
I
OFF
I
CC
I
CC
AC CHARACTERISTICS (tR = tF = 2.5ns; CL = 50pF; RL = 500)
Symbol Parameter W aveform Min Max Min Max Unit
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
s
t
h
t
w
t
OSHL
t
OSLH
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (t guaranteed by design.
Input Leakage Current 2.7V VCC 3.6V; 0V VI 5.5V ±5.0 µA 3–State Output Current 2.7 VCC 3.6V; 0V VO 5.5V;
Power–Off Leakage Current VCC = 0V; VI or VO = 5.5V 10 µA Quiescent Supply Current
Increase in ICC per Input 2.7 VCC 3.6V; VIH = VCC – 0.6V 500 µA
Clock Pulse Frequency 3 150 MHz
Propagation Delay Input to Output
Propagation Delay Clock to Output
Propagation Delay Select to Output
Output Enable Time to High and Low Level
Output Disable Time From High and Low Level
Setup Time, HIGH or LOW Data to Clock 3 2.5 2.5 ns Hold Time, HIGH or LOW Data to Clock 3 1.5 1.5 ns Clock Pulse Width, HIGH or LOW 3 3.3 3.3 ns Output–to–Output Skew
(Note 3.)
2.7 VCC 3.6V; VI = GND or V
2.7 VCC 3.6V; 3.6 VI or VO 5.5V ± 10 µA
VI = VIH or V
VCC = 3.0V to 3.6V VCC = 2.7V
1 1.5
1.5
3 1.5
1.5
1 1.5
1.5
2 1.5
1.5
2 1.5
1.5
IL
CC
Limits
TA = –40°C to +85°C
7.0
7.0
8.5
8.5
8.5
8.5
8.5
8.5
8.5
8.5
1.0
1.0
) or LOW–to–HIGH (t
OSHL
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
±5.0 µA
10 µA
8.0
8.0
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
); parameter
OSLH
ns
ns
ns
ns
ns
ns
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol Characteristic Condition Min Typ Max Unit
V
OLP
V
OLV
4. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is measured in the LOW state.
LCX DATA BR1339 — REV 3
Dynamic LOW Peak Voltage (Note 4.) VCC = 3.3V, CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V Dynamic LOW Valley Voltage (Note 4.) VCC = 3.3V, CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V
5 MOTOROLA
Page 6
MC74LCX646
CAPACITIVE CHARACTERISTICS
Symbol Parameter Condition Typical Unit
C
IN
C
I/O
C
PD
Input Capacitance VCC = 3.3V, VI = 0V or V Input/Output Capacitance VCC = 3.3V, VI = 0V or V Power Dissipation Capacitance 10MHz, VCC = 3.3V, VI = 0V or V
An, Bn,
SBA, SAB
Bn, An
WAVEFORM 1 – SAB to B and SBA to A, An to Bn PROPAGATION DELAYS
1.5V
t
, t
PLH
PHL
1.5V
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
CC CC
CC
2.7V
0V
V
OH
V
OL
7 pF 8 pF
25 pF
OE
1.5V1.5V
DIR
t
PZH
An, Bn
t
PZL
An, Bn
WAVEFORM 2 – OE/DIR to An/Bn OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
1.5V
1.5V
t
PHZ
t
PLZ
VOH – 0.3V
VOL + 0.3V
Figure 1. AC Waveforms
2.7V
0V
3.0V
0V
MOTOROLA LCX DATA
6
BR1339 — REV 3
Page 7
An, Bn
CAB,
CBA
Bn, An
MC74LCX646
2.7V
1.5V 0V
t
s
1.5V
t
h
t
w
t
PLH
, t
1.5V
PHL
f
max
1.5V
2.7V
0V
V
OH
V
OL
WAVEFORM 3 – CLOCK to Bn/An PROPAGATION DELAYS, CLOCK MINIMUM PULSE WIDTH,
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted
NEGATIVE PULSE
POSITIVE PULSE
An/Bn to CLOCK SETUP AND HOLD TIMES
t
1.5V
1.5V
WAVEFORM 4 – INPUT PULSE DEFINITION
tR = tF = 2.5ns, 10% to 90% of 0V to 2.7V
w
t
w
1.5V
1.5V
Figure 2. AC Waveforms
V
CC
R
PULSE
GENERATOR
DUT
R
T
C
L
1
R
L
6V OPEN GND
LCX DATA BR1339 — REV 3
TEST SWITCH
t
, t
PLH
PHL
t
, t
PZL
PLZ
Open Collector/Drain t t
, t
PZH
PHZ
CL = 50pF or equivalent (Includes jig and probe capacitance) RL = R1 = 500 or equivalent RT = Z
of pulse generator (typically 50)
OUT
PLH
and t
PHL
Open
GND
Figure 3. T est Circuit
7 MOTOROLA
6V 6V
Page 8
MC74LCX646
24 13
112
D 24 PL
–T
SEATING PLANE
–A
0.010 (0.25) A B
M
S S
T
G 22 PL
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
–B
P 12 PL
C
K
0.010 (0.25)
J
F
M
M M
B
R X 45°
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
MIN MINMAX MAX
DIM
A B C D F G
K M P R
J
15.54
7.60
2.65
0.49
0.90
0.32
0.29 8
10.55
0.75
0.601
0.292
0.093
0.014
0.016
0.009
0.005 0
°
°
0.395
0.010
15.25
7.40
2.35
0.35
0.41
1.27 BSC 0.050 BSC
0.23
0.13 0
°
10.05
0.25
0.612
0.299
0.104
0.019
0.035
0.013
0.011 8
°
0.415
0.029
0.076 (0.003)
SEATING
–T–
PLANE
L/2
L
PIN 1 IDENT
0.20 (0.008) T
C
D
K24X REF
0.12 (0.005) V
24 13
A
–V–
M
S
U
G
H
SD SUFFIX
PLASTIC SSOP PACKAGE
CASE 940D–03
ISSUE B
M
S
U
T
S
J
B
121
–U–
N
N
DETAIL E
K
K1
SECTION N–N
0.25 (0.010)
M
F
DETAIL E
J1
–W–
NOTES:
4 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982. 5 CONTROLLING DIMENSION: MILLIMETER. 6 DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE. 7 DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006)
PER SIDE. 8 DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF K DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR INTRUSION
SHALL NOT REDUCE DIMENSION K BY MORE
THAN 0.07 (0.002) AT LEAST MATERIAL
CONDITION. 9 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
10 DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
MILLIMETERS
DIMAMIN MAX MIN MAX
8.07 8.33 0.317 0.328
B 5.20 5.38 0.205 0.212 C 1.73 1.99 0.068 0.078 D 0.05 0.21 0.002 0.008 F 0.63 0.95 0.024 0.037 G 0.65 BSC 0.026 BSC H 0.44 0.60 0.017 0.024 J 0.09 0.20 0.003 0.008
J1 0.09 0.16 0.003 0.006
K 0.25 0.38 0.010 0.015
K1 0.25 0.33 0.010 0.013
L 7.65 7.90 0.301 0.311 M 0 8 0 8
____
INCHES
MOTOROLA LCX DATA
8
BR1339 — REV 3
Page 9
OUTLINE DIMENSIONS
MC74LCX646
S
U0.15 (0.006) T
S
U0.15 (0.006) T
0.10 (0.004)
SEATING
–T–
PLANE
PLASTIC TSSOP PACKAGE
DT SUFFIX
CASE 948H–01
ISSUE O
24X REFK
M
2X L/2
0.10 (0.004) V
24
L
PIN 1 IDENT.
1
A
–V–
C
D
G
S
U
T
S
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
13
B
–U–
12
H
–W–
Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE. 4 DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5 DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION. 6 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY. 7 DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
DIM MIN MAX MIN MAX
A 7.70 7.90 0.303 0.311 B 4.30 4.50 0.169 0.177 C ––– 1.20 ––– 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC M 0 8 0 8
____
INCHESMILLIMETERS
DETAIL E
K
N
K1
J1
SECTION N–N
J
N
F
DETAIL E
0.25 (0.010)
M
LCX DATA BR1339 — REV 3
9 MOTOROLA
Page 10
MC74LCX646
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MOTOROLA LCX DATA
10
MC74LCX646/D
BR1339 — REV 3
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