The MC74LCX16501 is a high performance, non–inverting 18–bit
universal bus transceiver operating from a 2.7 to 3.6V supply. This part is
not byte controlled; it is “18–bit” controlled. High impedance TTL
compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A VI specification of 5.5V allows MC74LCX16501 inputs to
be safely driven from 5V devices. The MC74LCX16501 is suitable for
memory address driving and all TTL level bus oriented transceiver
applications.
Data flow in each direction is controlled by Output Enable (OEAB,
OEBA
), Latch Enable (LEAB, LEBA) and Clock inputs (CAB, CBA). When
LEAB is HIGH, the A–to–B dataflow is transparent. When LEAB is LOW,
and CAB is held at LOW or HIGH, the data A is latched; on the
LOW–to–HIGH transition of CAB the A–data is stored in the
latch/flip–flop. The outputs are active when OEAB is HIGH. When OEAB
is LOW the B–outputs are in 3–state. Similarly , the LEBA, OEBA
control the B–to–A dataflow. Please note that the output enables are
complementary; OEAB is active HIGH, OEBA
• Designed for 2.7 to 3.6V V
• 6ns t
Maximum
pd
Operation
CC
is active LOW.
• 5V Tolerant — Interface Capability With 5V TTL Logic
• Supports Live Insertion and Withdrawal
• I
Specification Guarantees High Impedance When VCC = 0V
OFF
• LVTTL Compatible
• LVCMOS Compatible
• 24mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current in All Three Logic States (20µA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500mA
• ESD Performance: Human Body Model >2000V; Machine
Model >200V
and CBA
LOW–VOLTAGE CMOS
18–BIT UNIVERSAL BUS
TRANSCEIVER
56–LEAD PLASTIC TSSOP PACKAGE
PIN NAMES
Pins
OEAB, OEBA
CAB, CBA
LEAB, LEBA
A0–A17
B0–B17
DT SUFFIX
CASE 1202–01
Function
Output Enable Inputs
Clock Pulse Inputs
Latch Enable Inputs
Side A Inputs/Outputs
Side B Inputs/Outputs
3/97
Motorola, Inc. 1997
1
REV 1
Page 2
MC74LCX16501
V
CC
A11
V
CC
A16
GNDOEAB
561
CABLEAB
552
B0A0
543
GNDGND
534
B1A1
525
B2A2
516
V
507
CC
B3A3
498
B4A4
489
B5A5
4710
GNDGND
4611
B6A6
4512
B7A7
4413
B8A8
4314
B9A9
4215
B10A10
4116
B11
4017
GNDGND
3918
B12A12
3819
B13A13
3720
B14A14
3621
V
3522
CC
B15A15
3423
B16
3324
GNDGND
3225
B17A17
3126
CBAOEBA
3027
GNDLEBA
2928
OEAB
CBA
LEBA
OEBA
CAB
LEAB
A0
1
30
28
27
55
2
C1
3
1D
C1
1D
C1
1D
C1
1D
54
B0
To 17 Other Channels
Figure 1. 56-Lead Pinout
Figure 2. Logic Diagram
(Top View)
MOTOROLALCX DATA
2
BR1339 — REV 3
Page 3
MC74LCX16501
Operating Mode
FUNCTION TABLE
l
h
l
h
L
H
L
H
L
H
Data
Ports
Operating Mode
l
Clock A and/or B Data; A and B Outputs Disabled
h
L
Clock A Data to B Bus; Store A Data
H
L
A Data to B Bus; (Transparent)
H
l
Clock B Data to A Bus; Store B Data
h
L
B Data to A Bus; (Transparent)
H
Inputs
OEABOEBALEABLEBACABCBAAnBn
LHInputInput
H or LH or LXXHold Data; A and B Outputs Disabled
LL
HHInputOutput
LX
HXXX*
LLOutputInput
XL
XHX*X
HLOutputOutput
LLH or LH or LQBQAStored A Data to B Bus; Stored B Data to A Bus
H = High Voltage Level; L = Low Voltage Level; h = High Voltage Level One Setup Time Prior to the Latch Enable or Clock Low–to–High Transition; l = Low Voltage
Level One Setup Time Prior to the Latch Enable or Clock Low–to–High Transition; X = Don’t Care; ↑ = Low–to–High Clock T ransition; QA = A input storage register;
QB = B input storage register; * = The clocks are not internally gated with either the Output Enables or the Source Inputs. Therefore, data at the A or B ports may be
clocked into the storage registers, at any time. For ICC reasons, Do Not Float Inputs.
↑↑
H or LX*XQAHold and Display B Data
↑X*
X*H or LQBXHold and Display A Data
X*↑
LCX DATABR1339 — REV 3
3MOTOROLA
Page 4
MC74LCX16501
Real Time Transfer – Bus B to
Bus A
BUS A
OEABLOEBA
CABXCBAXLEABXLEBA
L
Store Data from Bus A, Bus B or
Bus A and Bus B
BUS A
BUS B
H
BUS B
Real Time Transfer – Bus A to
Bus B
BUS A
OEABHOEBA
CABXCBAXLEABHLEBA
H
Transfer A Stored Data to Bus B
or B Stored Data to Bus A or
Both at the Same Time
BUS A
BUS B
X
BUS B
CAB
OEAB
X
L
L
OEBA
H
X
H
CBA
LEAB
↑
X
L
X
X
X
↑
L
X
Store Bus A in Both Registers or
Store Bus B in Both Registers
BUS A
CAB
CBA
OEAB
H
L
OEBA
H
L
X
X
LEAB
X
L
X
L
LEBA
X
L
L
BUS B
LEBA
L
L
Figure 3. Bus Applications
OEAB
OEBA
H
H
L
L
H
L
BUS A
OEABLOEBA
H
CAB
↑
X
H or L
Isolation
CAB
H or L
CBA
X
↑
H or L
CBA
H or L
LEBA
LEAB
L
X
X
L
L
L
BUS B
LEABLLEBA
L
MOTOROLALCX DATA
4
BR1339 — REV 3
Page 5
MC74LCX16501
ABSOLUTE MAXIMUM RATINGS*
SymbolParameterValueConditionUnit
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
1. Output in HIGH or LOW State. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
SymbolParameterMinTypMaxUnit
V
CC
V
I
V
O
I
OH
I
OL
I
OH
I
OL
T
A
∆t/∆VInput Transition Rise or Fall Rate, VIN from 0.8V to 2.0V ,
DC Supply Voltage–0.5 to +7.0V
DC Input Voltage–0.5 ≤ VI ≤ +7.0V
DC Output Voltage–0.5 ≤ VO ≤ +7.0Output in 3–StateV
–0.5 ≤ VO ≤ VCC + 0.5Note 1.V
DC Input Diode Current–50VI < GNDmA
DC Output Diode Current–50VO < GNDmA
+50VO > V
DC Output Source/Sink Current±50mA
DC Supply Current Per Supply Pin±100mA
DC Ground Current Per Ground Pin±100mA
Storage Temperature Range–65 to +150°C
Supply VoltageOperating
Data Retention Only
Input Voltage05.5V
Output Voltage(HIGH or LOW State)
3. These AC parameters are preliminary and may be modified prior to release.
4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (t
guaranteed by design.
Power–Off Leakage CurrentVCC = 0V; VI or VO = 5.5V10µA
Quiescent Supply Current
Increase in ICC per Input2.7 ≤ VCC ≤ 3.6V; VIH = VCC – 0.6V500µA
Maximum Clock Frequency3170MHz
Propagation Delay
Input to Output
Propagation Delay
Clock to Output
Propagation Delay
LExx to Output
Output Enable Time to
High and Low Level
Output Disable Time From
High and Low Level
Setup Time3,42.52.5ns
Hold Time3,41.51.5ns
Pulse Width Time3,43.03.0ns
Output–to–Output Skew
(Note 4.)
2.7 ≤ VCC ≤ 3.6V; VI = GND or V
2.7 ≤ VCC ≤ 3.6V; 3.6 ≤ VI or VO ≤ 5.5V± 20µA
11.5
31.5
41.5
21.5
21.5
VI = VIH or V
VCC = 3.0V to 3.6VVCC = 2.7V
1.5
1.5
1.5
1.5
1.5
IL
CC
Limits
TA = –40°C to +85°C
6.0
6.0
6.7
6.7
7.0
7.0
7.2
7.2
7.0
7.0
1.0
1.0
) or LOW–to–HIGH (t
OSHL
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
±5.0µA
20µA
7.0
7.0
8.0
8.0
8.0
8.0
8.2
8.2
8.0
8.0
); parameter
OSLH
ns
ns
ns
ns
ns
ns
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
SymbolCharacteristicConditionMinTypMaxUnit
V
OLP
V
OLV
5. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is
measured in the LOW state.
MOTOROLALCX DATA
Dynamic LOW Peak Voltage (Note 5.)VCC = 3.3V, CL = 50pF, VIH = 3.3V, VIL = 0V0.8V
Dynamic LOW Valley Voltage (Note 5.)VCC = 3.3V, CL = 50pF, VIH = 3.3V, VIL = 0V0.8V
6
BR1339 — REV 3
Page 7
MC74LCX16501
CAPACITIVE CHARACTERISTICS
SymbolParameterConditionTypicalUnit
C
IN
C
I/O
C
PD
Input CapacitanceVCC = 3.3V, VI = 0V or V
Input/Output CapacitanceVCC = 3.3V, VI = 0V or V
Power Dissipation Capacitance10MHz, VCC = 3.3V, VI = 0V or V
An, Bn
Bn, An
1.5V
t
, t
PLH
PHL
1.5V
WAVEFORM 1 – An to Bn PROPAGATION DELAYS
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
CC
CC
CC
2.7V
0V
V
OH
V
OL
7pF
8pF
20pF
OEBA
1.5V1.5V
OEAB
t
PZH
An, Bn
t
PZL
An, Bn
WAVEFORM 2 – OEBA/OEAB to An/Bn OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted
An, Bn
LEAB,
LEBA
Bn, An
WAVEFORM 4 – LExx to An, Bn PROPAGATION DELAYS, LExx MINIMUM
An/Bn to CLOCK SETUP AND HOLD TIMES
2.7V
1.5V
0V
1.5V
t
h
2.7V
0V
V
OH
V
OL
t
s
t
PLH
1.5V
t
w
, t
PHL
1.5V
PULSE WIDTH, An, Bn to LExx SETUP AND HOLD TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted
t
NEGATIVE
PULSE
POSITIVE
PULSE
1.5V
1.5V
WAVEFORM 5 – INPUT PULSE DEFINITION
tR = tF = 2.5ns, 10% to 90% of 0V to 2.7V
w
t
w
1.5V
1.5V
Figure 5. AC Waveforms (continued)
MOTOROLALCX DATA
8
BR1339 — REV 3
Page 9
PULSE
GENERATOR
V
CC
DUT
R
T
TESTSWITCH
t
, t
PLH
PHL
t
, t
PZL
PLZ
Open Collector/Drain t
t
, t
PZH
PHZ
CL = 50pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = Z
of pulse generator (typically 50Ω)
OUT
PLH
and t
PHL
C
R
L
Open
6V
6V
GND
Figure 6. T est Circuit
MC74LCX16501
6V
R
1
L
OPEN
GND
LCX DATABR1339 — REV 3
9MOTOROLA
Page 10
MC74LCX16501
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 1202–01
ISSUE A
S
U
M
L
0.254 (0.010)T
0.076 (0.003)
–T–
SEATING
PLANE
–U–
PIN 1
IDENT.
K
56X REF
0.12 (0.005)V
M
S
U
T
S
J
2956
B
128
N
A
–V–
N
DETAIL E
D
C
K
K1
J1
SECTION N–N
F
0.25 (0.010)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/ Locations Not Listed: Motorola Literature Distribution;JAP AN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–24473–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315
Mfax: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://www.mot.com/SPS/
– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
◊
MOTOROLALCX DATA
10
Mfax is a trademark of Motorola, Inc.
MC74LCX16501/D
BR1339 — REV 3
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