Page 1
SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC74HCU04A is identical in pinout to the LS04 and the MC14069UB.
The device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of six single–stage inverters. These inverters are well
suited for use as oscillators, pulse shapers, and in many other applications
requiring a high–input impedance amplifier. For digital applications, the
HC04A is recommended.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V; 2.5 to 6 V in Oscillator
Configurations
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 12 FETs or 3 Equivalent Gates
LOGIC DIAGRAM
Y1A1
A2
A3
A4
A5
A6
Y2
Y3
Y4
Y5
Y6
1
3
5
9
11
13
2
4
6
8
10
12
Y = A
PIN 14 = V
CC
PIN 7 = GND
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
FUNCTION TABLE
PIN ASSIGNMENT
Inputs
A
L
H
11
12
13
14
8
9
105
4
3
2
1
7
6
Y5
A5
Y6
A6
V
CC
Y4
A4
Y2
A2
Y1
A1
GND
Y3
A3
Outputs
Y
H
L
D SUFFIX
SOIC PACKAGE
CASE 751A–03
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
ORDERING INFORMATION
MC74HCUXXAN
MC74HCUXXAD
MC74HCUXXADT
Plastic
SOIC
TSSOP
1
14
1
14
1
14
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
Page 2
MC74HCU04A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 50
mA
P
D
Power Dissipation in Still Air Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: –10mW/_C from 65_ to 125_C
SOIC Package: –7mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time (Figure 1)
—
No
Limit
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.5 V*
|I
out
| v 20 µA
2.0
3.0
4.5
6.0
1.7
2.5
3.6
4.8
1.7
2.5
3.6
4.8
l.7
2.5
3.6
4.8
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= VCC – 0.5 V*
|I
out
| v 20 µA
2.0
3.0
4.5
6.0
0.3
0.5
0.8
1.1
0.3
0.5
0.8
1.1
0.3
0.5
0.8
1.1
V
Vin = GND
|I
out
| v 20 µA
2.0
4.5
6.0
1.8
4.0
5.5
1.8
4.0
5.5
1.8
4.0
5.5
Vin = GND |I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
3.0
4.5
6.0
2.36
3.86
5.36
2.26
3.76
5.26
2.20
3.70
5.20
Vin = V
CC
|I
out
| v 20 µA
2.0
4.5
6.0
0.2
0.5
0.5
0.2
0.5
0.5
0.2
0.5
0.5
Vin = V
CC
|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
3.0
4.5
6.0
0.32
0.32
0.32
0.32
0.37
0.37
0.32
0.40
0.40
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
V
OH
V
OL
Minimum High–Level Output
Voltage
Maximum Low–Level Output
Voltage
V
V
Page 3
MC74HCU04A
High–Speed CMOS Logic Data
DL129 — Rev 6
3 MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Unit
v
125_C
v
85_C
– 55 to
25_C
V
CC
V
Test Conditions
Parameter
Symbol
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
I
out
= 0 µA
6.0
1
10
40
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
*For VCC = 2.0 V, V
out
= 0.2 V or VCC – 0.2 V.
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
80
40
16
14
100
45
20
17
120
50
24
20
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
C
in
Maximum Input Capacitance
—
10
10
10
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
15
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
C
PD
Power Dissipation Capacitance (Per Inverter)*
pF
Page 4
MC74HCU04A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
Figure 1. Switching Waveforms
t
r
V
CC
GND
90%
50%
10%
90%
50%
10%
INPUT A
OUTPUT Y
t
PHL
t
PLH
t
THL
t
TLH
*Includes all probe and jig capacitance
Figure 2. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
LOGIC DETAIL
(1/6 of Device Shown)
t
f
A
V
CC
Y
Page 5
MC74HCU04A
High–Speed CMOS Logic Data
DL129 — Rev 6
5 MOTOROLA
Crystal Oscillator Stable RC Oscillator
Schmitt Trigger High Input Impedance Single–Stage Amplifier
with a 2 to 6 V Supply Range
Multi–Stage Amplifier LED Driver
For reduced power supply current, use high–efficiency
LEDs
such as the Hewlett–Packard HLMP series or equivalent.
R
2
1/6 HCU04
C
1
R2 > > R
1
C1 < C
2
V
out
C
2
R
1
R
2
R
1
C
1/6 HCU041/6 HCU041/6 HCU04
V
out
R
2
R
1
V
in
V
out
1/6 HCU04 1/6 HCU04
R2 > 6R
1
V
CC
INPUT OUTPUT
1 M
1 M
1/6 HCU04
V
CC
INPUT OUTPUT
1/6 HCU04 1/6 HCU04 1/6 HCU04
+V
1/6 HCU04
TYPICAL APPLICATIONS
Page 6
MC74HCU04A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
6
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
1 7
14 8
B
A
F
H G D
K
C
N
L
J
M
SEATING
PLANE
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
M 0 10 0 10
N 0.015 0.039 0.39 1.01
_ _ _ _
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
0.19
0.10
0
°
5.80
0.25
8.75
4.00
1.75
0.49
1.25
0.25
0.25
7
°
6.20
0.50
0.337
0.150
0.054
0.014
0.016
0.008
0.004
0
°
0.228
0.010
0.344
0.157
0.068
0.019
0.049
0.009
0.009
7
°
0.244
0.019
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
P 7 PL
G
C
K
SEATING
PLANE
D 14 PL
M
J
R
X 45°
1
7
814
0.25 (0.010) T B A
M
S S
B0.25 (0.010)
M M
F
Page 7
MC74HCU04A
High–Speed CMOS Logic Data
DL129 — Rev 6
7 MOTOROLA
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
_ _ _ _
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V
S
T
L
–U–
SEATING
PLANE
0.10 (0.004)
–T–
SECTION N–N
DETAIL E
J
J1
K
K1
DETAIL E
F
M
–W–
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
–V–
14X REFK
N
N
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MC74HCU04A/D
*MC74HCU04A/D*
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