Datasheet MC74HCU04ADTEL, MC74HCU04ADTR2, MC74HCU04AF, MC74HCU04AFEL, MC74HCU04AD Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 2

1 Publication Order Number:

MC74HCU04A/D

MC74HCU04A

Hex Unbuffered Inverter

High–Performance Silicon–Gate CMOS

The MC74HCU04A is identical in pinout to the LS04 and the
MC14069UB. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.

This device consists of six single–stage inverters. These inverters
are well suited for use as oscillators, pulse shapers, and in many other
applications requiring a high–input impedance amplifier. For digital
applications, the HC04A is recommended.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V; 2.5 to 6 V in Oscillator

Configurations

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 12 FETs or 3 Equivalent Gates

LOGIC DIAGRAM

Y1A1

A2

A3

A4

A5

A6

Y2

Y3

Y4

Y5

Y6

1

3

5

9

11

13

2

4

6

8

10

12

Y = A

PIN 14 = V

CC

PIN 7 = GND

FUNCTION TABLE

Inputs

A

L
H

Outputs

Y

H
L

Device Package Shipping

ORDERING INFORMATION

MC74HCU04AN PDIP–14 2000 / Box
MC74HCU04AD SOIC–14

http://onsemi.com

55 / Rail

MC74HCU04ADR2 SOIC–14 2500 / Reel

MARKING

DIAGRAMS

A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

MC74HCU04ADT TSSOP–14 96 / Rail
MC74HCU04ADTR2 TSSOP–14

2500 / Reel

TSSOP–14
DT SUFFIX

CASE 948G

HCU

04A

ALYW

1

14

1

14

PDIP–14

N SUFFIX

CASE 646

MC74HCU04AN

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

1

14

HCU04A

AWLYWW

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

Y5

A5

Y6

A6

V

CC

Y4

A4

Y2

A2

Y1

A1

GND

Y3

A3

MC74HCU04A

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2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎ

Î

750
500
450

Î

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

ÎÎ

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

ÎÎÎ

Î

260

Î

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: –10mW/_C from 65_ to 125_C

SOIC Package: –7mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

ÎÎ

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature, All Package T ypes

– 55

ÎÎ

+ 125

_

C

tr, t

f

Input Rise and Fall Time (Figure 1)

—

ÎÎ

No

Limit

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Î

Symbol

ООООООО

Î

Parameter

ООООООО

Î

Test Conditions

ÎÎ

Î

V

CC
V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

Î

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎ

Î

ÎÎ

Î

V

IH

ООООООО

Î

ООООООО

Î

Minimum High–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.5 V*

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1.7

2.5

3.6

4.8

ÎÎÎ

Î

Î

Î

Î

Î

Î

1.7

2.5

3.6

4.8

ÎÎ

Î

ÎÎ

Î

l.7

2.5

3.6

4.8

Î

Î

Î

Î

V

ÎÎ

Î

V

IL

ООООООО

Î

Maximum Low–Level Input
Voltage

ООООООО

Î

V

out

= VCC – 0.5 V*

|I

out

| v 20 µA

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

0.3

0.5

0.8

1.1

ÎÎÎ

Î

Î

Î

0.3

0.5

0.8

1.1

ÎÎ

Î

0.3

0.5

0.8

1.1

Î

Î

V

ÎÎ

Î

ÎÎ

Î

V

OH

ООООООО

Î

ООООООО

Î

Minimum High–Level Output
Voltage

ООООООО

Î

ООООООО

Î

Vin = GND
|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1.8

4.0

5.5

ÎÎÎ

Î

Î

Î

Î

Î

Î

1.8

4.0

5.5

ÎÎ

Î

ÎÎ

Î

1.8

4.0

5.5

Î

Î

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = GND |I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

2.36

3.86

5.36

ÎÎÎ

Î

Î

Î

2.26

3.76

5.26

ÎÎ

Î

2.20

3.70

5.20

Î

Î

ÎÎ

Î

V

OL

ООООООО

Î

Maximum Low–Level Output
Voltage

ООООООО

Î

Vin = V

CC

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

0.2

0.5

0.5

ÎÎÎ

Î

Î

Î

0.2

0.5

0.5

ÎÎ

Î

0.2

0.5

0.5

Î

Î

V

ÎÎ

Î

ÎÎ

Î

ООООООО

Î

ООООООО

Î

ООООООО

Î

ООООООО

Î

Vin = V

CC

|I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

ÎÎ

Î

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

0.32

0.32

0.32

ÎÎÎ

Î

Î

Î

Î

Î

Î

0.32

0.37

0.37

ÎÎ

Î

ÎÎ

Î

0.32

0.40

0.40

Î

Î

Î

Î

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HCU04A

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3

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Unit

v

125_C

ÎÎÎ

v

85_C

– 55 to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

ÎÎ

Î

I

in

ООООООО

Î

Maximum Input Leakage
Current

ООООООО

Î

Vin = VCC or GND

ÎÎ

Î

6.0

ÎÎ

Î

± 0.1

ÎÎÎ

Î

Î

Î

± 1.0

ÎÎ

Î

± 1.0

Î

Î

µA

ÎÎ

Î

I

CC

ООООООО

Î

Maximum Quiescent Supply
Current (per Package)

ООООООО

Î

Vin = VCC or GND
I

out

= 0 µA

ÎÎ

Î

6.0

ÎÎ

Î

1

ÎÎÎ

Î

Î

Î

10

ÎÎ

Î

40

Î

Î

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
*For VCC = 2.0 V, V

out

= 0.2 V or VCC – 0.2 V.

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

ÎÎÎ

Î

Symbol

ОООООООООООООО

Î

Parameter

ÎÎ

Î

V

CC
V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

Î

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Input A to Output Y

(Figures 1 and 2)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

70
40
14
12

ÎÎÎ

Î

Î

Î

Î

Î

Î

90
45
18
15

ÎÎ

Î

ÎÎ

Î

105

50
21
18

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

TLH

,

t

THL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Output Transition Time, Any Output

(Figures 1 and 2)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

75
27
15
13

ÎÎÎ

Î

Î

Î

Î

Î

Î

95
32
19
16

ÎÎ

Î

ÎÎ

Î

110

36
22
19

Î

Î

Î

Î

ns

C

in

Maximum Input Capacitance

—

10

ÎÎÎ

10

10

pF

NOTES:

1. For propagation delays with loads other than 50 pF , see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Inverter)*

15

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

MC74HCU04A

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4

Figure 1. Switching Waveforms

t

r

V

CC

GND

90%
50%

10%

90%

50%

10%

INPUT A

OUTPUT Y

t

PHL

t

PLH

t

THL

t

TLH

*Includes all probe and jig capacitance

Figure 2. Test Circuit

CL*

TEST

POIN

T

DEVICE
UNDER

TEST

OUTPUT

LOGIC DETAIL

(1/6 of Device Shown)

t

f

A

V

CC

Y

MC74HCU04A

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5

Crystal Oscillator Stable RC Oscillator

Schmitt Trigger High Input Impedance Single–Stage Amplifier

with a 2 to 6 V Supply Range

Multi–Stage Amplifier LED Driver

For reduced power supply current, use high–efficiency LEDs
such as the Hewlett–Packard HLMP series or equivalent.

R

2

1/6 HCU04A

C

1

R2 > > R

1

C1 < C

2

V

out

C

2

R

1

R

2

R

1

C

1/6 HCU04A1/6 HCU04A1/6 HCU04A

V

out

R

2

R

1

V

in

V

out

1/6 HCU04A 1/6 HCU04A

R2 > 6R

1

V

CC

INPUT OUTPUT

1 M

1 M

1/6 HCU04A

V

CC

INPUT OUTPUT

1/6 HCU04A 1/6 HCU04A 1/6 HCU04A

+V

1/6 HCU04A

TYPICAL APPLICATIONS

MC74HCU04A

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6

P ACKAGE DIMENSIONS

PDIP–14

N SUFFIX

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

4. ROUNDED CORNERS OPTIONAL.

17

14 8

B

A

F

HG D

K

C

N

L

J

M

SEATING
PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78

G 0.100 BSC 2.54 BSC

H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC

M 0 10 0 10

N 0.015 0.039 0.39 1.01

____

SOIC–14

D SUFFIX

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

G

P

7 PL

14 8

71

M

0.25 (0.010) B

M

S

B

M

0.25 (0.010) A

S

T

–T–

F

R

X 45

SEATING
PLANE

D 14 PL

K

C

J

M

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

____

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7

P ACKAGE DIMENSIONS

TSSOP–14
DT SUFFIX

CASE 948G–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V

S

T

L

–U–

SEATING
PLANE

0.10 (0.004)

–T–

SECTION N–N

DETAIL E

J

J1

K

K1

DETAIL E

F

M

–W–

0.25 (0.010)

8

14

7

1

PIN 1
IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

–V–

14X REFK

N

N

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