Datasheet MC74HCT74ADT, MC74HCT74AN, MC74HCT74AD, MC74HCT74ADR2 Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 8

1 Publication Order Number:

MC74HCT74A/D

MC74HCT74A

Dual D Flip-Flop with Set
and Reset with LSTTL
Compatible Inputs

High–Performance Silicon–Gate CMOS

The MC74HCT74A is identical in pinout to the LS74. This device
may be used as a level converter for interfacing TTL or NMOS outputs
to High Speed CMOS inputs.

This device consists of two D flip–flops with individual Set, Reset,
and Clock inputs. Information at a D–input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q

outputs are available from each flip–flop. The Set

and Reset inputs are asynchronous.

• Output Drive Capability: 10 LSTTL Loads

• TTL NMOS Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 1.0 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 136 FETs or 34 Equivalent Gates

LOGIC DIAGRAM

RESET 1

DATA 1

CLOCK 1

SET 1

RESET 2

DATA 2

CLOCK 2

SET 2

1

2
3

4

13

12
11

10

5
6

9
8

Q1

Q1

Q2

Q2

PIN 14 = VCC
PIN 7 = GND

Design Criteria

Value

Units

Internal Gate Count*

34

ea.

Internal Gate Propagation Delay

1.5

ns

ОООООООО

Î

Internal Gate Power Dissipation

ÎÎ

Î

5.0

Î

Î

µW

Speed Power Product

.0075

pJ

*Equivalent to a two–input NAND gate.

Device Package Shipping

ORDERING INFORMATION

MC74HCT74AN PDIP–14 2000 / Box
MC74HCT74AD SOIC–14

http://onsemi.com

55 / Rail

MC74HCT74ADR2 SOIC–14 2500 / Reel

MARKING

DIAGRAMS

A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

1

14

PDIP–14
N SUFFIX
CASE 646

MC74HCT74AN

AWLYYWW

SOIC–14
D SUFFIX

CASE 751A

1

14

HCT74A

AWLYWW

FUNCTION TABLE

PIN ASSIGNMENT

Inputs Outputs

Set Reset Clock Data Q Q

LH XX HL
HL XX LH
L L X X H* H*
HH H HL
HH L LH
H H L X No Change
H H H X No Change
H H X No Change

*Both outputs will remain high as long as Set and

Reset are low, but the output states are unpredict­able if Set and Reset go high simultaneously.

SET 1

CLOCK 1

DATA 1

RESET 1

11

12

13

14

8

9

105

4

3

2

1

7

6

SET 2

CLOCK 2

DATA 2

RESET 2

V

CC

Q2

Q2

GND

Q1

Q1

MC74HCT74A

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2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

ÎÎÎ

Î

750
500

Î

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: –10mW/_C from 65_ to 125_C

SOIC Package: –7mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎ

Î

Symbol

ООООООООООООО

Î

Parameter

Î

Î

Min

ÎÎ

Max

Î

Î

Unit

ÎÎ

Î

V

CC

ООООООООООООО

Î

DC Supply Voltage (Referenced to GND)

Î

Î

4.5

ÎÎ

5.5

Î

Î

V

ÎÎ

Vin, V

out

ООООООООООООО

DC Input Voltage, Output Voltage (Referenced to GND)Î0

ÎÎ

V

CC

Î

V

ÎÎ

T

A

ООООООООООООО

Operating Temperature, All Package Types

Î

– 55

ÎÎ

+ 125

Î

_

C

ÎÎ

tr, t

f

ООООООООООООО

Input Rise and Fall Time (Figure 1)

Î

0

ÎÎ

500Îns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC
V

– 55 to

25_C

ÎÎÎ

v

85_Cv 125_C

Unit

ÎÎ

Î

V

IH

ООООООО

Î

Minimum High–Level Input
Voltage

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

4.5

5.5

ÎÎ

Î

2.0

2.0

ÎÎÎ

Î

Î

Î

2.0

2.0

ÎÎ

Î

2.0

2.0

Î

Î

V

ÎÎ

Î

V

IL

ООООООО

Î

Maximum Low–Level Input
Voltage

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

4.5

5.5

ÎÎ

Î

0.8

0.8

ÎÎÎ

Î

Î

Î

0.8

0.8

ÎÎ

Î

0.8

0.8

Î

Î

V

V

OH

Minimum High–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

4.5

5.5

4.4

5.4

ÎÎÎ

4.4

5.4

4.4

5.4

V

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or V

IL

|I

out

| v 4.0 mA

ÎÎ

Î

4.5

ÎÎ

Î

3.98

ÎÎÎ

Î

Î

Î

3.84

ÎÎ

Î

3.7

Î

Î

ÎÎ

Î

V

OL

ООООООО

Î

Maximum Low–Level Output
Voltage

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

4.5

5.5

ÎÎ

Î

0.1

0.1

ÎÎÎ

Î

Î

Î

0.1

0.1

ÎÎ

Î

0.1

0.1

Î

Î

V

Vin = VIH or V

IL

|I

out

| v 4.0 mA

4.5

0.26

ÎÎÎ

0.33

0.4

ÎÎ

Î

I

in

ООООООО

Î

Maximum Input Leakage
Current

ООООООО

Î

Vin = VCC or GND

ÎÎ

Î

5.5

ÎÎ

Î

± 0.1

ÎÎÎ

Î

Î

Î

± 1.0

ÎÎ

Î

± 1.0

Î

Î

µA

ÎÎ

Î

I

CC

ООООООО

Î

Maximum Quiescent Supply
Current (per Package)

ООООООО

Î

Vin = VCC or GND
I

out

= 0 µA

ÎÎ

Î

5.5

ÎÎ

Î

2.0

ÎÎÎ

Î

Î

Î

20

ÎÎ

Î

80

Î

Î

µA

ÎÎ

Î

∆I

CC

ООООООО

Î

Additional Quiescent Supply

ООООООО

Î

Vin = 2.4 V , Any One Input

p

ÎÎÎÎÎ

Î

≥–55_C

ÎÎÎÎ

Î

25_C to 125_C

Î

Î

Current

V

i

n

=

V

CC

or

GND, Other In uts

l

out

= 0 µA

5.5

2.9

2.4

mA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HCT74A

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3

AC ELECTRICAL CHARACTERISTICS (V

CC

= 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

Symbol Parameter

– 55 to

25_C

v

85_C

v

125_C

Unit

f

max

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

30

24

20

MHz

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООООО

Î

Maximum Propagation Delay, Clock to Q or Q

(Figures 1 and 4)

ÎÎ

Î

24

ÎÎ

Î

30

ÎÎ

Î

36

Î

Î

ns

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООООО

Î

Maximum Propagation Delay, Set or Reset to Q or Q

(Figures 2 and 4)

ÎÎ

Î

24

ÎÎ

Î

30

ÎÎ

Î

36

Î

Î

ns

ÎÎÎ

Î

t

TLH

,

t

THL

ОООООООООООООООО

Î

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

ÎÎ

Î

15

ÎÎ

Î

19

ÎÎ

Î

22

Î

Î

ns

C

in

Maximum Input Capacitance

10

10

10

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Enabled Output)*

32

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (V

CC

= 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

ÎÎ

– 55 to

25_C

v

85_C

v

125_C

ÎÎ

Symbol

Parameter

Fig.

Min

Max

Min

Max

Min

Max

ÎÎ

Units

t

su

Minimum Setup Time, Data to Clock

3

15

19

22

ÎÎ

ns

t

h

Minimum Hold Time, Clock to Data

3

3

3

3

ÎÎ

ns

t

rec

Minimum Recovery Time, Set or Reset Inactive to Clock

2

6

8

9

ÎÎ

ns

t

w

Minimum Pulse Width, Clock

1

15

19

22

ÎÎ

ns

t

w

Minimum Pulse Width, Set or Reset

2

15

19

22

ÎÎ

ns

tr, tfMaximum Input Rise and Fall Times

1

500

500

500

ÎÎ

ns

MC74HCT74A

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4

SWITCHING W AVEFORMS

1/f

max

Figure 1.

CLOCK

Q OR Q

t

f

t

r

3 V

GND

2.7 V

1.3 V

0.3 V

90%

1.3 V

10%

t

PLH

t

PHL

t

TLH

t

THL

t

w

Figure 2.

GND

SET OR

RESET

Q

OR Q

Q OR Q

CLOCK

t

PLH

t

PHL

DATA

CLOCK

Figure 3.

VALID

t

su

t

h

t

rec

t

w

EXPANDED LOGIC DIAGRAM

SET

DATA

RESET

4, 10

2, 12

1, 13

CLOCK

3, 11

5, 9

6, 8

Q

Q

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

Figure 4.

3 V

GND

3 V

1.3 V

1.3 V

1.3 V

1.3 V

GND

3 V

GND

3 V

1.3 V

1.3 V

MC74HCT74A

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5

P ACKAGE DIMENSIONS

PDIP–14

N SUFFIX

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

4. ROUNDED CORNERS OPTIONAL.

17

14 8

B

A

F

HG D

K

C

N

L

J

M

SEATING
PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78

G 0.100 BSC 2.54 BSC

H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC

M 0 10 0 10

N 0.015 0.039 0.39 1.01

____

SOIC–14

D SUFFIX

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

G

P

7 PL

14 8

71

M

0.25 (0.010) B

M

S

B

M

0.25 (0.010) A

S

T

–T–

F

R

X 45

SEATING
PLANE

D 14 PL

K

C

J

M

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

____

MC74HCT74A

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Notes

MC74HCT74A

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Notes

MC74HCT74A

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8

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