Datasheet MC74HCT245AFL1, MC74HCT245AH, MC74HCT245AN, MC74HCT245ADWR2, MC74HCT245ADT Datasheet (MOTOROLA)
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Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 8
1 Publication Order Number:
MC74HCT245A/D
MC74HCT245A
Octal 3-State Noninverting
Bus Transceiver with LSTTL
Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT245A is identical in pinout to the LS245. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High Speed CMOS inputs.
The MC74HCT245A is a 3–state noninverting transceiver that is
used for 2–way asynchronous communication between data buses.
The device has an active–low Output Enable pin, which is used to
place the I/O ports into high–impedance states. The Direction control
determines whether data flows from A to B or from B to A.
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 304 FETs or 76 Equivalent Gates
LOGIC DIAGRAM
A
DATA
PORT
A8
A7
A6
A5
A3
A4
A2
A1
9
8
7
6
5
4
3
2
DIRECTION
OUTPUT ENABLE
1
19
PIN 20 = V
CC
PIN 10 = GND
18
17
16
15
14
13
12
11
B1
B2
B3
B4
B5
B6
B7
B8
B
DATA
PORT
Design Criteria
Value
Units
Internal Gate Count*
76
ea
Internal Gate Propagation Delay
1.0
ns
Internal Gate Power Dissipation
5.0
µW
Speed Power Product
0.005
pJ
*Equivalent to a two–input NAND gate.
FUNCTION TABLE
Control Inputs
Output
Enable
Direction
Operation
L L Data Transmitted from Bus B to Bus A
L H Data Transmitted from Bus A to Bus B
H X Buses Isolated (High–Impedance State)
X = Don’t Care
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MARKING
DIAGRAMS
1
20
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
SOIC WIDE–20
DW SUFFIX
CASE 751D
HCT245A
AWLYYWW
PDIP–20
N SUFFIX
CASE 738
1
20
MC74HCT245AN
AWLYYWW
TSSOP–20
DT SUFFIX
CASE 948G
1
20
1
20
1
20
Device Package Shipping
ORDERING INFORMATION
MC74HCT245AN PDIP–20 1440 / Box
MC74HCT245ADW SOIC–WIDE
38 / Rail
MC74HCT245ADWR2 SOIC–WIDE 1000 / Reel
MC74HCT245ADT TSSOP–20 75 / Rail
MC74HCT245ADTR2 TSSOP–20
2500 / Reel
HCT
245A
ALYW
1
20
PIN ASSIGNMENT
A5
A3
A2
A1
DIRECTION
GND
A8
A7
A6
A4 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
B3
B2
B1
OUTPUT ENABLE
V
CC
B8
B7
B6
B5
B4
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MC74HCT245A
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2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 35
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
ÎÎ
Î
P
D
ОООООООООООО
Î
Power Dissipation in Still Air, Plastic DIP†
SOIC Package†
TSSOP Package†
ÎÎÎ
Î
750
500
450
Î
Î
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
ÎÎ
Î
T
L
ОООООООООООО
Î
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
ÎÎÎ
Î
260
Î
Î
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
ÎÎ
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
4.5
ÎÎ
5.5
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
ÎÎ
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
ÎÎ
+ 125
_
C
tr, t
f
Input Rise and Fall Time (Figure 1)
0
ÎÎ
500
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
ÎÎÎ
v
85_Cv 125_C
Unit
ÎÎ
Î
V
IH
ООООООО
Î
Minimum High–Level Input
Voltage
ООООООО
Î
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
ÎÎ
Î
4.5
5.5
ÎÎ
Î
2.0
2.0
ÎÎÎ
Î
Î
Î
2.0
2.0
ÎÎ
Î
2.0
2.0
Î
Î
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
4.5
5.5
0.8
0.8
ÎÎÎ
0.8
0.8
0.8
0.8
V
ÎÎ
Î
V
OH
ООООООО
Î
Minimum High–Level Output
Voltage
ООООООО
Î
Vin = VIH or V
IL
|I
out
| v 20 µA
ÎÎ
Î
4.5
5.5
ÎÎ
Î
4.4
5.4
ÎÎÎ
Î
Î
Î
4.4
5.4
ÎÎ
Î
4.4
5.4
Î
Î
V
Vin = VIH or V
IL
|I
out
| v 6.0 mA
4.5
3.98
ÎÎÎ
3.84
3.7
ÎÎ
Î
V
OL
ООООООО
Î
Maximum Low–Level Output
Voltage
ООООООО
Î
Vin = VIH or V
IL
|I
out
| v 20 µA
ÎÎ
Î
4.5
5.5
ÎÎ
Î
0.1
0.1
ÎÎÎ
Î
Î
Î
0.1
0.1
ÎÎ
Î
0.1
0.1
Î
Î
V
Vin = VIH or V
IL
|I
out
| v 6.0 mA
4.5
0.26
ÎÎÎ
0.33
0.4
I
in
Maximum Input Leakage Current
Vin = VCC or GND, Pins 1 or 19
5.5
± 0.1
ÎÎÎ
± 1.0
± 1.0
µA
ÎÎ
Î
I
CC
ООООООО
Î
Maximum Quiescent Supply
Current (per Package)
ООООООО
Î
Vin = VCC or GND
I
out
= 0 µA
ÎÎ
Î
5.5
ÎÎ
Î
4.0
ÎÎÎ
Î
Î
Î
40
ÎÎ
Î
160
Î
Î
µA
ÎÎ
Î
I
OZ
ООООООО
Î
Maximum Three–State
Leakage Current
ООООООО
Î
Output in High–Impedance State
Vin = VIL or V
IH
V
out
= VCC or GND, I/O Pins
ÎÎ
Î
5.5
ÎÎ
Î
± 0.5
ÎÎÎ
Î
Î
Î
± 5.0
ÎÎ
Î
± 10
Î
Î
µA
∆I
CC
Additional Quiescent Supply
Vin = 2.4 V, Any One Input
p
≥ –55_C
25_C to 125_C
Current
V
i
n
=
V
CC
or
GND, Other In uts
l
out
= 0 µA
5.5
2.9
2.4
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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MC74HCT245A
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AC ELECTRICAL CHARACTERISTICS (V
CC
= 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
ÎÎÎ
Î
Symbol
ОООООООООООООООО
Î
Parameter
ÎÎ
Î
– 55 to
25_C
ÎÎ
Î
v
85_C
ÎÎ
Î
v
125_C
Î
Î
Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, A to B or B to A
(Figures 1 and 3)
22
28
33
ns
ÎÎÎ
Î
t
PLZ
,
t
PHZ
ОООООООООООООООО
Î
Maximum Propagation Delay, Direction or Output Enable to A or B
(Figures 2 and 4)
ÎÎ
Î
30
ÎÎ
Î
36
ÎÎ
Î
42
Î
Î
ns
ÎÎÎ
Î
t
PZL
,
t
PZH
ОООООООООООООООО
Î
Maximum Propagation Delay, Output Enable to A or 8
(Figures 2 and 4)
ÎÎ
Î
30
ÎÎ
Î
36
ÎÎ
Î
42
Î
Î
ns
t
TLH
,
t
THL
Maximum Output Transition Time. any Output
(Figures 1 and 3)
12
15
18
ns
C
in
Maximum Input Capacitance (Pin 1 or 19)
10
10
10
pF
ÎÎÎ
Î
C
out
ОООООООООООООООО
Î
Maximum Three–State I/O Capacitance, (I/O in High–Impedance
State)
ÎÎ
Î
15
ÎÎ
Î
15
ÎÎ
Î
15
Î
Î
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
97
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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MC74HCT245A
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SWITCHING W AVEFORMS
3.0 V
GND
t
f
t
r
INPUT
A OR B
OUTPUT
B OR A
0.3 V
1.3 V
2.7 V
10%
1.3 V
90%
t
TLH
t
PLH
t
PHL
t
THL
Figure 1.
OUTPUT
ENABLE
A OR B
A OR B
1.3 V
1.3 V
1.3 V
90%
10%
t
PZL
t
PLZ
t
PZHtPHZ
3.0 V
GND
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
3.0 V
GND
1.3 V 1.3 V
Figure 2.
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 3.
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4. Test Circuit
CONNECT TO VCC WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
1 kΩ
DIRECTION
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EXPANDED LOGIC DIAGRAM
A
DATA
PORT
B
DATA
PORT
OUTPUT ENABLE
DIRECTION
A1
A2
A3
A4
A5
A6
A7
A8
2
3
4
5
6
7
8
9
19
1
B1
B2
B3
B4
B5
B6
B7
B8
18
17
16
15
14
13
12
11
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P ACKAGE DIMENSIONS
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
PDIP–20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J
20 PL
M
B
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022
G 2.54 BSC0.100 BSC
J 0.21 0.380.008 0.015
K 2.80 3.550.110 0.140
L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040
____
E
1.27 1.770.050 0.070
1
11
10
20
–A–
SEATING
PLANE
K
N
FG
D
20 PL
–T–
M
A
M
0.25 (0.010) T
E
B
C
F
1.27 BSC0.050 BSC
20
1
11
10
B20X
H10X
C
L
18X
A1
A
SEATING
PLANE
q
h X 45
_
E
D
M
0.25
M
B
M
0.25
SAS
B
T
e
T
B
A
DIM MIN MAX
MILLIMETERS
A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90
q
0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
__
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P ACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
CASE 948E–02
ISSUE A
DIMAMIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B 4.30 4.50 0.169 0.177
C 1.20 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
110
1120
PIN 1
IDENT
A
B
–T–
0.100 (0.004)
C
D
G
H
SECTION N–N
K
K1
JJ1
N
N
M
F
–W–
SEATING
PLANE
–V–
–U–
S
U
M
0.10 (0.004) V
S
T
20X REFK
L
L/2
2X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E
6.40 0.252
––– –––
S
U0.15 (0.006) T
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MC74HCT245A
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8
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