Datasheet MC74HCT174AN, MC74HCT174AD Datasheet (Motorola)

Page 1

SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
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High–Performance Silicon–Gate CMOS
The MC74HCT174A is identical in pinout to the LS174. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.
This device consists of six D flip–flops with common Clock and Reset inputs. Each flip–flop is loaded with a low–to–high transition of the Clock input. Reset is asynchronous and active–low.
Output Drive Capability: 10 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 178 FETs or 44.5 Equivalent Gates
LOGIC DIAGRAM
PIN 16 = V
CC
PIN 8 = GND
3 4
6 11 13 14
2 5
7 10 12 15
D0 D1 D2 D3 D4 D5
Q0 Q1
Q2 Q3 Q4 Q5
CLOCK
9
RESET
1
DATA
INPUTS
NONINVERTING
OUTPUTS
Design Criteria
Value
Units
Internal Gate Count*
44.5
ea.
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
0.005
µW
Speed Power Product
0.0075
pJ
*Equivalent to a two–input NAND gate.

PIN ASSIGNMENT
FUNCTION TABLE
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Q4
D4
D5
Q5
V
CC
CLOCK
Q3
D3
D1
D0
Q0
RESET
GND
Q2
D2
Q1
Inputs Output
Reset Clock D Q
L X X L H H H H L L H L X No Change H X No Change
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
1
16
1
16
ORDERING INFORMATION
MC74HCXXXAN MC74HCXXXAD
Plastic SOIC
Page 2
MC74HCT174A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 50
mA
P
D
Power Dissipation in Still Air Plastic DIP†
SOIC Package†
750 500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
4.5
5.5
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time (Figure 1)
0
500
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC V
– 55 to
25_C
85_C
125_C
Unit
V
IH
Minimum High–Level Input Voltage
V
out
= 0.1 or VCC – 0.1 V
|I
out
| v 20 µA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
V
IL
Maximum Low–Level Input Voltage
V
out
= 0.1 or VCC – 0.1 V
|I
out
| v 20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
OH
Minimum High–Level Output Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
Vin = VIH or V
IL
|I
out
| v 4.0 mA
4.5
3.98
3.84
3.70
V
OL
Maximum Low–Level Output Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or V
IL
|I
out
| v 4.0 mA
4.5
0.26
0.33
0.4
I
in
Maximum Input Leakage Current
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
µA
I
CC
Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND I
out
= 0 µA
5.5
4.0
40
160
µA
I
CC
Additional Quiescent Supply
Vin = 2.4 V, Any One Input
– 55_C
25_C to 125_C
Current
Vin = VCC or GND, Other Inputs l
out
= 0 µA
5.5
2.9
2.4
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance cir­cuit. For proper operation, Vin and V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Page 3
MC74HCT174A
High–Speed CMOS Logic Data DL129 — Rev 6
3 MOTOROLA
AC ELECTRICAL CHARACTERISTICS (V
CC
= 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
– 55 to
25_C
v
85_C
v
125_C
Unit
f
MAX
Maximum Clock Frequency (50% Duty Cycle)
30
24
20
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
24
30
36
ns
t
PHL
Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)
23
28
35
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
15
19
22
ns
C
in
Maximum Input Capacitance
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
79
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (V
CC
= 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to 25_C
v
85_C
v
125_C
Symbol
Parameter
Fig.
Min
Max
Min
Max
Min
Max
Unit
t
su
Minimum Setup Time, Data to Clock
3
10
13
15
ns
t
h
Minimum Hold Time, Clock to Data
3
5.0
6.0
8.0
ns
t
rec
Minimum Recovery Time, Reset Inactive to Clock
2
5.0
6.0
8.0
ns
t
w
Minimum Pulse Width, Clock
1
15
19
22
ns
t
w
Minimum Pulse Width, Reset
2
15
19
22
ns
tr, t
f
Maximum Input Rise and Fall Times
1
500
500
500
ns
Page 4
MC74HCT174A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
SWITCHING WAVEFORMS
CLOCK
9
D0
3
RESET
1
D1
4
D2
6
D3
11
D4
13
D5
14
C
Q
D
R
2
5
7
10
12
15
Q0
Q1
Q2
Q3
Q4
Q5
EXPANDED LOGIC DIAGRAM
1.3 V
3.0 V
GND
3.0 V GND
1.3 V
CLOCK
Q
RESET
t
PHL
Figure 1.
1.3 V
DATA
CLOCK
3.0 V
3.0 V
GND
Figure 2.
VALID
GND
t
su
t
h
1/f
max
CLOCK
Q
t
r
t
f
V
CC
GND
2.7 V
1.3 V
0.3 V
90%
1.3 V
10%
t
PLH
t
PHL
t
TLH
t
THL
t
w
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE UNDER
TEST
OUTPUT
Figure 3. Figure 4. Test Circuit
C
Q
D
R
C
Q
D
R
C
Q
D
R
C
Q
D
R
C
Q
D
R
t
w
t
rec
1.3 V
1.3 V
Page 5
MC74HCT174A
High–Speed CMOS Logic Data DL129 — Rev 6
5 MOTOROLA
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
A B C D F G H J K L M S
18.80
6.35
3.69
0.39
1.02
0.21
2.80
7.50 0
°
0.51
19.55
6.85
4.44
0.53
1.77
0.38
3.30
7.74 10
°
1.01
0.740
0.250
0.145
0.015
0.040
0.008
0.110
0.295 0
°
0.020
0.770
0.270
0.175
0.021
0.070
0.015
0.130
0.305 10
°
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
2.54 BSC
1.27 BSC
0.100 BSC
0.050 BSC
–A
B
1 8
916
F
H
G
D
16 PL
S
C
–T
SEATING PLANE
K
J
M
L
T A0.25 (0.010)
M M
0.25 (0.010) T B A
M
S S
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A B C D F G J K M P R
9.80
3.80
1.35
0.35
0.40
0.19
0.10 0
°
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25 7
°
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004 0
°
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009 7
°
0.244
0.019
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
1
8
916
–A
–B
D 16 PL
K
C
G
–T
SEATING
PLANE
R X 45°
M
J
F
P 8 PL
0.25 (0.010) B
M M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
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MC74HCT174A/D
*MC74HCT174A/D*
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