Datasheet MC74HCT157AN, MC74HCT157AD Datasheet (Motorola)

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Page 1

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SEMICONDUCTOR TECHNICAL DATA

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High–Performance Silicon–Gate CMOS

The MC74HCT157A is identical in pinout to the LS157. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

This device routes 2 nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the outputs in noninverted form. A high level on the Output Enable input sets all four Y outputs to a low level.

The HCT157A is similar in function to the HC257 which has 3–state outputs.

• Output Drive Capability: 10 LSTTL Loads

• TTL NMOS Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 1.0 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 102 FETs or 25.5 Equivalent Gates

LOGIC DIAGRAM

NIBBLE

A INPUTS

NIBBLE

B INPUTS

OUTPUT ENABLE

ОООООООООО

Internal Gate Count*

ОООООООООО

Internal Gate Propagation Delay

SELECT

Design Criteria

PIN 16 = V

PIN 8 = GND

Value

ÎÎÎ

25.5

ÎÎÎ

1.5

DATA OUTPUTS

ÎÎ

Unit

ea ns



N SUFFIX

ORDERING INFORMATION

MC74HCTXXXAN MC74HCTXXXAD

PIN ASSIGNMENT

SELECT

A0 B0

Y0 A1

B1 Y1

GND

FUNCTION TABLE

Inputs

Output Outputs Enable Select Y0 – Y3

L L

X = don’t care A0 – A3, B0 – B3 = the levels of the respective Data–Word Inputs.

PLASTIC PACKAGE

SOIC PACKAGE

CASE 751B–05

1 2 3 4

16 15 14 13 125

6 7

11 10

X L H

CASE 648–08

D SUFFIX

Plastic SOIC

OUTPUT ENABLE

A3 B3

Y3 A2

B2 Y2

L A0–A3 B0–B3

Internal Gate Power Dissipation Speed Power Product

*Equivalent to a two input NAND gate.

2/97

 Motorola, Inc. 1997

0.005

0.0075

µW

REV 7

Page 2

MC74HCT157A

Current

GND, Other Inputs

MAXIMUM RATINGS*

Symbol

I I

DC Supply Voltage (Referenced to GND)

DC Input Voltage (Referenced to GND)

DC Output Voltage (Referenced to GND)

out

DC Input Current, per Pin

DC Output Current, per Pin

out

DC Supply Current, VCC and GND Pins

Power Dissipation in Still Air Plastic DIP†

ОООООООООООО

Storage Temperature

stg

Lead Temperature, 1 mm from Case for 10 Seconds

ОООООООООООО

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

ÎÎ

Vin, V

ÎÎ

tr, t

out

ОООООООООООО

DC Supply Voltage (Referenced to GND)

ОООООООООООО

DC Input Voltage, Output Voltage

ОООООООООООО

(Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)

Parameter

SOIC Package†

(Plastic DIP or SOIC Package)

Parameter

Value

– 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5

± 20 ± 25 ± 50

750 500

ÎÎÎÎ

– 65 to + 150

260

ÎÎÎÎ

Min

Max

– 55

4.5

5.5

+ 125

500

Unit

V V

V mA mA mA

Unit

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

should be constrained to the

out

range GND v (Vin or V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

) v VCC.

out

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

ÎÎ

ÎÎÎОООООООÎООООООО

ÎÎ

ÎÎÎОООООООÎООООООО

ÎÎ

∆I

Minimum High–Level Input

ООООООО

Voltage Maximum Low–Level Input

Voltage

ООООООО

Minimum High–Level Output Voltage

ООООООО

Maximum Low–Level Output Voltage

ООООООО

Maximum Input Leakage Current

ООООООО

Maximum Quiescent Supply

ООООООО

Current (per Package)

Additional Quiescent Supply

Parameter

Test Conditions

= 0.1 V or VCC – 0.1 V

out

ООООООО

| v 20 µA

out

0.1 V or VCC – 0.1 V

out

| v 20 mA

ООООООО

out

Vin = VIH or V |I

| v 20 mA

out

ООООООО

Vin = VIH or V |I

| v 4.0 mA

out

Vin = VIH or V |I

| v 20 µA

ООООООО

out

Vin = VIH or V |I

| v 4.0 mA

out

Vin = VCC or GND

ООООООО

Vin = VCC or GND

ООООООО

= 0 µA

out

Vin = 2.4 V, Any One Input

out

= 0 µA

4.5

ÎÎ

5.5

4.5

5.5

ÎÎ

4.5

5.5

ÎÎ

4.5

5.5

ÎÎ

4.5

ÎÎ

5.5

ÎÎ

5.5

ÎÎ

5.5

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

– 55 to

25_C

2.0

ÎÎ

2.0

0.8

ÎÎ

4 4

5.4

ÎÎ

3.98

0.1

ÎÎ

0.26

ÎÎ

± 0.1

ÎÎ

4.0

ÎÎ

≥ – 55_C

2.9

85_Cv 125_C

2.0

ÎÎ

2.0

0.8

ÎÎ

4.4

5.4

ÎÎ

3.84

0.1

ÎÎ

0.33

ÎÎ

± 1.0

ÎÎ

25_C to 125_C

2.4

2.0

ÎÎ

2.0

0.8

ÎÎ

4.4

5.4

ÎÎ

3.7

0.1

ÎÎ

0.4

ÎÎ

± 1.0

ÎÎ

160

ÎÎ

Unit

µA

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

Page 3

MC74HCT157A

AC ELECTRICAL CHARACTERISTICS (V

= 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

– 55 to

ÎÎ

Symbol

PLH

PHL

ÎÎ

PLH

ÎÎ

PHL

PLH

ÎÎ

PHL

TLH

THL

ÎÎ

tr, t

ООООООООООООООООО

Maximum Propagation Delay, Input A or B to Output Y

(Figures 1 and 4)

ООООООООООООООООО

Maximum Propagation Delay, Select to Output Y

ООООООООООООООООО

(Figures 2 and 4)

Maximum Propagation Delay, Output Enable to Output Y

ООООООООООООООООО

(Figures 3 and 4)

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

ООООООООООООООООО

Parameter

Maximum Input Rise and Fall Time

25_C

ÎÎ

500

ÎÎ

85_C

ÎÎ

500

ÎÎ

125_C

ÎÎ

500

Unit

NOTE:For propagation delays with loads other than 50 pF , and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

*Used to determine the no–load dynamic power consumption: PD = CPD V

Motorola High–Speed CMOS Data Book (DL129/D).

Power Dissipation Capacitance (Per Transceiver Channel)*

f + ICC VCC. For load considerations, see Chapter 2 of the

PIN DESCRIPTIONS

INPUTS A0, A1, A2, A3 (Pins 2, 5, 11, 14)

Nibble A inputs. The data present on these pins is transferred to the outputs when the Select input is at a low level and the Output Enable input is at a low level. The data is presented to the outputs in noninverted form.

B0, B1, B2, B3 (Pins 3, 6, 10, 13)

Nibble B inputs. The data present on these pins is transferred to the outputs when the Select input is at a high level and the Output Enable input is at a low level. The data is presented to the outputs in noninverted form.

OUTPUTS Y0, Y1, Y2, Y3 (Pins 4, 7, 9, 12)

Data outputs. The selected input Nibble is presented at

these outputs when the Output Enable input is at a low level. The data is presented to the outputs in noninverted form. For the Output Enable input at a high level, the outputs are at a low level.

CONTROL INPUTS

Select (Pin 1)

Nibble select. This input determines the data word to be transferred to the outputs. A low level on this input selects the A inputs and a high level selects the B inputs.

Output Enable (Pin 15)

Output Enable input. A low level on this input allows the selected input data to be presented at the outputs. A high level on this input sets all outputs to a low level.

High–Speed CMOS Logic Data DL129 — Rev 6

3 MOTOROLA

Page 4

MC74HCT157A

NIBBLE

INPUTS

OUTPUT ENABLE

SELECT

EXPANDED LOGIC DIAGRAM

DATA OUTPUTS

INPUT A OR B

PLH

OUTPUT Y

OUTPUT ENABLE

OUTPUT Y

PHL

TLH

THL

1.3 V

0.3 V

90%

1.3 V

10%

2.7 V

1.3 V

0.3 V

SWITCHING WAVEFORMS

PHL

THL

3 V

SELECT

GND

OUTPUT Y

Figure 1. Figure 2.

90%

1.3 V 10%

GND

PLH

TLH

2.7 V

1.3 V

10%

TLH

DEVICE UNDER

TEST

0.3 V

90%

PLH

*Includes all probe and jig capacitance

TEST POINT

OUTPUT

CL*

PHL

3 V

GND

THL

Figure 3.

MOTOROLA High–Speed CMOS Logic Data

Figure 4. T est Circuit

DL129 — Rev 6

Page 5

–A

–

916

–T

–A

16 PL

–

M M

916

–B

–

–T

SEATING

–

PLANE

D 16 PL

0.25 (0.010) T B A

OUTLINE DIMENSIONS

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

SEATING PLANE

–

TA0.25 (0.010)

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

P 8 PL

0.25 (0.010) B

S S

M M

R X 45°

MC74HCT157A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

INCHES MILLIMETERS

MIN MINMAX MAX

DIM

0.740

0.250

0.145

0.015

0.040

H J

0.008

0.110

0.295

0.020

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM

A B C D F G J K M P R

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50

0.51

10.00

4.00

1.75

0.49

1.25

0.25

0.25 7

6.20

0.50

19.55

6.85

4.44

0.53

1.77

2.54 BSC

1.27 BSC

0.38

3.30

7.74 10

1.01

0.386

0.150

0.054

0.014

0.016

0.008

0.004 0

0.229

0.010

0.770

0.270

0.175

0.021

0.070

0.100 BSC

0.050 BSC

0.015

0.130

0.305 10

0.040

MILLIMETERS INCHES

MIN MINMAX MAX

9.80

3.80

1.35

0.35

0.40

1.27 BSC 0.050 BSC

0.19

0.10 0

5.80

0.25

0.393

0.157

0.068

0.019

0.049

0.009

0.009 7

0.244

0.019

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High–Speed CMOS Logic Data

◊

5 MOTOROLA

MC74HCT157A/D

DL129 — Rev 6

Datasheet MC74HCT157AN, MC74HCT157AD Datasheet (Motorola)

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