Datasheet MC74HC74ADG Specification

MC74HC74A

Dual D Flip-Flop with Set and Reset

High−Performance Silicon−Gate CMOS

The MC74HC74A is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of two D flip−flops with individual Set, Reset, and Clock inputs. Information at a D−input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q

outputs are available from each flip−flop. The Set

and Reset inputs are asynchronous.

Features

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 mA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the JEDEC Standard No. 7.0 A Requirements

• Chip Complexity: 128 FETs or 32 Equivalent Gates

• These Devices are Pb−Free, Halogen Free and are RoHS Compliant

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable

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14

PDIP−14

14

1

14

1

14

1

14

1

(Note: Microdot may be in either location)

N SUFFIX

CASE 646

1

14

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14 DT SUFFIX

CASE 948G

SOEIAJ−14

F SUFFIX

CASE 965

A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb−Free Package

MARKING

DIAGRAMS

MC74HC74AN

AWLYYWWG

HC74AG

AWLYWW

1

14

ALYWG

1

14

74HC74A

ALYWG

1

HC

74A

G

July, 2013 − Rev. 13

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.

1 Publication Order Number:

MC74HC74A/D

MC74HC74A

RESET 1

DATA 1

CLOCK 1

SET 1

1

2

3

4

Q1

6

Q1

7

GND

FUNCTION TABLE

Inputs Outputs

Set Reset Clock Data Q Q

LH XX HL

HL XX LH

L L X X H* H* HH H HL HH L L H H H L X No Change H H H X No Change H H X No Change

*Both outputs will remain high as long as Set and Reset are low, but the output

states are unpredictable if Set and Reset go high simultaneously.

14

13

12

11

105

9

8

V

CC

RESET 2

DATA 2

CLOCK 2

SET 2

Q2

RESET 1

DATA 1

CLOCK 1

SET 1

RESET 2

DATA 2

CLOCK 2

SET 2

LOGIC DIAGRAMPIN ASSIGNMENT

1

2

3

4

13

12

11

10

5

6

9

8

PIN 14 = VCC PIN 7 = GND

Q1

Q2

MAXIMUM RATINGS

Symbol

V

DC Supply Voltage (Referenced to GND)

CC

V

DC Input Voltage (Referenced to GND)

in

DC Output Voltage (Referenced to GND)

out

I

DC Input Current, per Pin

in

I

DC Output Current, per Pin

out

I

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air, Plastic DIP†

D

T

Storage Temperature

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

Parameter

SOIC Package†

TSSOP Package†

(Plastic DIP, SOIC or TSSOP Package)

Value

– 0.5 to + 7.0

– 0.5 to VCC + 0.5

± 20

± 25

± 50

750 500 450

– 65 to + 150

260 300

Unit

V

mA

mW

_C

RECOMMENDED OPERATING CONDITIONS

Symbol

V

Vin, V

DC Supply Voltage (Referenced to GND)

CC

DC Input Voltage, Output Voltage (Referenced to GND)

out

T

Operating Temperature, All Package Types

A

tr, tfInput Rise and Fall Time VCC = 2.0 V

(Figures 1, 2, 3) V

Parameter

V V

= 3.0 V

CC

= 4.5 V

CC

= 6.0 V

CC

Min

2.0

0

– 55

0 0 0 0

Max

6.0

V

CC

+ 125

1000

600 500 400

Unit

V

_C

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V

should be constrained to the

V

out

range GND v (V

in

or V

) v VCC.

out

in

and

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V

CC

Unused outputs must be left open.

).

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2

MC74HC74A

ÎÎÎ

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Symbol

V

Minimum High−Level Input

IH

Voltage

V

Maximum Low−Level Input

IL

Voltage

V

Minimum High−Level Output

OH

Voltage

V

Maximum Low−Level Output

OL

Voltage

I

Maximum Input Leakage Current

in

I

Maximum Quiescent Supply

CC

Current (per Package)

AC ELECTRICAL CHARACTERISTICS (C

Symbol

f

t

C

* Used to determine the no−load dynamic power consumption: PD = CPD V

Maximum Clock Frequency (50% Duty Cycle)

max

(Figures 1 and 4)

,

Maximum Propagation Delay, Clock to Q or Q

PLH

PHL

PLH

PHL

TLH

THL

C

PD

in

(Figures 1 and 4)

,

Maximum Propagation Delay, Set or Reset to Q or Q

(Figures 2 and 4)

,

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

Maximum Input Capacitance

Power Dissipation Capacitance (Per Flip−Flop)*

Parameter

V

out

|I

out

V

out

|I

out

Vin = VIH or V |I

out

Vin = VIH or VIL|I

Vin = VIH or V |I

out

Vin = VIH or VIL|I

Vin = VCC or GND

Vin = VCC or GND I

out

= 50 pF, Input tr = t

L

Parameter

Test Conditions

= 0.1 V or VCC – 0.1 V

| v 20 mA

= 0.1 V or VCC – 0.1 V

| v 20 mA

IL

| v 2.4 mA

out

| v 4.0 mA

|I

out

|I

| v 5.2 mA

out

IL

| v 20 mA

| v 2.4 mA

out

| v 4.0 mA

|I

out

|I

| v 5.2 mA

out

= 0 mA

= 6.0 ns)

f

2

f + ICC VCC.

CC

V

CC

V

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

4.5

6.0

3.0

4.5

6.0

2.0

4.5

6.0

3.0

4.5

6.0

CC

V

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

—

Guaranteed Limit

– 55 to

25_C

1.5

2.1

3.15

4.2

0.5

0.9

1.35

1.8

1.9

4.4

5.9

2.48

3.98

5.48

0.1

0.26

± 0.1

2.0

v 85_C

1.5

2.1

3.15

4.2

0.5

0.9

1.35

1.8

1.9

4.4

5.9

2.34

3.84

5.34

0.1

0.33

± 1.0

20

v 125_C

3.15

1.35

± 1.0

Guaranteed Limit

– 55 to

25_C

6.0 15 30 35

100

75 20 17

105

80 21 18

75 30 15 13

10

v 85_C

4.8 10 24 28

125

90 25 21

130

95 26 22

95 40 19 16

10

v 125_C

Typical @ 25°C, VCC = 5.0 V

32

1.5

2.1

4.2

0.5

0.9

1.8

1.9

4.4

5.9

2.2

3.7

5.2

0.1

0.4

80

4.0

8.0 20 24

150 120

30 26

160 130

32 27

110

55 22 19

10

Unit

V

mA

Unit

MHz

ns

pF

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3

MC74HC74A

ÎÎÎ

TIMING REQUIREMENTS (Input t

Symbol

t

Minimum Setup Time, Data to Clock

t

tr, t

t

rec

t

su

h

w

(Figure 3)

Minimum Hold Time, Clock to Data

(Figure 3)

Minimum Recovery Time, Set or Reset Inactive to Clock

(Figure 2)

Minimum Pulse Width, Clock

(Figure 1)

Minimum Pulse Width, Set or Reset

(Figure 2)

Maximum Input Rise and Fall Times

f

(Figures 1, 2, 3)

= tf = 6.0 ns)

r

Parameter

V

CC

V

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

Guaranteed Limit

– 55 to

25_C

80 35 16 14

3.0

8.0

60 25 12 10

1000

800 500 400

v 85_C

100

45 20 17

3.0

8.0

75 30 15 13

1000

800 500 400

v 125_C

120

55 24 20

3.0

8.0

90 40 18 15

1000

800 500 400

Unit

ns

ORDERING INFORMATION

Device Package Shipping

MC74HC74ANG PDIP−14

(Pb−Free)

MC74HC74ADG

NLV74HC74ADG*

MC74HC74ADR2G

NLV74HC74ADR2G*

MC74HC74ADTR2G

NLV74HC74ADTR2G*

SOIC−14

(Pb−Free)

SOIC−14

(Pb−Free)

TSSOP−14

(Pb−Free)

MC74HC74AFG SOEIAJ−14

(Pb−Free)

MC74HC74AFELG SOEIAJ−14

(Pb−Free)

25 Units / Rail

55 Units / Rail

2500 / Tape & Reel

50 Units / Rail

2000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

†

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4

CLOCK

Q or Q

10%

90%

50%

10%

90%

MC74HC74A

SWITCHING WAVEFORMS

t

50%

w

V

CC

GND

t

PHL

t

PLH

t

rec

V

CC

50%

GND

t

f

t

w

t

PLH

t

r

1/f

max

t

PHL

V

CC

GND

SET OR

RESET

Q

OR Q

Q OR Q

t

TLH

t

THL

CLOCK

SET

DATA

4, 10

2, 12

50%

t

su

Figure 1.

VALID

t

h

50%

Figure 3.

V

CC

GND

V

CC

GND

Figure 2.

TEST POINT

OUTPUT

DEVICE UNDER

TEST

CL*

*Includes all probe and jig capacitance

Figure 4.

5, 9

Q

RESET

1, 13

3, 11

CLOCK

Figure 5. EXPANDED LOGIC DIAGRAM

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5

6, 8

Q

A1

14 8

17

NOTE 8

b2

TOP VIEW

D1

D

e

14X

SIDE VIEW

A

E1

B

A2

A

NOTE 3

L

C

b

M

0.010 CA

MC74HC74A

PACKAGE DIMENSIONS

PDIP−14

CASE 646−06

ISSUE R

H

WITH LEADS CONSTRAINED

SEATING PLANE

MBM

E

c

END VIEW

NOTE 5

M

eB

END VIEW

NOTE 6

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.

4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH.

5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C.

6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED.

7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY.

8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS).

INCHES

DIM MIN MAX

A −−−− 0.210 A1 0.015 −−−− A2 0.115 0.195 2.92 4.95

b 0.014 0.022 b2

0.060 TYP 1.52 TYP

C 0.008 0.014

D 0.735 0.775 D1 0.005 −−−−

E 0.300 0.325

E1 0.240 0.280 6.10 7.11

e 0.100 BSC

eB −−−− 0.430 −−− 10.92

L 0.115 0.150 2.92 3.81

M −−−− 10

MILLIMETERS

MIN MAX

−−− 5.33

0.38 −−−

0.35 0.56

0.20 0.36

18.67 19.69

0.13 −−−

7.62 8.26

2.54 BSC

−−− 10

°°

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6

MC74HC74A

PACKAGE DIMENSIONS

SOIC−14 NB

CASE 751A−03

ISSUE K

14

H

M

0.25 B

D

A B

8

A3

E

L

71

b

M

13X

M

0.25 B

S

A

C

S

A

e

A1

C

SEATING PLANE

DETAIL A

h

X 45

_

M

DETAIL A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

DIM MIN MAX MIN MAX

A 1.35 1.75 0.054 0.068 A1 0.10 0.25 0.004 0.010 A3 0.19 0.25 0.008 0.010

b 0.35 0.49 0.014 0.019

D 8.55 8.75 0.337 0.344

E 3.80 4.00 0.150 0.157

e 1.27 BSC 0.050 BSC H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 L 0.40 1.25 0.016 0.049 M 0 7 0 7

__ __

INCHESMILLIMETERS

SOLDERING FOOTPRINT*

6.50

1

14X

1.18

1.27

PITCH

14X

0.58

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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7

MC74HC74A

PACKAGE DIMENSIONS

TSSOP−14 DT SUFFIX

CASE 948G−01

ISSUE B

0.10 (0.004)

−T−

SEATING PLANE

14X REFK

S

U

T

S

N

0.25 (0.010)

U0.15 (0.006) T

S

2X L/2

0.10 (0.004) V

14

M

8

M

L

PIN 1 IDENT.

1

S

U0.15 (0.006) T

A

−V−

B

N

−U− F

7

DETAIL E

K

K1

J

J1

SECTION N−N

C

D

G

H

DETAIL E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024

−W−

J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC M 0 8 0 8

____

INCHESMILLIMETERS

SOLDERING FOOTPRINT

14X

0.36

1

14X

1.26

7.06

0.65

PITCH

DIMENSIONS: MILLIMETERS

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8

14 8

1

Z

D

e

b

0.13 (0.005)

M

E

7

A

0.10 (0.004)

H

A

1

MC74HC74A

PACKAGE DIMENSIONS

SOEIAJ−14

F SUFFIX

CASE 965−01

ISSUE B

L

E

VIEW P

_

M

L

DETAIL P

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI

Q

1

c

Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

--- 2.05 --- 0.081

A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.10 0.20 0.004 0.008

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L

1.10 1.50 0.043 0.059

E

0

M

_

Q

0.70 0.90 0.028 0.035

1

--- 1.42 --- 0.056

Z

INCHES

10

_

10

0

_

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MC74HC74A/D

9

Datasheet MC74HC74ADG Specification

Specifications and Main Features

Frequently Asked Questions

User Manual