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MC74HC595AD
Datasheet (MOTOROLA)
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Datasheet MC74HC595ADT, MC74HC595AD Datasheet (Motorola)

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Page 1

SEMICONDUCTOR TECHNICAL DATA
1
REV 7
Motorola, Inc. 1997
3/97
$ "!%$" " "%$!%$ $ #$" &$ $ $$ %$!%$#
High–Performance Silicon–Gate CMOS
The MC54/74HC595A is identical in pinout to the LS595. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC595A consists of an 8–bit shift register and an 8–bit D–type latch with three–state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8–bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register.
The HC595A directly interfaces with the Motorola SPI serial data port on CMOS MPUs and MCUs.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 328 FETs or 82 Equivalent Gates
• Improvements over HC595
— Improved Propagation Delays — 50% Lower Quiescent Power — Improved Input Noise and Latchup Immunity
LOGIC DIAGRAM
SERIAL
DATA
INPUT
14
11
10
12 13
SHIFT
CLOCK RESET
LATCH
CLOCK
OUTPUT
ENABLE
SHIFT
REGISTER
LATCH
15
1 2 3
4 5 6 7
9
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
SQ
H
A
VCC = PIN 16 GND = PIN 8
PARALLEL
DATA
OUTPUTS
SERIAL
DATA
OUTPUT

PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
LATCH CLOCK
OUTPUT ENABLE
A
Q
A
V
CC
SQ
H
RESET
SHIFT CLOCK
Q
E
Q
D
Q
C
Q
B
GND
Q
H
Q
G
Q
F
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD MC74HCXXXADT
Ceramic Plastic SOIC TSSOP
1
16
1
16
1
16
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
Page 2
MC54/74HC595A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 35
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
Î
Î
P
D
ОООООООООООО
Î
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
TSSOP Package†
ÎÎÎÎ
Î
750 500 450
Î
Î
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
Î
Î
Î
Î
T
L
ОООООООООООО
Î
ОООООООООООО
Î
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)
ÎÎÎÎ
Î
ÎÎÎÎ
Î
260 300
Î
Î
Î
Î
_
C
*Maximum Ratings are those values beyond which damage to the device may occur .
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
ÎÎ
Î
ÎÎ
Î
tr, t
f
ОООООООООООО
Î
ОООООООООООО
Î
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
Î
Î
Î
Î
0 0 0
Î
Î
Î
Î
1000
500 400
Î
Î
Î
Î
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
ÎÎ
Symbol
ООООООО
Parameter
ООООООО
Test Conditions
ÎÎ
V
CC
V
ÎÎ
– 55 to
25_C
ÎÎ
v
85_C
ÎÎ
v
125_C
Î
Unit
ÎÎ
Î
ÎÎ
Î
V
IH
ООООООО
Î
ООООООО
Î
Minimum High–Level Input Voltage
ООООООО
Î
ООООООО
Î
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
1.5
2.1
3.15
4.2
ÎÎ
Î
ÎÎ
Î
1.5
2.1
3.15
4.2
ÎÎ
Î
ÎÎ
Î
1.5
2.1
3.15
4.2
Î
Î
Î
Î
V
ÎÎ
Î
ÎÎ
Î
V
IL
ООООООО
Î
ООООООО
Î
Maximum Low–Level Input Voltage
ООООООО
Î
ООООООО
Î
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
0.5
0.9
1.35
1.8
ÎÎ
Î
ÎÎ
Î
0.5
0.9
1.35
1.8
ÎÎ
Î
ÎÎ
Î
0.5
0.9
1.35
1.8
Î
Î
Î
Î
V
ÎÎ
Î
ÎÎ
Î
V
OH
ООООООО
Î
ООООООО
Î
Minimum High–Level Output Voltage, QA – Q
H
ООООООО
Î
ООООООО
Î
Vin = VIH or V
IL
|I
out
| v 20 µA
ÎÎ
Î
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
ÎÎ
1.9
4.4
5.9
ÎÎ
Î
ÎÎ
Î
1.9
4.4
5.9
ÎÎ
Î
ÎÎ
Î
1.9
4.4
5.9
Î
Î
Î
Î
V
ÎÎÎОООООООÎООООООО
Î
Vin = VIH or VIL|I
out
| v 2.4 mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
ÎÎ
Î
3.0
4.5
6.0
ÎÎ
2.48
3.98
5.48
ÎÎ
Î
2.34
3.84
5.34
ÎÎ
Î
2.2
3.7
5.2
Î
Î
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance cir­cuit. For proper operation, Vin and V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Page 3
MC54/74HC595A
High–Speed CMOS Logic Data DL129 — Rev 6
3 MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Unit
Guaranteed Limit
V
CC
V
Test Conditions
Parameter
Symbol
Unit
v
125_C
v
85_C
– 55 to
25_C
V
CC
V
Test Conditions
Parameter
Symbol
ÎÎ
Î
V
OL
ООООООО
Î
Maximum Low–Level Output Voltage, QA – Q
H
ООООООО
Î
Vin = VIH or V
IL
|I
out
| v 20 µA
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
0.1
0.1
0.1
ÎÎ
Î
0.1
0.1
0.1
ÎÎ
Î
0.1
0.1
0.1
Î
Î
V
ÎÎÎОООООООÎООООООО
Î
Vin = VIH or VIL|I
out
| v 2.4 mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
ÎÎ
Î
3.0
4.5
6.0
ÎÎ
0.26
0.26
0.26
ÎÎ
Î
0.33
0.33
0.33
ÎÎ
Î
0.4
0.4
0.4
Î
Î
ÎÎ
Î
ÎÎ
V
OH
ООООООО
Î
ООООООО
Minimum High–Level Output Voltage, SQ
H
ООООООО
Î
ООООООО
Vin = VIH or V
IL
II
out
I v 20 µA
ÎÎ
Î
ÎÎ
2.0
4.5
6.0
ÎÎ
ÎÎ
1.9
4.4
5.9
ÎÎ
Î
ÎÎ
1.9
4.4
5.9
ÎÎ
Î
ÎÎ
1.9
4.4
5.9
Î
Î
Î
V
ÎÎ
Î
ÎÎ
Î
ООООООО
Î
ООООООО
Î
ООООООО
Î
ООООООО
Î
Vin = VIH or VIL|I
out
| v 2.4 mA
II
outI v
4.0 mA
II
out
Iv 5.2 mA
ÎÎ
Î
ÎÎ
Î
3.0
4.5
6.0
ÎÎ
ÎÎ
2.98
3.98
5.48
ÎÎ
Î
ÎÎ
Î
2.34
3.84
5.34
ÎÎ
Î
ÎÎ
Î
2.2
3.7
5.2
Î
Î
Î
Î
ÎÎ
Î
V
OL
ООООООО
Î
Maximum Low–Level Output Voltage, SQ
H
ООООООО
Î
Vin = VIH or V
IL
II
out
I v 20 µA
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
0.1
0.1
0.1
ÎÎ
Î
0.1
0.1
0.1
ÎÎ
Î
0.1
0.1
0.1
Î
Î
V
ÎÎÎОООООООÎООООООО
Î
Vin = VIH or VIL|I
out
| v 2.4 mA
II
outI v
4.0 mA
II
out
Iv 5.2 mA
ÎÎ
Î
3.0
4.5
6.0
ÎÎ
0.26
0.26
0.26
ÎÎ
Î
0.33
0.33
0.33
ÎÎ
Î
0.4
0.4
0.4
Î
Î
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
ÎÎ
Î
ÎÎ
I
OZ
ООООООО
Î
ООООООО
Maximum Three–State Leakage Current, QA – Q
H
ООООООО
Î
ООООООО
Output in High–Impedance State Vin = VIL or V
IH
V
out
= VCC or GND
ÎÎ
Î
ÎÎ
6.0
ÎÎ
ÎÎ
± 0.5
ÎÎ
Î
ÎÎ
± 5.0
ÎÎ
Î
ÎÎ
± 10
Î
Î
Î
µA
ÎÎ
Î
I
CC
ООООООО
Î
Maximum Quiescent Supply Current (per Package)
ООООООО
Î
Vin = VCC or GND l
out
= 0 µA
ÎÎ
Î
6.0
ÎÎ
4.0
ÎÎ
Î
40
ÎÎ
Î
160
Î
Î
µA
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
ÎÎ
Î
Symbol
ООООООООООООООО
Î
Parameter
ÎÎ
Î
V
CC
V
ÎÎ
– 55 to
25_C
ÎÎ
Î
v
85_C
ÎÎ
Î
v
125_C
Î
Î
Unit
ÎÎ
Î
ÎÎ
f
max
ООООООООООООООО
Î
ООООООООООООООО
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
ÎÎ
Î
ÎÎ
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
6.0 15 30 35
ÎÎ
Î
ÎÎ
4.8 10 24 28
ÎÎ
Î
ÎÎ
4.0
8.0 20 24
Î
Î
Î
MHz
ÎÎ
Î
ÎÎ
Î
t
PLH
,
t
PHL
ООООООООООООООО
Î
ООООООООООООООО
Î
Maximum Propagation Delay, Shift Clock to SQ
H
(Figures 1 and 7)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
140 100
28 24
ÎÎ
Î
ÎÎ
Î
175 125
35 30
ÎÎ
Î
ÎÎ
Î
210 150
42 36
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
PHL
ООООООООООООООО
Î
ООООООООООООООО
Î
Maximum Propagation Delay, Reset to SQ
H
(Figures 2 and 7)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
145 100
29 25
ÎÎ
Î
ÎÎ
Î
180 125
36 31
ÎÎ
Î
ÎÎ
Î
220 150
44 38
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
PLH
,
t
PHL
ООООООООООООООО
Î
ООООООООООООООО
Î
Maximum Propagation Delay, Latch Clock to QA – Q
H
(Figures 3 and 7)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
140 100
28 24
ÎÎ
Î
ÎÎ
Î
175 125
35 30
ÎÎ
Î
ÎÎ
Î
210 150
42 36
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
t
PLZ
,
t
PHZ
ООООООООООООООО
Î
ООООООООООООООО
Maximum Propagation Delay, Output Enable to QA – Q
H
(Figures 4 and 8)
ÎÎ
Î
ÎÎ
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
150 100
30 26
ÎÎ
Î
ÎÎ
190 125
38 33
ÎÎ
Î
ÎÎ
225 150
45 38
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
PZL
,
t
PZH
ООООООООООООООО
Î
ООООООООООООООО
Î
Maximum Propagation Delay, Output Enable to QA – Q
H
(Figures 4 and 8)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
135
90 27 23
ÎÎ
Î
ÎÎ
Î
170 110
34 29
ÎÎ
Î
ÎÎ
Î
205 130
41 35
Î
Î
Î
Î
ns
Page 4
MC54/74HC595A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
Unit
Guaranteed Limit
V
CC
V
Parameter
Symbol
Unit
v
125_C
v
85_C
– 55 to
25_C
V
CC
V
Parameter
Symbol
ÎÎ
Î
t
TLH
,
t
THL
ООООООООООООООО
Î
Maximum Output Transition Time, QA – Q
H
(Figures 3 and 7)
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
60 23 12 10
ÎÎ
Î
75 27 15 13
ÎÎ
Î
90 31 18 15
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
TLH
,
t
THL
ООООООООООООООО
Î
ООООООООООООООО
Î
Maximum Output Transition Time, SQ
H
(Figures 1 and 7)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
75 27 15 13
ÎÎ
Î
ÎÎ
Î
95 32 19 16
ÎÎ
Î
ÎÎ
Î
110
36 22 19
Î
Î
Î
Î
ns
C
in
Maximum Input Capacitance
—
10
10
10
pF
ÎÎ
Î
C
out
ООООООООООООООО
Î
Maximum Three–State Output Capacitance (Output in High–Impedance State), QA – Q
H
ÎÎ
Î
—
ÎÎ15ÎÎ
Î
15
ÎÎ
Î
15
Î
Î
pF
NOTE:For propagation delays with loads other than 50 pF , and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
300
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (Input t
r
= tf = 6.0 ns)
Guaranteed Limit
ÎÎ
Î
Symbol
ООООООООООООООО
Î
Parameter
ÎÎ
Î
V
CC
V
ÎÎ
25_C to
– 55_C
ÎÎ
Î
v
85_C
ÎÎ
Î
v
125_C
Î
Î
Unit
ÎÎ
Î
ÎÎ
Î
t
su
ООООООООООООООО
Î
ООООООООООООООО
Î
Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
50 40 10
9.0
ÎÎ
Î
ÎÎ
Î
65 50 13 11
ÎÎ
Î
ÎÎ
Î
75 60 15 13
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
su
ООООООООООООООО
Î
ООООООООООООООО
Î
Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
75 60 15 13
ÎÎ
Î
ÎÎ
Î
95 70 19 16
ÎÎ
Î
ÎÎ
Î
110
80 22 19
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
h
ООООООООООООООО
Î
ООООООООООООООО
Î
Minimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
5.0
5.0
5.0
5.0
ÎÎ
Î
ÎÎ
Î
5.0
5.0
5.0
5.0
ÎÎ
Î
ÎÎ
Î
5.0
5.0
5.0
5.0
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
rec
ООООООООООООООО
Î
ООООООООООООООО
Î
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
50 40 10
9.0
ÎÎ
Î
ÎÎ
Î
65 50 13 11
ÎÎ
Î
ÎÎ
Î
75 60 15 13
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
w
ООООООООООООООО
Î
ООООООООООООООО
Î
Minimum Pulse Width, Reset
(Figure 2)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
60 45 12 10
ÎÎ
Î
ÎÎ
Î
75 60 15 13
ÎÎ
Î
ÎÎ
Î
90 70 18 15
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
w
ООООООООООООООО
Î
ООООООООООООООО
Î
Minimum Pulse Width, Shift Clock
(Figure 1)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
50 40 10
9.0
ÎÎ
Î
ÎÎ
Î
65 50 13 11
ÎÎ
Î
ÎÎ
Î
75 60 15 13
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
w
ООООООООООООООО
Î
ООООООООООООООО
Î
Minimum Pulse Width, Latch Clock
(Figure 6)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
50 40 10
9.0
ÎÎ
Î
ÎÎ
Î
65 50 13 11
ÎÎ
Î
ÎÎ
Î
75 60 15 13
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
tr, t
f
ООООООООООООООО
Î
ООООООООООООООО
Î
Maximum Input Rise and Fall Times
(Figure 1)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
1000
800 500 400
ÎÎ
Î
ÎÎ
Î
1000
800 500 400
ÎÎ
Î
ÎÎ
Î
1000
800 500 400
Î
Î
Î
Î
ns
Page 5
MC54/74HC595A
High–Speed CMOS Logic Data DL129 — Rev 6
5 MOTOROLA
FUNCTION TABLE
Inputs Resulting Function
Operation
Reset
Serial
Input
A
Shift
Clock
Latch Clock
Output Enable
Shift
Register
Contents
Latch
Register
Contents
Serial
Output
SQ
H
Parallel
Outputs
QA – Q
H
Reset shift register L X X L, H, ↓ L L U L U Shift data into shift
register
H D ↑ L, H, ↓ L D → SRA;
SRN → SR
N+1
U SRG → SR
H
U
Shift register remains unchanged
H X L, H, ↓ L, H, ↓ L U U U U
Transfer shift register contents to latch register
H X L, H, ↓ ↑ L U SRN → LR
N
U SR
N
Latch register remains unchanged
X X X L, H, ↓ L * U * U
Enable parallel outputs X X X X L * ** * Enabled Force outputs into high
impedance state
X X X X H * ** * Z
SR = shift register contents D = data (L, H) logic level ↑ = Low–to–High * = depends on Reset and Shift Clock inputs LR = latch register contents U = remains unchanged ↓ = High–to–Low ** = depends on Latch Clock input
PIN DESCRIPTIONS
INPUTS
A (Pin 14)
Serial Data Input. The data on this pin is shifted into the
8–bit serial shift register.
CONTROL INPUTS Shift Clock (Pin 11)
Shift Register Clock Input. A low– to–high transition on this input causes the data at the Serial Input pin to be shifted into the 8–bit shift register.
Reset (Pin 10)
Active–low, Asynchronous, Shift Register Reset Input. A low on this pin resets the shift register portion of this device only . The 8–bit latch is not affected.
Latch Clock (Pin 12)
Storage Latch Clock Input. A low–to–high transition on this
input latches the shift register data.
Output Enable (Pin 13)
Active–low Output Enable. A low on this input allows the data from the latches to be presented at the outputs. A high on this input forces the outputs (QA–QH) into the high– impedance state. The serial output is not affected by this control unit.
OUTPUTS QA – QH (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Noninverted, 3–state, latch outputs.
SQH (Pin 9)
Noninverted, Serial Data Output. This is the output of the eighth stage of the 8–bit shift register. This output does not have three–state capability.
Page 6
MC54/74HC595A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
6
SWITCHING W AVEFORMS
SERIAL
INPUT A
50%
50%
LATCH
CLOCK
V
CC
GND
VALID
t
su
t
h
Figure 5.
SHIFT
CLOCK
OUTPUT
SQ
H
t
r
t
f
V
CC
GND
90%
50%
10%
90%
50%
10%
t
PLH
t
PHL
t
TLH
t
THL
t
w
1/f
max
RESET
OUTPUT
SQ
H
SHIFT
CLOCK
t
w
50%
50%
50%
V
CC
GND
V
CC
GND
t
PHL
t
rec
t
su
50%
50%
V
CC
GND
LATCH
CLOCK
QA–Q
H
OUTPUTS
50%
t
PLHtPHL
t
TLHtTHL
90%
50%
10%
V
CC
GND
V
CC
GND
SHIFT
CLOCK
LATCH
CLOCK
Figure 3.
V
CC
GND
t
w
Figure 1. Figure 2.
Figure 4.
Figure 6.
OUTPUT Q
OUTPUT Q
50%
50%
90%
10%
t
PZL
t
PLZ
t
PZHtPHZ
V
CC
GND HIGH
IMPEDANCE V
OL
V
OH
HIGH IMPEDANCE
OUTPUT
ENABLE
50%
TEST CIRCUITS
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE UNDER
TEST
OUTPUT
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE UNDER
TEST
OUTPUT
CONNECT TO VCC WHEN TESTING t
PLZ
AND t
PZL
. CONNECT TO GND WHEN TESTING t
PHZ
AND t
PZH
.
1 k
Ω
Figure 7. Figure 8.
Page 7
MC54/74HC595A
High–Speed CMOS Logic Data DL129 — Rev 6
7 MOTOROLA
D
R
Q
SR
A
DQ
LR
A
D
Q
SR
B
DQ
LR
B
R
D
Q
SR
C
DQ
LR
C
R
D
Q
SR
D
DQ
LR
D
R
D
Q
SR
E
DQ
LR
E
R
D
Q
SR
F
DQ
LR
F
R
D
Q
SR
G
DQ
LR
G
R
D
Q
SR
H
DQ
LR
H
R
EXPANDED LOGIC DIAGRAM
OUTPUT ENABLE
LATCH
CLOCK
SERIAL
DATA
INPUT A
SHIFT
CLOCK
RESET
13
12
14
11
10
15
1
2
3
4
5
6
7
9
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
SERIAL
DATA
OUTPUT SQ
H
PARALLEL
DATA
OUTPUTS
Page 8
MC54/74HC595A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
8
TIMING DIAGRAM
SHIFT
CLOCK
SERIAL DATA
INPUT A
RESET
LATCH
CLOCK
OUTPUT
ENABLE
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
SERIAL DATA
OUTPUT SQ
H
NOTE: implies that the output is in a high–impedance
state.
Page 9
MC54/74HC595A
High–Speed CMOS Logic Data DL129 — Rev 6
9 MOTOROLA
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
19.05
6.10 —
0.39
1.40
0.21
3.18
19.93
7.49
5.08
0.50
1.65
0.38
4.31
0
°
0.51
15
°
1.01
1.27 BSC
2.54 BSC
7.62 BSC
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
0.750
0.240 —
0.015
0.055
0.008
0.125
0.785
0.295
0.200
0.020
0.065
0.015
0.170
0.050 BSC
0.100 BSC
0.300 BSC
A B C D E F G J K L
M
N
0
°
0.020
15
°
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.
18
916
–A
–
–B
–
C
K
N
G
E
F
D 16 PL
–T
–
SEATING
PLANE
M
L
J 16 PL
0.25 (0.010) T A
M
S
0.25 (0.010) T B
M
S
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
A B C D F G H
J K L M S
18.80
6.35
3.69
0.39
1.02
0.21
2.80
7.50 0
°
0.51
19.55
6.85
4.44
0.53
1.77
0.38
3.30
7.74 10
°
1.01
0.740
0.250
0.145
0.015
0.040
0.008
0.110
0.295 0
°
0.020
0.770
0.270
0.175
0.021
0.070
0.015
0.130
0.305 10
°
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
2.54 BSC
1.27 BSC
0.100 BSC
0.050 BSC
–A
–
B
18
916
F
H
G
D
16 PL
S
C
–T
–
SEATING PLANE
K
J
M
L
TA0.25 (0.010)
M M
0.25 (0.010) T B A
M
S S
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A B C D F G J K M P R
9.80
3.80
1.35
0.35
0.40
0.19
0.10 0
°
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25 7
°
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004 0
°
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009 7
°
0.244
0.019
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
1
8
916
–A
–
–B
–
D 16 PL
K
C
G
–T
–
SEATING
PLANE
R X 45°
M
J
F
P 8 PL
0.25 (0.010) B
M M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
Page 10
MC54/74HC595A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
10
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
ÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C ––– 1.20 ––– 0.047 D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC M 0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MA TERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.
____
SECTION N–N
SEATING PLANE
IDENT.
PIN 1
1
8
16
9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
DETAIL E
F
M
L
2X L/2
–U–
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V
S
T
0.10 (0.004)
–T–
–V–
–W–
0.25 (0.010)
16X REFK
N
N
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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