Datasheet MC74HC589AFL1, MC74HC589AN, MC74HC589AF, MC74HC589AFEL, MC74HC589ADT Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 1

1 Publication Order Number:

MC74HC589A/D

MC74HC589A

8-Bit Serial or
Parallel-Input/Serial-Output
Shift Register with 3-State
Output

High–Performance Silicon–Gate CMOS

The MC74HC589A device consists of an 8–bit storage latch which
feeds parallel data to an 8–bit shift register. Data can also be loaded
serially (see Function Table). The shift register output, QH, is a
three–state output, allowing this device to be used in bus–oriented
systems.

The HC589A directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 526 FETs or 131.5 Equivalent Gates

LOGIC DIAGRAM

SERIAL

DATA

INPUT

14

15
1
2
3
4
5
6
7

12

11
13
10

S

A

A
B
C
D
E

F
G
H

LATCH CLOCK

SHIFT CLOCK

SERIAL SHIFT/

PARALLEL LOAD

OUTPUT ENABLE

PARALLEL

DATA

INPUTS

DATA

LATCH

SHIFT

REGISTER

VCC = PIN 16
GND = PIN 8

9

Q

H

SERIAL

DATA

OUTPUT

SO–16

D SUFFIX

CASE 751B

http://onsemi.com

TSSOP–16
DT SUFFIX
CASE 948F

1

16

PDIP–16
N SUFFIX
CASE 648

1

16

1

16

MARKING

DIAGRAMS

1

16

MC74HC589AN

AWLYYWW

1

16

HC589A

AWLYWW

A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week

HC

589A

ALYW

1

16

Device Package Shipping

ORDERING INFORMATION

MC74HC589AN PDIP–16 2000 / Box
MC74HC589AD SOIC–16

48 / Rail
MC74HC589ADR2 SOIC–16 2500 / Reel
MC74HC589ADT TSSOP–16 96 / Rail
MC74HC589ADTR2 TSSOP–16

2500 / Reel

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

LATCH CLOCK

SERIAL SHIFT/
PARALLEL LOAD

S

A

A

V

CC

Q

H

OUTPUT ENABLE

SHIFT CLOCK

E

D

C

B

GND

H

G

F

MC74HC589A

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2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎ

Î

750
500
450

Î

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

ÎÎ

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

ÎÎÎ

Î

260

Î

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: –10 mW/_C from 65_ to 125_C

SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

ÎÎ

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

ÎÎ

+ 125

_

C

ÎÎ

Î

ÎÎ

Î

tr, t

f

ООООООООООООО

Î

ООООООООООООО

Î

Input Rise and Fall Time VCC = 2.0 V

VCC = 3.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

Î

Î

Î

Î

0
0
0

ÎÎ

ÎÎ

ÎÎ

1000

TBD

500
400

Î

Î

Î

Î

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC
V

– 55 to

25_C

ÎÎÎ

v

85_Cv 125_C

Unit

ÎÎ

Î

ÎÎ

Î

V

IH

ООООООО

Î

ООООООО

Î

Minimum High–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

ÎÎÎ

Î

Î

Î

Î

Î

Î

1.5

2.1

3.15

4.2

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

Î

Î

Î

Î

V

ÎÎ

Î

ÎÎ

Î

V

IL

ООООООО

Î

ООООООО

Î

Maximum Low–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.8

ÎÎÎ

Î

Î

Î

Î

Î

Î

0.5

0.9

1.35

1.8

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.8

Î

Î

Î

Î

V

ÎÎ

Î

V

OH

ООООООО

Î

Minimum High–Level Output
Voltage

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

1.9

4.4

5.9

ÎÎÎ

Î

Î

Î

1.9

4.4

5.9

ÎÎ

Î

1.9

4.4

5.9

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

2.48

3.98

5.48

ÎÎÎ

Î

Î

Î

2.34

3.84

5.34

ÎÎ

Î

2.20

3.70

5.20

Î

Î

ÎÎ

Î

V

OL

ООООООО

Î

Maximum Low–Level Output
Voltage

ООООООО

Î

Vin = V

IH

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

0.1

0.1

0.1

ÎÎÎ

Î

Î

Î

0.1

0.1

0.1

ÎÎ

Î

0.1

0.1

0.1

Î

Î

V

ÎÎ

Î

ÎÎ

Î

ООООООО

Î

ООООООО

Î

ООООООО

Î

ООООООО

Î

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

ÎÎ

Î

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

0.26

0.26

0.26

ÎÎÎ

Î

Î

Î

Î

Î

Î

0.33

0.33

0.33

ÎÎ

Î

ÎÎ

Î

0.40

0.40

0.40

Î

Î

Î

Î

I

in

Maximum Input Leakage
Current

Vin = VCC or GND

6.0

± 0.1

ÎÎÎ

± 1.0

± 1.0

µA

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HC589A

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3

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Unit

Guaranteed Limit

V

CC

V

Test Conditions

Parameter

Symbol

Unit

v

125_C

ÎÎÎ

v

85_C

– 55 to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

ÎÎ

Î

I

OZ

ООООООО

Î

Maximum Three–State
Leakage Current

ООООООО

Î

Output in High–Impedance State
Vin = VIL or V

IH

V

out

= VCC or GND

ÎÎ

Î

6.0

ÎÎ

Î

± 0.5

ÎÎÎ

Î

Î

Î

± 5.0

ÎÎ

Î

± 10

Î

Î

µA

ÎÎ

Î

I

CC

ООООООО

Î

Maximum Quiescent Supply
Current (per Package)

ООООООО

Î

Vin = VCC or GND
I

out

= 0 µA

ÎÎ

Î

6.0

ÎÎ

Î

4

ÎÎÎ

Î

Î

Î

40

ÎÎ

Î

160

Î

Î

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

ÎÎÎ

v

85_Cv 125_C

Unit

ÎÎÎ

Î

ÎÎÎ

Î

f

max

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Clock Frequency (50% Duty Cycle)

(Figures 2 and 8)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

6.0

TBD

30
35

ÎÎÎ

Î

Î

Î

Î

Î

Î

4.8

TBD

24
28

ÎÎ

Î

ÎÎ

Î

4.0

TBD

20
24

Î

Î

Î

Î

MHz

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Latch Clock to Q

H

(Figures 1 and 8)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

175
100

40
30

ÎÎÎ

Î

Î

Î

Î

Î

Î

225
110

50
40

ÎÎ

Î

ÎÎ

Î

275
125

60
50

Î

Î

Î

Î

ns

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

Maximum Propagation Delay, Shift Clock to Q

H

(Figures 2 and 8)

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

160

90
30
25

ÎÎÎ

Î

Î

Î

200
130

40
30

ÎÎ

Î

240
160

48
40

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Serial Shift/Parallel Load to Q

H

(Figures 4 and 8)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

160

90
30
25

ÎÎÎ

Î

Î

Î

Î

Î

Î

200
130

40
30

ÎÎ

Î

ÎÎ

Î

240
160

48
40

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PLZ

,

t

PHZ

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Output Enable to Q

H

(Figures 3 and 9)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

150

80
27
23

ÎÎÎ

Î

Î

Î

Î

Î

Î

170
100

30
25

ÎÎ

Î

ÎÎ

Î

200
130

40
30

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PZL

,

t

PZH

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Output Enable to Q

H

(Figures 3 and 9)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

150

80
27
23

ÎÎÎ

Î

Î

Î

Î

Î

Î

170
100

30
25

ÎÎ

Î

ÎÎ

Î

200
130

40
30

Î

Î

Î

Î

ns

ÎÎÎ

Î

t

TLH

,

t

THL

ОООООООООООООО

Î

Maximum Output Transition Time, Any Output

(Figures 1 and 8)

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

60

TBD

12
10

ÎÎÎ

Î

Î

Î

75

TBD

15
13

ÎÎ

Î

90

TBD

18
15

Î

Î

ns

C

in

Maximum Input Capacitance

—

10

ÎÎÎ

10

10

pF

ÎÎÎ

Î

C

out

ОООООООООООООО

Î

Maximum Three–State Output Capacitance (Output in
High–Impedance State)

ÎÎ

Î

—

ÎÎ

Î

15

ÎÎÎ

Î

Î

Î

15

ÎÎ

Î

15

Î

Î

pF

NOTES:

1. For propagation delays with loads other than 50 pF , see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Package)*

50

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

MC74HC589A

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4

TIMING REQUIREMENTS (Input t

r

= tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

ÎÎÎ

v

85_Cv 125_C

Unit

ÎÎÎ

Î

ÎÎÎ

Î

t

su

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Setup Time, A–H to Latch Clock

(Figure 5)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

100

TBD

20
17

ÎÎÎ

Î

Î

Î

Î

Î

Î

125

TBD

25
21

ÎÎ

Î

ÎÎ

Î

150

TBD

30
26

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

su

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Setup Time, Serial Data Input SA to Shift Clock

(Figure 6)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

100

TBD

20
17

ÎÎÎ

Î

Î

Î

Î

Î

Î

125

TBD

25
21

ÎÎ

Î

ÎÎ

Î

150

TBD

30
26

Î

Î

Î

Î

ns

ÎÎÎ

Î

t

su

ОООООООООООООО

Î

Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock

(Figure 7)

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

100

TBD

20
17

ÎÎÎ

Î

Î

Î

125

TBD

25
21

ÎÎ

Î

150

TBD

30
26

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

h

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Hold Time, Latch Clock to A–H

(Figure 5)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

25

TBD

5
5

ÎÎÎ

Î

Î

Î

Î

Î

Î

30

TBD

6
6

ÎÎ

Î

ÎÎ

Î

40

TBD

8
7

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

h

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Hold Time, Shift Clock to Serial Data Input S

A

(Figure 6)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

5
5
5
5

ÎÎÎ

Î

Î

Î

Î

Î

Î

5
5
5
5

ÎÎ

Î

ÎÎ

Î

5
5
5
5

Î

Î

Î

Î

ns

ÎÎÎ

Î

t

w

ОООООООООООООО

Î

Minimum Pulse Width, Shift Clock

(Figure 2)

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

75

TBD

15
13

ÎÎÎ

Î

Î

Î

95

TBD

19
16

ÎÎ

Î

110

TBD

23
19

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

w

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Pulse Width, Latch Clock

(Figure 1)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

80

TBD

16
14

ÎÎÎ

Î

Î

Î

Î

Î

Î

100

TBD

20
17

ÎÎ

Î

ÎÎ

Î

120

TBD

24
20

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

w

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Pulse Width, Serial Shift/Parallel Load

(Figure 4)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

80

TBD

16
14

ÎÎÎ

Î

Î

Î

Î

Î

Î

100

TBD

20
17

ÎÎ

Î

ÎÎ

Î

120

TBD

24
20

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

tr, t

f

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Input Rise and Fall Times

(Figure 1)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1000

TBD

500
400

ÎÎÎ

Î

Î

Î

Î

Î

Î

1000
TBD

500
400

ÎÎ

Î

ÎÎ

Î

1000
TBD

500
400

Î

Î

Î

Î

ns

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

MC74HC589A

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5

FUNCTION TABLE

Inputs Resulting Function

Operation

Output
Enable

Serial Shift/

Parallel Load

Latch
Clock

Shift

Clock

Serial

Input

S

A

Parallel

Inputs

A–H

Data

Latch

Contents

Shift

Register

Contents

Output

Q

H

Force output into high
impedance state

H X X X X X X X Z

Load parallel data into
data latch

L H L, H, X a–h a–h U U

Transfer latch contents to
shift register

L L L, H, X X X U LRN SR

N

LR

H

Contents of input latch
and shift register are
unchanged

L H L, H, L, H, X X U U U

Load parallel data into
data latch and shift
register

L L X X a–h a–h a–h h

Shift serial data into shift
register

L H X D X * SRA = D,

SRN SR

N+1

SRG SR

H

Load parallel data in data
latch and shift serial data
into shift register

L H D a–h a–h SRA = D,

SRN SR

N+1

SRG SR

H

LR = latch register contents U = remains unchanged
SR = shift register contents X = don’t care
a–h = data at parallel data inputs A–H Z = high impedance
D = data (L, H) at serial data input S

A

* = depends on Latch Clock input

MC74HC589A

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6

SWITCHING W AVEFORMS

Figure 1. (Serial Shift/Parallel Load = L) Figure 2. (Serial Shift/Parallel Load = H)

LATCH CLOCK

Q

H

t

r

t

f

V

CC

GND

90%

50%

10%

t

PLH

t

PHL

t

TLH

t

THL

t

w

SHIFT CLOCK

Q

H

V

CC

GND

50%

50%

t

PLH

t

PHL

1/f

max

90%
50%
10%

t

w

Figure 3.

Q

H

Q

H

50%

50%

90%

10%

t

PZL

t

PLZ

t

PZHtPHZ

V

CC

GND
HIGH

IMPEDANCE
V

OL

V

OH

HIGH
IMPEDANCE

OUTPUT

ENABLE

50%

SERIAL SHIFT/

PARALLEL LOAD

Q

H

50%

t

PLH

50%

V

CC

GND

t

PHL

50%

t

w

Figure 4.

A–H

50%

50%

LATCH CLOCK

V

CC

GND

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

DATA VALID

t

su

t

h

S

A

50%

50%

SHIFT CLOCK

V

CC

GND

DATA VALID

t

su

t

h

SERIAL SHIFT/

PARALLEL LOAD

50%

50%

SHIFT CLOCK

V

CC

GND

t

su

Figure 5. Figure 6.

Figure 7. Figure 8. Test Circuit

MC74HC589A

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7

TEST CIRCUIT

Figure 9.

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

CONNECT TO VCC WHEN
TESTING t

PLZ

AND t

PZL

.
CONNECT TO GND WHEN
TESTING t

PHZ

AND t

PZH

.

1 kΩ

PIN DESCRIPTIONS

DATA INPUTS
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)

Parallel data inputs. Data on these inputs are stored in the

data latch on the rising edge of the Latch Clock input.

SA (Pin 14)

Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input if Serial
Shift/Parallel Load is high. Data on this input is ignored
when Serial Shift/Parallel Load

is low.

CONTROL INPUTS
Serial Shift/Parallel Load

(Pin 13)

Shift register mode control. When a high level is applied
to this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register
accepts parallel data from the data latch.

Shift Clock (Pin 11)

Serial shift clock. A low–to–high transition on this input
shifts data on the serial data input into the shift register and

data in stage H is shifted out QH, being replaced by the data
previously stored in stage G.

Latch Clock (Pin 12)

Data latch clock. A low–to–high transition on this input

loads the parallel data on inputs A–H into the data latch.

Output Enable (Pin 10)

Active–low output enable A high level applied to this pin
forces the QH output into the high impedance state. A low
level enables the output. This control does not affect the state
of the input latch or the shift register.

OUTPUT
QH (Pin 9)

Serial data output. This pin is the output from the last stage
of the shift register. This is a 3–state output.

MC74HC589A

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8

TIMING DIAGRAM

SHIFT CLOCK

SERIAL DATA

INPUT, S

A

OUTPUT ENABLE

SERIAL SHIFT/

PARALLEL LOAD

LATCH CLOCK

A

B

C

D

E

F

G

H

Q

H

PARALLEL

DATA

INPUTS

SERIAL SHIFT SERIAL SHIFT SERIAL SHIFT

SERIAL

SHIFT

RESET LATCH

AND SHIFT REGISTER

LOAD LATCH PARALLEL LOAD

SHIFT REGISTER

LOAD LATCH PARALLEL LOAD

SHIFT REGISTER

PARALLEL LOAD, LATCH

AND SHIFT REGISTER

HIGH IMPEDANCE

H LHH HLLHL H LLL

H

L

HH

L

L

L

L

L

L

L

L

H

L

H

L

H

H

L

H

L

L

L

L

L

L

L

H

L

L

L

L

H

H

L

H

MC74HC589A

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9

PARALLEL

DATA

INPUTS

10
14

11

13

12

15

1

2

3

4

5

6

7

OUTPUT ENABLE

S

A

SHIFT CLOCK

SERIAL SHIFT/

PARALLEL LOAD

LATCH CLOCK

A

B

C

D

E

F

G

H

STAGE A

STAGE B

STAGE C*

STAGE D*

STAGE E*

STAGE F*

STAGE G*

STAGE H

V

CC

9

Q

H

DCQ

DCQ

D

CQ

S

R

D

CQ

S

R

DCQ

D

CQ

S

R

*NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above.

LOGIC DETAIL

MC74HC589A

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10

P ACKAGE DIMENSIONS

PDIP–16

N SUFFIX

CASE 648–08

ISSUE R

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

A
B
C
D

F
G
H
J
K
L
M
S

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50
0°

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74
10°

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295
0°

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305
10°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

B

18

916

F

H

G

D

16 PL

S

C

–T

–

SEATING
PLANE

K

J

M

L

TA0.25 (0.010)

M M

0.25 (0.010) T B A

M

S S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F
G
J
K
M
P
R

9.80

3.80

1.35

0.35

0.40

0.19

0.10
0°

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

0.25
7°

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004
0°

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.009
7°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

1

8

916

–A

–

–B

–

D

16 PL

K

C

G

–T

–

SEATING

PLANE

R X 45°

M

J

F

P 8 PL

0.25 (0.010) B

M M

SOIC–16

D SUFFIX

CASE 751B–05

ISSUE J

MC74HC589A

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11

P ACKAGE DIMENSIONS

TSSOP–16

DT SUFFIX

CASE 948F–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.

____

SECTION N–N

SEATING
PLANE

IDENT.

PIN 1

1

8

16

9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

DETAIL E

F

M

L

2X L/2

–U–

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V

S

T

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

N

N

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