Page 1
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 6
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC54/74HC574A is identical in pinout to the LS574. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising edge
of the Clock. The Output Enable input does not affect the states of the
flip–flops, but when Output Enable is high, all device outputs are forced to
the high–impedance state. Thus, data may be stored even when the outputs
are not enabled.
The HC574A is identical in function to the HCT374A but has the flip–flop
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
The HC574A is the noninverting version of the HC564.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 266 FETs or 66.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0
2 19
Q0
D1
D2
D3
D4
D5
D6
D7
CLOCK
OUTPUT ENABLE
3
4
5
6
7
8
9
11
1
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NON–
INVERTING
OUTPUTS
PIN 20 = V
CC
PIN 10 = GND
Design Criteria
Value
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Units
Internal Gate Count*
66.5
ÎÎÎ
ÎÎÎ
ÎÎÎ
ea
Internal Gate Propagation Delay
1.5
ÎÎÎ
ÎÎÎ
ÎÎÎ
ns
Internal Gate Power Dissipation
5.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
µW
Speed Power Product
0.0075
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
pJ
*Equivalent to a two–input NAND gate.
PIN ASSIGNMENT
D4
D2
D1
D0
OUTPUT
ENABLE
GND
D7
D6
D5
D3 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q3
Q2
Q1
Q0
V
CC
CLOCK
Q7
Q6
Q5
Q4
FUNCTION TABLE
Inputs Output
OE Clock D Q
L H H
L L L
L L,H, X No Change
H X X Z
X = Don’t Care
Z = High Impedance
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
Ceramic
Plastic
SOIC
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
1
20
1
20
Page 2
MC54/74HC574A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 35
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
P
D
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: –10 mW/_C from 65_ to 125_C
Ceramic DIP: –10 mW/_C from 100_ to 125_C
SOIC Package: –7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_C
v
125_C
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
Vin = VIH or V
IL
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or V
IL
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
V
OH
V
OL
Minimum High–Level Output
Voltage
Maximum Low–Level Output
Voltage
V
V
Page 3
MC54/74HC574A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3 MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_C
v
125_C
Unit
I
OZ
Maximum Three–State Leakage
Current
Output in High–Impedance State
Vin = VIL or V
IH
V
out
= VCC or GND
6.0
± 0.5
± 5.0
± 10
µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
|I
out
| = 0 µA
6.0
4.0
40
160
µA
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
– 55 to
25_C
v
85_C
v
125_C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
2.0
4.5
6 0
140
28
24
175
35
30
210
42
36
ns
t
TLH
,
t
THL
Maximum Output Transition Time, any Output
(Figures 1 and 4)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
C
in
Maximum Input Capacitance
10
10
10
pF
C
out
Maximum Three–State Output Capacitance, Output in High–Impedance State
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
24
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
ООООООООООООО
ООООООООООООО
ООООООООООООО
Guaranteed Limit
ООООООООООООО
ООООООООООООО
ООООООООООООО
V
– 55 to 25_C
v
85_C
v
125_C
Symbol
ООООООООООООО
ООООООООООООО
Parameter
Fig.
V
CC
Volts
Min
Max
Min
Max
Min
ÎÎ
ÎÎ
Max
Unit
t
su
ООООООООООООО
ООООООООООООО
ООООООООООООО
ООООООООООООО
ООООООООООООО
Minimum Setup Time, Data to Clock
3
2.0
4.6
6.0
50
10
9.0
65
13
11
75
15
13
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ns
t
h
ООООООООООООО
ООООООООООООО
ООООООООООООО
ООООООООООООО
Minimum Hold Time, Clock to Data
3
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ns
t
w
ООООООООООООО
ООООООООООООО
ООООООООООООО
ООООООООООООО
Minimum Pulse Width, Clock
1
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ns
tr, t
f
ООООООООООООО
ООООООООООООО
ООООООООООООО
ООООООООООООО
ООООООООООООО
Maximum Input Rise and Fall Times
1
2.0
4.5
6.0
1000
500
400
1000
500
400
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
1000
500
400
ns
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
pF
Page 4
MC54/74HC574A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–4
SWITCHING WAVEFORMS
Figure 1. Figure 2.
CLOCK
Q
t
r
t
f
V
CC
GND
90%
50%
10%
90%
50%
10%
t
PLH
t
PHL
t
TLH
t
THL
t
w
1/f
max
Q
Q
1.3 V
1.3 V
90%
10%
t
PZL
t
PLZ
t
PZHtPHZ
3.0 V
GND
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
Figure 3.
Figure 4.
EXPANDED LOGIC DIAGRAM
Figure 5. Test Circuit
50%CLOCK
V
CC
VALID
GND
V
CC
GND
t
su
t
h
50%DATA
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO VCC WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
1 k
Ω
C
D
Q
2
D0
19
Q0
C
D
Q
3
D1
18
Q1
C
D
Q
4
D2
17
Q2
C
D
Q
5
D3
16
Q3
C
D
Q
6
D4
15
Q4
C
D
Q
7
D5
14
Q5
C
D
Q
8
D6
13
Q6
C
D
Q
9
D7
12
Q7
11
CLOCK
1
OUTPUT ENABLE
Page 5
MC54/74HC574A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5 MOTOROLA
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
ISSUE E
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 23.88 25.15 0.940 0.990
B 6.60 7.49 0.260 0.295
C 3.81 5.08 0.150 0.200
D 0.38 0.56 0.015 0.022
F 1.40 1.65 0.055 0.065
G 2.54 BSC 0.100 BSC
H 0.51 1.27 0.020 0.050
J 0.20 0.30 0.008 0.012
K 3.18 4.06 0.125 0.160
L 7.62 BSC 0.300 BSC
M 0 15 0 15
N 0.25 1.02 0.010 0.040
_ _ _ _
A
20
1 10
11
B
F
C
SEATING
PLANE
D
H
G
K
N
J
M
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J
20 PL
M
B
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022
G 2.54 BSC0.100 BSC
J 0.21 0.380.008 0.015
K 2.80 3.550.110 0.140
L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040
_ __ _
E
1.27 1.770.050 0.070
1
11
10
20
–A–
SEATING
PLANE
K
N
FG
D
20 PL
–T–
M
A
M
0.25 (0.010) T
E
B
C
F
1.27 BSC0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
–B–
20
1
11
10
S
A
M
0.010 (0.25) B
S
T
D20X
M
B
M
0.010 (0.25)
P10X
J
F
G
18X
K
C
–T–
SEATING
PLANE
M
R
X 45
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
_ _
_ _
Page 6
MC54/74HC574A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–6
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MC54/74HC574A/D
*MC54/74HC574A/D*
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