Datasheet MC74HC564ADW, MC74HC564AN Datasheet (Motorola)



SEMICONDUCTOR TECHNICAL DATA

    

High–Performance Silicon–Gate CMOS

The MC74HC564A is identical in pinout to the LS564. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device is identical in function to the HC534A but has the flip–flop inputs on the opposite side of the package from the outputs to facilitate PC board layout.

Data meeting the setup time is clocked, in inverted form, to the outputs with the rising edge of the Clock. The Output Enable input does not affect the states of the flip–flops, but when Output Enable is high, all device outputs are forced to the high–impedance state. Thus, data may be stored even when the outputs are not enabled.

The HC564A is the inverting version of the HC574A.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 282 FETs or 70.5 Equivalent Gates

LOGIC DIAGRAM

219

DATA

INPUTS

OUTPUT

ENABLE

D0 D1 D2 D3 D4 D5 D6

D7

CLOCK

3 4 5 6 7 8 9

11

1

Q0

18

Q1

17

Q2

16

Q3

15

Q4

14

Q5

13

Q6

12

Q7

PIN 20 = V

PIN 10 = GND

INVERTING

OUTPUTS

CC



N SUFFIX

20

1

20

1

ORDERING INFORMATION

MC74HCXXXAN MC74HCXXXADW

PIN ASSIGNMENT

OUTPUT

ENABLE

D0

D1 D2 D3 5

D4

D5

D6

D7

GND

FUNCTION TABLE

Inputs Output

Output Enable Clock D Q

LHL LLH L L,H, X No Change

HXXZ

X = don’t care Z = high impedance

PLASTIC PACKAGE

CASE 738–03

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

1 2

3 4

6 7 8 9 10

20 19

18 17 16 15 14 13 12

11

Plastic SOIC

V

CC Q0 Q1

Q2 Q3

Q4 Q5 Q6 Q7 CLOCK

9/96

 Motorola, Inc. 1996

1

REV 0

MC74HC564A

Î

MAXIMUM RATINGS*

Symbol

V

I I

T

Î

DC Supply Voltage (Referenced to GND)

CC

V

DC Input Voltage (Referenced to GND)

in

DC Output Voltage (Referenced to GND)

out

I

DC Input Current, per Pin

in

DC Output Current, per Pin

out

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air Plastic DIP†

D

Storage Temperature

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

ОООООООООООО

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

V

Vin, V

T

tr, t

ÎÎ

DC Supply Voltage (Referenced to GND)

CC

DC Input Voltage, Output Voltage (Referenced to GND)

out

Operating Temperature, All Package Types

A

Input Rise and Fall Time VCC = 2.0 V

f

(Figure 1) VCC = 4.5 V

ОООООООООООО

Parameter

SOIC Package†

(Plastic DIP or SOIC Package)

Parameter

VCC = 6.0 V

Value

– 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5

± 20 ± 35 ± 75

750 500

– 65 to + 150

260

ÎÎÎÎ

Min

Max

2.0

6.0

0

V

CC

– 55

+ 125

0

1000

0

500

Î

0

400

Unit

V V

V mA mA mA

mW

_

C

_

C

Î

Unit

V

_

C

ns

Î

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

should be constrained to the

out

range GND v (Vin or V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

) v VCC.

out

MOTOROLA High–Speed CMOS Logic Data

2

DL129 — Rev 6

MC74HC564A

Î

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

V

Symbol

ÎÎ

V

IH

ÎÎ

V

IL

ÎÎ

ООООООО

Parameter

Minimum High–Level Input Voltage

ООООООО

Maximum Low–Level Input

ООООООО

Voltage

ООООООО

Test Conditions

ООООООО

V

= 0.1 V or VCC – 0.1 V

out

|I

| v 20 µA

out

ООООООО

V

= 0.1 V or VCC – 0.1 V

out

ООООООО

|I

| v 20 µA

out

ООООООО

CC

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

ÎÎ

3.0

4.5

ÎÎ

6.0

V

OH

ÎÎ

ÎÎÎОООООООÎООООООО

V

OL

ÎÎ

ÎÎÎОООООООÎООООООО

I

in

I

OZ

ÎÎ

I

CC

ÎÎ

Minimum High–Level Output

ООООООО

Voltage

ООООООО

Maximum Low–Level Output Voltage

ООООООО

Maximum Input Leakage Current Maximum Three–State Leakage

ООООООО

Current

ООООООО

Maximum Quiescent Supply

ООООООО

Current (per Package)

Vin = VIH or V

ООООООО

|I

| v 20 µA

out

ООООООО

Vin = VIH or VIL|I

Vin = VIH or V |I

| v 20 µA

out

ООООООО

Vin = VIH or VIL|I

IL

| v 2.4 mA

out

|I

| v 6.0 mA

out

|I

| v 7.8 mA

out

| v 2.4 mA

out

|I

| v 6.0 mA

out

|I

| v 7.8 mA

out

Vin = VCC or GND

Output in High–Impedance State

ООООООО

Vin = VIL or V V

= VCC or GND

out

ООООООО

Vin = VCC or GND

ООООООО

I

= 0 µA

out

IH

2.0

ÎÎ

4.5

6.0

ÎÎ

3.0

4.5

ÎÎ

6.0

2.0

4.5

ÎÎ

6.0

3.0

4.5

ÎÎ

6.0

ÎÎ

6.0

ÎÎ

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

– 55 to

V

25_C

ÎÎ

1.5

2.1

ÎÎ

3.15

4.2

ÎÎ

0.5

ÎÎ

0.9

1.35

ÎÎ

1.8

1.9

ÎÎ

4.4

5.9

ÎÎ

2.48

3.98

ÎÎ

5.48

0.1

ÎÎ

0.1

0.26

ÎÎ

0.26

± 0.1 ± 0.5

ÎÎ

ÎÎ4ÎÎ

v

85_C

ÎÎ

1.5

2.1

ÎÎ

3.15

4.2

ÎÎ

0.5

ÎÎ

0.9

1.35

ÎÎ

1.8

1.9

ÎÎ

4.4

5.9

ÎÎ

2.34

3.84

ÎÎ

5.34

0.1

ÎÎ

0.1

0.33

ÎÎ

0.33

± 1.0 ± 5.0

ÎÎ

40

v

125_C

ÎÎ

1.5

2.1

ÎÎ

3.15

4.2

ÎÎ

0.5

ÎÎ

0.9

1.35

ÎÎ

1.8

1.9

ÎÎ

4.4

5.9

ÎÎ

2.20

3.70

ÎÎ

5.20

0.1

ÎÎ

0.1

0.40

ÎÎ

0.40

± 1.0

± 10

ÎÎ

160

ÎÎ

Unit

Î

µA µA

Î

µA

Î

V

High–Speed CMOS Logic Data DL129 — Rev 6

3 MOTOROLA

MC74HC564A

Î

AC ELECTRICAL CHARACTERISTICS (C

= 50 pF, Input tr = tf = 6 ns)

L

Guaranteed Limit

ÎÎ

Symbol

f

max

ÎÎ

t

,

PLH

t

PHL

ÎÎ

t

,

PLZ

t

PHZ

ÎÎ

t

,

PZL

t

PZH

ÎÎ

t

,

TLH

t

THL

ÎÎ

C

in

ÎÎ

C

out

ÎÎ

ООООООООООООООО

Parameter

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

ООООООООООООООО

Maximum Propagation Delay, Clock to Q

(Figures 1 and 4)

ООООООООООООООО

Maximum Propagation Delay, Output Enable to Q

(Figures 2 and 5)

ООООООООООООООО

Maximum Propagation Delay, Output Enable to Q

(Figures 2 and 5)

ООООООООООООООО

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

ООООООООООООООО

Maximum Input Capacitance

ООООООООООООООО

Maximum Three–State Output Capacitance

ООООООООООООООО

(Output in High–Impedance State)

V

CC

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

—

ÎÎ

—

ÎÎ

– 55 to

V

25_C

ÎÎ

ÎÎ10ÎÎ

ÎÎ15ÎÎ

10 20 32 36

150 100

30 26

125

75 30 26

125

75 25 21

60 23 12 10

ÎÎ

v

85_C

8

15

ÎÎ

27 31

ÎÎ

190 150

ÎÎ

38 33

ÎÎ

155

80

ÎÎ

38 33

ÎÎ

155

80

ÎÎ

31 26

ÎÎ

75 27

ÎÎ

15 13

ÎÎ

10 15

ÎÎ

v

125_C

ÎÎ

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

5 10 22 26

225 175

45 38

190 100

45 38

190 100

38 33

90 32 18 15

10 15

Î

Unit

MHz

Î

pF

Î

pF

Î

ns

Typical @ 25°C, VCC = 5.0 V

C

PD

*Used to determine the no–load dynamic power consumption: PD = CPD V

Motorola High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (Input t

ÎÎÎОООООООООООООООÎÎÎÎООООООО

ÎÎ

Symbol

t

su

ÎÎ

t

ÎÎ

t

w

ÎÎ

tr, t

ÎÎ

Power Dissipation Capacitance (Per Flip–Flop)*

= tf = 6 ns)

r

ООООООООООООООО

Minimum Setup Time, Data to Clock

ООООООООООООООО

(Figure 3)

ООООООООООООООО

Minimum Hold Time, Clock to Data

h

(Figure 3)

ООООООООООООООО

Minimum Pulse Width, Clock

(Figure 1)

ООООООООООООООО

Maximum Input Rise and Fall Times

f

(Figure 1)

ООООООООООООООО

Parameter

40

2

f + ICC VCC. For load considerations, see Chapter 2 of the

CC

Guaranteed Limit

V

CC

ÎÎ

2.0

ÎÎ

3.0

4.5

ÎÎ

6.0

2.0

3.0

ÎÎ

4.5

ÎÎ

6.0

2.0

3.0

ÎÎ

4.5

ÎÎ

6.0

2.0

3.0

ÎÎ

4.5

ÎÎ

6.0

– 55 to

V

ÎÎ

25_C

ÎÎ

1000

ÎÎ

75 60 15 13

3 3 3 3

75 60 15 13

800 500 400

ÎÎ

v

85_C

95

ÎÎ

75 19

ÎÎ

16

3 3

ÎÎ

3

ÎÎ

3

95 75

ÎÎ

19

ÎÎ

16

1000

800

ÎÎ

500

ÎÎ

400

ÎÎ

v

125_C

110

ÎÎ

90 22

ÎÎ

19

3

ÎÎ

3

ÎÎ

3

110

90

ÎÎ

22

ÎÎ

19

1000

800

ÎÎ

500

ÎÎ

400

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

pF

Î

Unit

Î

ns

MOTOROLA High–Speed CMOS Logic Data

4

DL129 — Rev 6

SWITCHING WAVEFORMS

MC74HC564A

CLOCK

Q

90%

50%

10%

50%

10%

90%

t

r

t

w

1/f

max

t

PLH

t

TLH

Figure 1.

t

f

t

PHL

t

THL

DATA

CLOCK

V

CC

GND

50%

t

su

VALID

50%

Figure 3.

OUTPUT

ENABLE

Q

t

h

50%

t

PZL

50%

t

PZHtPHZ

50%

V

CC

GND

V

CC

GND

t

PLZ

Figure 2.

10%

90%

V

CC

GND HIGH

IMPEDANCE V

OL

V

OH

HIGH IMPEDANCE

TEST POINT

OUTPUT

DEVICE

UNDER

TEST

*Includes all probe and jig capacitance

CL*

Figure 4.

TEST CIRCUITS

DEVICE

UNDER

TEST

TEST POINT

OUTPUT

*Includes all probe and jig capacitance

1 k

CL*

CONNECT TO VCC WHEN

Ω

TESTING t

CONNECT TO GND WHEN

TESTING t

Figure 5.

PLZ

PHZ

AND t

PZL

PZH

.

High–Speed CMOS Logic Data DL129 — Rev 6

5 MOTOROLA

MC74HC564A

EXPANDED LOGIC DIAGRAM

2 19

3 18

D1

4 17

D2

5 16

D3

6 15

QD0

D

C

Q

D

C

Q

D

C

Q

D

C

QD4

D

Q0

Q1

Q2

Q3

Q4

D5

D7

CLOCK

OUTPUT

ENABLE

C

7 14

8 13

9 12

11

1

Q

D

C

QD6

D

C

Q

D

C

Q5

Q6

Q7

MOTOROLA High–Speed CMOS Logic Data

6

DL129 — Rev 6

–T–

SEATING PLANE

20

1

–A–

20

1

E

FG

–A–

D20X

0.010 (0.25) B

18X

M

G

MC74HC564A

OUTLINE DIMENSIONS

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

M

C

ISSUE E

M

A

L

J

20 PL

0.25 (0.010) T

M

11

10

N

D

20 PL

0.25 (0.010) T

B

K

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D–04

11

–B–

P10X

0.010 (0.25)

10

S

A

T

S

C

SEATING

–T–

PLANE

K

M

J

F

ISSUE E

M

B

M

R

X 45

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

DIM MIN MAX MIN MAX

A 25.66 27.171.010 1.070 B 6.10 6.600.240 0.260 C 3.81 4.570.150 0.180 D 0.39 0.550.015 0.022 E F G 2.54 BSC0.100 BSC J 0.21 0.380.008 0.015 K 2.80 3.550.110 0.140 L 7.62 BSC0.300 BSC

M

B

NOTES:

M 0 15 0 15 N 0.51 1.010.020 0.040

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 M 0 7 0 7

__

P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029

MILLIMETERSINCHES

1.27 BSC0.050 BSC

1.27 1.770.050 0.070

____

INCHESMILLIMETERS

__

High–Speed CMOS Logic Data DL129 — Rev 6

7 MOTOROLA

MC74HC564A

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

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MOTOROLA High–Speed CMOS Logic Data

8

*MC74HC564A/D*

◊

MC74HC564A/D

DL129 — Rev 6

Datasheet MC74HC564ADW, MC74HC564AN Datasheet (Motorola)

Specifications and Main Features

Frequently Asked Questions

User Manual