Page 1
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
"
!
High–Performance Silicon–Gate CMOS
The MC74HC4514 is identical in pinout to the MC14514B metal–gate
CMOS device. The device inputs are compatible with standard CMOS
outputs, with pullup resistors; they are compatible with LSTTL outputs.
This device consists of a 4–bit storage latch with a Latch Enable and Chip
Select input. When a low signal is applied to the Latch Enable input, the
Address is stored, and decoded. When the Chip Select input is high, all
sixteen outputs are forced to a low level.
The Chip Select input is provided to facilitate the chip–select, demultiplexing, and cascading functions.
The demultiplexing function is accomplished by using the Address inputs
to select the desired device output, and then by using the Chip Select as a
data input.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 268 FETs or 67 Equivalent Gates
LOGIC DIAGRAM
BINARY
ADDRESS
INPUTS
A0
A1
A2
A3
21
3
2
1LATCH
ENABLE
CHIP
SELECT
PIN 24 = V
CC
PIN 12 = GND
4–BIT
STORAGE
LATCH
4–TO–16
LINE
DECODER
11
9
10
8
7
6
5
4
18
17
20
19
14
13
16
15
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
ACTIVE–HIGH
OUTPUTS
PIN ASSIGNMENT
Y5
Y7
A1
A0
LATCH
ENABLE
Y3
Y4
Y6 Y10
A2
A3
CHIP
SELECT
V
CC
Y15
Y14
Y9
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
13
11
12
21
22
23
24
Y13
Y12
Y8
Y11
Y0
GND
Y2
Y1
N SUFFIX
PLASTIC PACKAGE
CASE 724–03
ORDERING INFORMATION
MC74HCXXXXN
MC74HCXXXXDW
Plastic
SOIC
1
24
DW SUFFIX
SOIC PACKAGE
CASE 751E–04
1
24
Page 2
MC74HC4514
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 50
mA
P
D
Power Dissipation in Still Air Plastic DIP†
SOIC Package†
750
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_C
v
125_C
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
Vin = VIH or VIL|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
I
out
= 0 µA
6.0
8
80
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
V
OH
V
OL
Minimum High–Level Output
Voltage
Maximum Low–Level Output
Voltage
V
V
Page 3
MC74HC4514
High–Speed CMOS Logic Data
DL129 — Rev 6
3 MOTOROLA
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
– 55 to
25_C
v
85_C
v
125_C
Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Chip Select to Output Y
(Figures 1 and 5)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
t
PLH
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
t
PHL
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
t
PLH
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
t
PHL
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
in
Maximum Input Capacitance
—
10
10
10
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
70
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (Input t
r
= tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
– 55 to
25_C
v
85_C
v
125_C
Unit
t
su
Minimum Setup Time, Input A to Latch Enable
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
h
Minimum Hold Time, Latch Enable to Input A
(Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
t
w
Minimum Pulse Width, Latch Enable
(Figure 3)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 5)
Maximum Propagation Delay, Latch Enable to Output Y
(Figures 3 and 5)
ns
ns
C
PD
Power Dissipation Capacitance (Per Package)*
pF
Page 4
MC74HC4514
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
SWITCHING WAVEFORMS
Figure 1. Figure 2.
Figure 3. Figure 4.
*Includes all probe and jig capacitance
Figure 5. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
t
r
t
f
t
PHL
t
PLH
t
THL
t
TLH
10%
50%
V
CC
GND
10%
50%
90%
90%
OUTPUT Y
CHIP
SELECT
50%
t
PHL
t
PLH
V
CC
GND
VALID VALID
50%
INPUT A
OUTPUT Y
50%
INPUT A
LATCH
ENABLE
V
CC
V
CC
GND
GND
VALID
t
h
t
su
50%
V
CC
GND
t
PHL
50%
t
PLH
50%
50%
t
w
OUTPUT Y
LATCH
ENABLE
Page 5
MC74HC4514
High–Speed CMOS Logic Data
DL129 — Rev 6
5 MOTOROLA
FUNCTION TABLE
Address Inputs
Selected
Latch
Enable
Chip
Select
A3 A2 A1 A0
Output
(High)
H L L L L L Y0
H L L L L H Y1
H L L L H L Y2
H L L L H H Y3
H L L H L L Y4
H L L H L H Y5
H L L H H L Y6
H L L H H H Y7
H L H L L L Y8
H L H L L H Y9
H L H L H L Y10
H L H L H H Y11
H L H H L L Y12
H L H H L H Y13
H L H H H L Y14
H L H H H H Y15
X H X X X X
All
Outputs = L
L L X X X X
Latched
Data
PIN DESCRIPTIONS
ADDRESS INPUTS
A0, A1, A2, A3 (Pins 2, 3, 21, 22)
Address Inputs. These inputs are decoded to produce a
high level on one of 16 outputs. The inputs are arranged
such that A3 is the most–significant bit and A0 is the least–
significant bit. The decimal equivalent of the binary input
address indicates which of the 16 data outputs, Y0 –Y15, is
selected.
OUTPUTS
Y0 – Y15 (Pins 11, 9, 10, 8, 7, 6, 5, 4, 18, 17, 20, 19, 14,
13, 16, 15)
Active–High Outputs. These outputs produce a high level
when selected (Latch Enable = H, Chip Select = L) and are at
a low level when not selected.
CONTROL INPUTS
Latch Enable (Pin 1)
Latch Enable Input. A low level on this input stores the
data on the Address data inputs in the 4–bit latch. A high
level on the Latch Enable input makes the latch transparent
and allows the outputs to follow the inputs. Note that the data
is latched only while the Latch Enable input is at a low level.
Chip Select (Pin 23)
Chip Select Input. A high on this input produces a low level
on all outputs, regardless of what appears at the address or
Latch Enable inputs. A low level on the Chip Select input
allows the selected output to produce a high level.
TIMING DIAGRAM
INPUT A
LATCH ENABLE
CHIP SELECT
OUTPUT Y
Page 6
MC74HC4514
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
6
EXPANDED LOGIC DIAGRAM
Y0
11
A
BC D
Y1
9
AB
CD
Y2
10
A
BC D
Y3
8
AB C
D
Y4
7
A
BC D
Y5
6
AB
CD
Y6
5
A
BC D
Y7
4
AB CD
Y8
18
A
BC D
Y9
17
AB
CD
Y10
20
A
BC D
Y11
19
AB C
D
Y12
14
A
BC D
Y13
13
AB
CD
Y14
16
A
BC D
Y15
15
AB CD
2
A0
3
A1
21
A2
22
A3
1
LATCH
ENABLE
23
CHIP
SELECT
DATALEQ
Q
DATALEQ
Q
DATALEQ
Q
DATALEQ
Q
Page 7
MC74HC4514
High–Speed CMOS Logic Data
DL129 — Rev 6
7 MOTOROLA
MICROPROCESSOR MEMORY DECODING
A12
A11
A10
A9
A8
MC146805
CHIP
SELECT
LATCH
ENABLE
A3
A2
A1
A0
+ V
MC4514
Y15
Y14
Y13
Y12
Y11
Y10
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0 0000–00FF
0100–01FF
0200–02FF
0300–03FF
0400–04FF
0500–05FF
0600–06FF
0700–07FF
0800–08FF
0900–09FF
0A00–0AFF
0B00–0BFF
0C00–0CFF
0D00–0DFF
0E00–0EFF
0F00–0FFF
CHIP
SELECT
LATCH
ENABLE
A3
A2
A1
A0
+ V
MC4514
Y15
Y14
Y13
Y12
Y11
Y10
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0 1000–10FF
1100–11FF
1200–12FF
1300–13FF
1400–14FF
1500–15FF
1600–16FF
1700–17FF
1800–18FF
1900–19FF
1A00–1AFF
1B00–1BFF
1C00–1CFF
1D00–1DFF
1E00–1EFF
1F00–1FFF
HC04
TO DEVICE SELECTS
Page 8
MC74HC4514
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
8
CODE TO CODE CONVERSION — HEXADECIMAL TO BCD
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
GND
CHIP
SELECT
LATCH
ENABLE
A3
A2
A1
A0
MC146805
+ V
ALL DIODES GENERAL
PURPOSE GERMANIUM
R = 10 k
HC4050
R = 2 k
Ω
MC4511
A3
A2
A1
A0
R = 2 k
COMMON CATHODE LEDs
HC4050
Page 9
MC74HC4514
High–Speed CMOS Logic Data
DL129 — Rev 6
9 MOTOROLA
OUTLINE DIMENSIONS
NOTES:
1. CHAMFERED CONTOUR OPTIONAL.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
4. CONTROLLING DIMENSION: INCH.
–A–
–B–
24 13
12
1
–T–
SEATING
PLANE
24 PL
K
E
F
N
C
D
G
M
A
M
0.25 (0.010) T
24 PLJ
M
B
M
0.25 (0.010) T
L
M
NOTE 1
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 1.230 1.265 31.25 32.13
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.020 0.38 0.51
E 0.050 BSC 1.27 BSC
F 0.040 0.060 1.02 1.52
G 0.100 BSC 2.54 BSC
J 0.007 0.012 0.18 0.30
K 0.110 0.140 2.80 3.55
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01
_ _ _ _
N SUFFIX
PLASTIC PACKAGE
CASE 724–03
ISSUE D
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
–A–
–B– P12X
D24X
12
1324
1
M
0.010 (0.25) B
M
S
A
M
0.010 (0.25) B
S
T
–T–
G
22X
SEATING
PLANE
K
C
R
X 45
_
M
F
J
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 15.25 15.54 0.601 0.612
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.41 0.90 0.016 0.035
G 1.27 BSC 0.050 BSC
J 0.23 0.32 0.009 0.013
K 0.13 0.29 0.005 0.011
M 0 8 0 8
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
____
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MC74HC4514/D
*MC74HC4514/D*
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