Page 1
SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1995
10/95
# $"
#"% #"% $"
" "
$ #!
High–Performance Silicon–Gate CMOS
The MC74HC4316A utilizes silicon–gate CMOS technology to achieve
fast propagation delays, low ON resistances, and low OFF–channel leakage
current. This bilateral switch/multiplexer/demultiplexer controls analog and
digital voltages that may vary across the full analog power–supply range
(from VCC to VEE).
The HC4316A is similar in function to the metal–gate CMOS MC14016
and MC14066, and to the High–Speed CMOS HC4016A and HC4066A.
Each device has four independent switches. The device control and Enable
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs. The device has been designed so
that the ON resistances (RON) are much more linear over input voltage than
RON of metal–gate CMOS analog switches. Logic–level translators are
provided so that the On/Off Control and Enable logic–level voltages need
only be VCC and GND, while the switch is passing signals ranging between
VCC and VEE. When the Enable pin (active–low) is high, all four analog
switches are turned off.
• Logic–Level Translator for On/Off Control and Enable Inputs
• Fast Switching and Propagation Speeds
• High ON/OFF Output Voltage Ratio
• Diode Protection on All Inputs/Outputs
• Analog Power–Supply Voltage Range (VCC – VEE) = 2.0 to 12.0 Volts
• Digital (Control) Power–Supply Voltage Range (VCC – GND) = 2.0 to
6.0 Volts, Independent of V
EE
• Improved Linearity of ON Resistance
• Chip Complexity: 66 FETs or 16.5 Equivalent Gates
LOGIC DIAGRAM
X
A
A ON/OFF CONTROL
ANALOG
SWITCH
LEVEL
TRANSLATOR
ANALOG
OUTPUTS/INPUTS
PIN 16 = V
CC
PIN 8 = GND
PIN 9 = V
EE
GND
≥
V
EE
2
Y
A
1
15
X
B
B ON/OFF CONTROL
ANALOG
SWITCH
LEVEL
TRANSLATOR
3
Y
B
4
5
X
C
C ON/OFF CONTROL
ANALOG
SWITCH
LEVEL
TRANSLATOR
11
Y
C
10
6
X
D
D ON/OFF CONTROL
ANALOG
SWITCH
LEVEL
TRANSLATOR
12
Y
D
13
14
ENABLE
7
ANALOG INPUTS/OUTPUTS = XA, XB, XC, X
D
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
FUNCTION TABLE
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Y
D
X
D
D ON/OFF
CONTROL
A ON/OFF
CONTROL
V
CC
V
EE
X
C
Y
C
X
B
Y
B
Y
A
X
A
GND
ENABLE
C ON/OFF
CONTROL
B ON/OFF
CONTROL
Inputs
State of
On/Off Analog
Enable Control Switch
L H On
L L Off
H X Off
X = don’t care
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
1
16
1
16
ORDERING INFORMATION
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADT
Plastic
SOIC
TSSOP
1
14
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
Page 2
MC74HC4316A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
Positive DC Supply Voltage (Ref. to GND)
(Ref. to VEE)
– 0.5 to + 7.0
– 0.5 to + 14.0
V
V
EE
Negative DC Supply Voltage (Ref. to GND)
– 7.0 to + 0.5
V
V
IS
Analog Input Voltage
VEE – 0.5
to VCC + 0.5
V
V
in
DC Input Voltage (Ref. to GND)
– 0.5 to VCC + 0.5
V
I
DC Current Into or Out of Any Pin
± 25
mA
P
D
Power Dissipation in Still Air Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
Positive DC Supply Voltage (Ref. to GND)
2.0
6.0
V
V
EE
Negative DC Supply Voltage (Ref. to GND)
– 6.0
GND
V
V
IS
Analog Input Voltage
V
EEVCC
V
V
in
Digital Input Voltage (Ref. to GND)
GND
V
CC
V
VIO*
Static or Dynamic Voltage Across Switch
—
1.2
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time VCC = 2.0 V
(Control or Enable Inputs) VCC = 3.0 V
(Figure 10) VCC = 4.5 V
VCC = 6.0 V
0
0
0
0
1000
600
500
400
ns
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) V
EE
= GND Except Where Noted
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
V
IH
Minimum High–Level Voltage,
Control or Enable Inputs
Ron = Per Spec
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
IL
Maximum Low–Level Voltage,
Control or Enable Inputs
Ron = Per Spec
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
I
in
Maximum Input Leakage
Current, Control or Enable
Inputs
Vin = VCC or GND
VEE = – 6.0 V
6.0
± 0.1
± 1.0
± 1.0
µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
VIO = 0 V VEE = GND
VEE = – 6.0
6.0
6.0
2
4
20
40
40
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.
Page 3
MC74HC4316A
High–Speed CMOS Logic Data
DL129 — Rev 6
3 MOTOROLA
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to V
EE
)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
V
EE
V
– 55 to
25_C
v
85_Cv 125_C
Unit
R
on
Maximum “ON” Resistance
Vin = V
IH
VIS = VCC to V
EE
IS v 2.0 mA (Figures 1, 2)
2.0*
4 5
4.5
6.0
0.0
0.0
– 4.5
– 6.0
—
160
90
90
—
200
110
110
—
240
130
130
Ω
Vin = V
IH
VIS = VCC or VEE (Endpoints)
IS v 2.0 mA (Figures 1, 2)
2.0
4.5
4.5
6.0
0.0
0.0
– 4.5
– 6.0
—
90
70
70
—
115
90
90
—
140
105
105
∆R
on
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Vin = V
IH
VIS = 1/2 (VCC – VEE)
IS v 2.0 mA
2.0
4.5
4.5
6.0
0.0
0.0
– 4.5
– 6.0
—
20
15
15
—
25
20
20
—
30
25
25
Ω
I
off
Maximum Off–Channel Leakage
Current, Any One Channel
Vin = V
IL
VIO = VCC or V
EE
Switch Off (Figure 3)
6.0
– 6.0
0.1
0.5
1.0
µA
I
on
Maximum On–Channel Leakage
Current, Any One Channel
Vin = V
IH
VIS = VCC or V
EE
(Figure 4)
6.0
– 6.0
0.1
0.5
1.0
µA
*At supply voltage (VCC – VEE) approaching 2 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltage
operation, it is recommended that these devices only be used to control digital signals.
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Control or Enable tr = tf = 6 ns, VEE = GND)
Guaranteed Limit
Symbol
Parameter
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figures 8 and 9)
2.0
4.5
6.0
40
6
5
50
8
7
60
9
8
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Control or Enable to Analog Output
(Figures 10 and 11)
2.0
4.5
6.0
130
40
30
160
50
40
200
60
50
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Control or Enable to Analog Output
(Figures 10 and 11)
2.0
4.5
6.0
140
40
30
175
50
40
250
60
50
ns
C
Maximum Capacitance ON/OFF Control
and Enable Inputs
—
10
10
10
pF
Control Input = GND
Analog I/O
Feedthrough
—
—
35
1.0
35
1.0
35
1.0
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Switch) (Figure 13)*
15
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Page 4
MC74HC4316A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbol
Parameter
Test Conditions
V
CC
V
V
EE
V
Limit*
25_C
Unit
BW
Maximum On–Channel Bandwidth or
Minimum Frequency Response
(Figure 5)
fin = 1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at V
OS
Increase fin Frequency Until dB Meter
Reads – 3 dB RL = 50 Ω, CL = 10 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
150
160
160
MHz
—
Off–Channel Feedthrough Isolation
(Figure 6)
fin Sine Wave
Adjust fin Voltage to Obtain 0 dBm at V
IS
fin = 10 kHz, RL = 600 Ω, CL = 50 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 50
– 50
– 50
dB
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 40
– 40
– 40
—
Feedthrough Noise, Control to
Switch
(Figure 7)
Vin v 1 MHz Square Wave (tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
RL = 600 Ω, CL = 50 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
60
130
200
mV
PP
RL = 10 kΩ, CL = 10 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
30
65
100
—
Crosstalk Between Any Two
Switches
(Figure 12)
fin Sine Wave
Adjust fin Voltage to Obtain 0 dBm at V
IS
fin = 10 kHz, RL = 600 Ω, CL = 50 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 70
– 70
– 70
dB
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 80
– 80
– 80
THD
Total Harmonic Distortion
(Figure 14)
fin = 1 kHz, RL = 10 kΩ, CL = 50 pF
THD = THD
Measured
– THD
Source
VIS = 4.0 VPP sine wave
VIS = 8.0 VPP sine wave
VIS = 11.0 VPP sine wave
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
0.10
0.06
0.04
%
*Limits not tested. Determined by design and verified by qualification.
Page 5
MC74HC4316A
High–Speed CMOS Logic Data
DL129 — Rev 6
5 MOTOROLA
Figure 1b. Typical On Resistance,
VCC – VEE = 4.5 V
Figure 1d. Typical On Resistance,
VCC – VEE = 9.0 V
Figure 1c. Typical On Resistance,
VCC – VEE = 6.0 V
Figure 1e. Typical On Resistance,
Figure 1a. Typical On Resistance,
VCC – VEE = 2.0 V
Figure 2. On Resistance Test Set–Up
PLOTTER
MINI COMPUTER
PROGRAMMABLE
POWER
SUPPLY
DC ANALYZER
V
CC
+–
ANALOG IN COMMON OUT
GND
DEVICE
UNDER TEST
V
EE
TBD
TBD
TBD
TBD
TBD
Page 6
MC74HC4316A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
6
Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up
Figure 4. Maximum On Channel Leakage Current,
Test Set–Up
OFF
16
V
CC
V
EE
A
V
CC
V
EE
V
CC
O/I
7
8
9
SELECTED
CONTROL
INPUT
V
IL
ON
16
V
CC
N/C
A
V
EE
V
CC
V
EE
7
8
9
SELECTED
CONTROL
INPUT
V
IH
Figure 5. Maximum On–Channel Bandwidth
Test Set–Up
ON
16
V
CC
0.1 µF
CL*
f
in
TO dB
METER
*Includes all probe and jig capacitance.
R
L
R
L
V
EE
7
8
9
SELECTED
CONTROL
INPUT
V
CC
Figure 6. Off–Channel Feedthrough Isolation,
Test Set–Up
OFF
16
V
CC
0.1 µF
CL*
f
in
TO dB
METER
*Includes all probe and jig capacitance.
R
L
V
EE
7
8
9
SELECTED
CONTROL
INPUT
R
L
V
CC
Figure 7. Feedthrough Noise, Control to Analog Out,
Test Set–Up
16
V
CC
*Includes all probe and jig capacitance.
ON/OFF
CONTROL
R
L
SELECTED
CONTROL
INPUT
V
EE
7
8
9
CL*
TEST
POINT
R
L
V
CC
GND
ANALOG IN
ANALOG OUT
50%
t
PLH
t
PHL
50%
Figure 8. Propagation Delays, Analog In to
Analog Out
V
IS
Page 7
MC74HC4316A
High–Speed CMOS Logic Data
DL129 — Rev 6
7 MOTOROLA
POSITION WHEN TESTING t
PLZ
AND t
PZL
Figure 9. Propagation Delay Test Set–Up
ON
16
V
CC
*Includes all probe and jig capacitance.
TEST
POINT
ANALOG O/IANALOG I/O
50 pF*
SELECTED
CONTROL
INPUT
V
CC
Figure 10. Propagation Delay, ON/OFF Control
to Analog Out
ON/OFF
V
CC
TEST
POINT
16
V
CC
1 k
Ω
POSITION WHEN TESTING t
PHZ
AND t
PZH
50 pF*
1
2
1
2
Figure 11. Propagation Delay Test Set–Up
1
2
Figure 12. Crosstalk Between Any Two Switches,
Test Set–Up (Adjacent Channels Used)
R
L
ON
16
*Includes all probe and jig capacitance.
OFF
R
L
V
IS
f
in
0.1
µ
F
Figure 13. Power Dissipation Capacitance
Test Set–Up
16
V
CC
N/C
ON/OFF
A
N/C
SELECTED
CONTROL
INPUT
CONTROL
ON
16
V
CC
10 µF
CL*
f
in
R
L
TO
DISTORTION
METER
*Includes all probe and jig capacitance.
V
OS
V
IS
SELECTED
CONTROL
INPUT
V
CC
Figure 14. Total Harmonic Distortion, Test Set–Up
7
8
9
*Includes all probe and jig capacitance.
8
9
CONTROL
OR
ENABLE
V
CC
7
8
9
V
EE
CL*
CL*
R
L
SELECTED
CONTROL
INPUT
V
CC
TEST
POINT
ANALOG I/O
7
8
9
V
EE
7
8
9
V
EE
50%
50%
90%
10%
t
PZL
t
PLZ
t
PZHtPHZ
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
V
CC
GND
50%
ANALOG
OUT
CONTROL
ENABLE
t
r
t
f
Page 8
MC74HC4316A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
8
0
–10
–20
–30
–40
–50
–100
1.0 2.0
FREQUENCY (kHz)
dBm
–60
–70
–80
–90
FUNDAMENTAL FREQUENCY
DEVICE
SOURCE
Figure 15. Plot, Harmonic Distortion
3.0
APPLICATION INFORMATION
The Enable and Control pins should be at VCC or GND
logic levels, VCC being recognized as logic high and GND
being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or
VEE through a low value resistor. This minimizes crosstalk
and feedthrough noise that may be picked up by the unused
I/O pins.
The maximum analog voltage swings are determined by
the supply voltages VCC and VEE. The positive peak analog
voltage should not exceed VCC. Similarly, the negative peak
analog voltage should not go below VEE. In the example
below, the difference between VCC and VEE is twelve volts.
Therefore, using the configuration in Figure 16, a maximum
analog signal of twelve volts peak–to–peak can be controlled.
When voltage transients above VCC and/or below VEE are
anticipated on the analog channels, external diodes (Dx) are
recommended as shown in Figure 17. These diodes should
be small signal, fast turn–on types able to absorb the maximum anticipated current surges during clipping. An alternate
method would be to replace the Dx diodes with MOsorbs
(Motorola high current surge protectors). MOsorbs are fast
turn–on devices ideally suited for precise dc protection with
no inherent wear out mechanism.
ANALOG O/I
ON
16
VCC = 6 V
ANALOG I/O
+ 6 V
–6 V
+ 6 V
–6 V
ENABLE CONTROL
INPUTS
(VCC OR GND)
ON
16
V
CC
D
x
D
x
V
CC
D
x
Figure 16. Figure 17. Transient Suppressor Application
8
SELECTED
CONTROL
INPUT
D
x
SELECTED
CONTROL
INPUT
+ 6 V
V
EE
–6 V
V
CC
V
EE
ENABLE CONTROL
INPUTS
(VCC OR GND)
V
EE
V
EE
Page 9
MC74HC4316A
High–Speed CMOS Logic Data
DL129 — Rev 6
9 MOTOROLA
VCC = 5 V
16
HC4316A
ENABLE
AND
CONTROL
INPUTS
8
5
6
14
15
TTL
ANALOG
SIGNALS
R*
ANALOG
SIGNALS
HCT
BUFFER
R* = 2 TO 10 k
Ω
CHANNEL 4
CHANNEL 3
CHANNEL 2
CHANNEL 1
1 OF 4
SWITCHES
COMMON I/O
1 2 3 4
CONTROL INPUTS
INPUT
OUTPUT
0.01
µ
F
LF356 OR
EQUIVALENT
a. Using Pull–Up Resistors b. Using HCT Buffer
Figure 18. LSTTL/NMOS to HCMOS Interface
Figure 19. Switching a 0–to–12 V Signal Using a
Single Power Supply (GND ≠ 0 V)
Figure 20. 4–Input Multiplexer Figure 21. Sample/Hold Amplifier
+
–
1 OF 4
SWITCHES
+5 V
16
HC4016A
CONTROL
INPUTS
7
5
6
14
15
LSTTL/
NMOS
ANALOG
SIGNALS
ANALOG
SIGNALS
1 OF 4
SWITCHES
1 OF 4
SWITCHES
1 OF 4
SWITCHES
7
R*R*R*
R*
VEE = 0
TO –6 V
9
VEE = 0
TO –6 V
9
12 V
POWER
SUPPLY
R1 = R
2
R
1
R
2
VCC = 12 V
VEE = 0 V
GND = 6 V
12 V
PP
ANALOG
INPUT
SIGNAL
C
R
3
R
4
V
CC
V
EE
1 OF 4
SWITCHES
ANALOG
OUTPUT
SIGNAL
12 V
0
R1 = R
2
R3 = R
4
Page 10
MC74HC4316A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
10
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
M
S
18.80
6.35
3.69
0.39
1.02
0.21
2.80
7.50
0
°
0.51
19.55
6.85
4.44
0.53
1.77
0.38
3.30
7.74
10
°
1.01
0.740
0.250
0.145
0.015
0.040
0.008
0.110
0.295
0
°
0.020
0.770
0.270
0.175
0.021
0.070
0.015
0.130
0.305
10
°
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
2.54 BSC
1.27 BSC
0.100 BSC
0.050 BSC
–A
–
B
1 8
916
F
H
G
D
16 PL
S
C
–T
–
SEATING
PLANE
K
J
M
L
T A0.25 (0.010)
M M
0.25 (0.010) T B A
M
S S
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
9.80
3.80
1.35
0.35
0.40
0.19
0.10
0
°
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7
°
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004
0°
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7°
0.244
0.019
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
916
–A
–
–B
–
D 16 PL
K
C
G
–T
–
SEATING
PLANE
R X 45°
M
J
F
P 8 PL
0.25 (0.010) B
M M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
Page 11
MC74HC4316A
High–Speed CMOS Logic Data
DL129 — Rev 6
11 MOTOROLA
OUTLINE DIMENSIONS
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
ISSUE O
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
3. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
_ _ _ _
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V
S
T
L
–U–
SEATING
PLANE
0.10 (0.004)
–T–
SECTION N–N
DETAIL E
J
J1
K
K1
DETAIL E
F
M
–W–
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
–V–
14X REFK
N
N
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MC74HC4316A/D
*MC74HC4316A/D*
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