Datasheet MC74HC4066ND, MC74HC4066FL2, MC74HC4066FR1, MC74HC4066FR2, MC74HC4066FEL Datasheet (MOTOROLA)



SEMICONDUCTOR TECHNICAL DATA

1

REV 6

 Motorola, Inc. 1995

10/95

!  "  ! #! #

High–Performance Silicon–Gate CMOS

The MC54/74HC4066 utilizes silicon–gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF–channel leakage current. This bilateral switch/multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power–supply range (from V

CC

to GND).

The HC4066 is identical in pinout to the metal–gate CMOS MC14016 and MC14066. Each device has four independent switches. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal–gate CMOS analog switches.

This device is identical in both function and pinout to the HC4016. The ON/OFF control inputs are compatible with standard CMOS outputs; with pullup r esistors, they are compatible w ith LSTTL o utputs. For analog switches with voltage–level translators, see the HC4316.

• Fast Switching and Propagation Speeds

• High ON/OFF Output Voltage Ratio

• Low Crosstalk Between Switches

• Diode Protection on All Inputs/Outputs

• Wide Power–Supply Voltage Range (VCC – GND) = 2.0 to 12.0 Volts

• Analog Input Voltage Range (VCC – GND) = 2.0 to 12.0 Volts

• Improved Linearity and Lower ON Resistance over Input Voltage than

the MC14016 or MC14066 or HC4016

• Low Noise

• Chip Complexity: 44 FETs or 11 Equivalent Gates

LOGIC DIAGRAM

X

A

Y

A

1 2

A ON/OFF CONTROL

13

X

B

Y

B

4 3

B ON/OFF CONTROL

5

X

C

Y

C

8 9

C ON/OFF CONTROL

6

X

D

Y

D

11 10

D ON/OFF CONTROL

12

ANALOG OUTPUTS/INPUTS

ANALOG INPUTS/OUTPUTS = XA, XB, XC, X

D

PIN 14 = V

CC

PIN 7 = GND



FUNCTION TABLE

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

Y

D

X

D

D ON/OFF CONTROL

A ON/OFF CONTROL

V

CC

X

C

Y

C

X

B

Y

B

Y

A

X

A

GND

C ON/OFF CONTROL

B ON/OFF CONTROL

On/Off Control State of

Input Analog Switch

L Off H On

D SUFFIX

SOIC PACKAGE

CASE 751A–03

N SUFFIX

PLASTIC PACKAGE

CASE 646–06

ORDERING INFORMATION

MC54HCXXXXJ MC74HCXXXXN MC74HCXXXXD MC74HCXXXXDT

Ceramic Plastic SOIC TSSOP

1

14

1

14

1

14

DT SUFFIX

TSSOP PACKAGE

CASE 948G–01

J SUFFIX

CERAMIC PACKAGE

CASE 632–08

1

14

MC54/74HC4066

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

Positive DC Supply Voltage (Referenced to GND)

– 0.5 to + 14.0

V

IS

Analog Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

in

Digital Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

V

I

DC Current Into or Out of Any Pin

± 25

mA

P

D

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

TSSOP Package†

750 500 450

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

(Ceramic DIP)

260 300

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

Positive DC Supply Voltage (Referenced to GND)

2.0

12.0

V

IS

Analog Input Voltage (Referenced to GND)

GND

V

CC

V

in

Digital Input Voltage (Referenced to GND)

GND

V

CC

V

VIO*

Static or Dynamic Voltage Across Switch

—

1.2

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time, ON/OFF Control Inputs (Figure 10) VCC = 2.0 V

VCC = 4.5 V VCC = 9.0 V

VCC = 12.0 V

0 0 0 0

1000

500 400 250

ns

*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may

be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC V

– 55 to

25_C

v

85_Cv 125_C

Unit

V

IH

Minimum High–Level Voltage ON/OFF Control Inputs

Ron = Per Spec

2.0

4.5

9.0

12.0

1.5

3.15

6.3

8.4

1.5

3.15

6.3

8.4

1.5

3.15

6.3

8.4

V

IL

Maximum Low–Level Voltage ON/OFF Control Inputs

Ron = Per Spec

2.0

4.5

9.0

12.0

0.3

0.9

1.8

2.4

0.3

0.9

1.8

2.4

0.3

0.9

1.8

2.4

V

I

in

Maximum Input Leakage Current ON/OFF Control Inputs

Vin = VCC or GND

12.0

± 0.1

± 1.0

µA

I

CC

Maximum Quiescent Supply Current (per Package)

Vin = VCC or GND VIO = 0 V

6.0

12.0

2 8

20 80

40

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.

MC54/74HC4066

High–Speed CMOS Logic Data DL129 — Rev 6

3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC V

– 55 to

25_C

v

85_Cv 125_C

Unit

R

on

Maximum “ON” Resistance

Vin = V

IH

VIS = VCC to GND IS v 2.0 mA (Figures 1, 2)

2.0†

4.5

9.0

12.0

—

170

85 85

— 215 106 106

— 255 130 130

Ω

Vin = V

IH

VIS = VCC or GND (Endpoints) IS v 2.0 mA (Figures 1, 2)

2.0

4.5

9.0

12.0

— 85 63 63

—

106

78 78

— 130

95

∆R

on

Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package

Vin = V

IH

VIS = 1/2 (VCC – GND) IS v 2.0 mA

2.0

4.5

9.0

12.0

— 30 20 20

— 35 25 25

—

40

30

Ω

I

off

Maximum Off–Channel Leakage Current, Any One Channel

Vin = V

IL

VIO = VCC or GND Switch Off (Figure 3)

12.0

0.1

0.5

1.0

µA

I

on

Maximum On–Channel Leakage Current, Any One Channel

Vin = V

IH

VIS = VCC or GND (Figure 4)

12.0

0.1

0.5

1.0

µA

†At supply voltage (VCC – GND) approaching 2 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltage

operation, it is recommended that these devices only be used to control digital signals.

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC V

– 55 to

25_C

v

85_Cv 125_C

Unit

t

PLH

,

t

PHL

Maximum Propagation Delay, Analog Input to Analog Output

(Figures 8 and 9)

2.0

4.5

9.0

12.0

50 10 10 10

65 13 13 13

75

15

ns

t

PLZ

,

t

PHZ

Maximum Propagation Delay, ON/OFF Control to Analog Output

(Figures 10 and 11)

2.0

4.5

9.0

12.0

150

30 30 30

190

38 30 30

225

45

30

ns

t

PZL

,

t

PZH

Maximum Propagation Delay, ON/OFF Control to Analog Output

(Figures 10 and 1 1)

2.0

4.5

9.0

12.0

125

25 25 25

160

32 32 32

185

37

ns

C

Maximum Capacitance ON/OFF Control Input

—

10

pF

Control Input = GND

Analog I/O

Feedthrough

— —

35

1.0

35

1.0

35

1.0

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Switch) (Figure 13)*

15

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC4066

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

4

ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)

Symbol

Parameter

Test Conditions

V

CC

V

Limit*

25_C

54/74HC

Unit

BW

Maximum On–Channel Bandwidth or Minimum Frequency Response

(Figure 5)

fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at V

OS

Increase fin Frequency Until dB Meter Reads – 3 dB

RL = 50 Ω, CL = 10 pF

4.5

9.0

12.0

150 160 160

MHz

—

Off–Channel Feedthrough Isolation

(Figure 6)

fin  Sine Wave Adjust fin Voltage to Obtain 0 dBm at V

IS

fin = 10 kHz, RL = 600 Ω, CL = 50 pF

4.5

9.0

12.0

– 50 – 50 – 50

dB

fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF

4.5

9.0

12.0

– 40 – 40 – 40

—

Feedthrough Noise, Control to Switch

(Figure 7)

Vin v 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A

RL = 600 Ω, CL = 50 pF

4.5

9.0

12.0

60

130 200

mV

PP

RL = 10 kΩ, CL = 10 pF

4.5

9.0

12.0

30 65

100

—

Crosstalk Between Any Two Switches

(Figure 12)

fin  Sine Wave Adjust fin Voltage to Obtain 0 dBm at V

IS

fin = 10 kHz, RL = 600 Ω, CL = 50 pF

4.5

9.0

12.0

– 70 – 70 – 70

dB

fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF

4.5

9.0

12.0

– 80 – 80 – 80

THD

Total Harmonic Distortion

(Figure 14)

fin = 1 kHz, RL = 10 kΩ, CL = 50 pF THD = THD

Measured

– THD

Source

VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave

VIS = 11.0 VPP sine wave

4.5

9.0

12.0

0.10

0.06

0.04

%

*Guaranteed limits not tested. Determined by design and verified by qualification.

MC54/74HC4066

High–Speed CMOS Logic Data DL129 — Rev 6

5 MOTOROLA

Figure 1a. Typical On Resistance, VCC = 2.0 V Figure 1b. Typical On Resistance, VCC = 4.5 V

600

500

400

300

200

100

0

2.001.751.501.251.000.750.500.250

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

–55

°

C

25

°

C

125

°

C

R

on

, ON RESISTANCE (OHMS)

120

100

80

60

40

20

0

4.54.03.53.02.52.01.51.00.50

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

R

on

, ON RESISTANCE (OHMS)

125°C

25

°

C

–55°C

80 70 60 50 40 30 20 10

0

6.05.55.04.54.03.53.02.52.01.51.00.50

Figure 1c. Typical On Resistance, VCC = 6.0 V

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

R

on

, ON RESISTANCE (OHMS)

125°C

25°C

–55°C

120

100

80

60

40

20

0

9.08.07.06.05.04.03.02.01.00

Figure 1d. Typical On Resistance, VCC = 9.0 V

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

R

on

, ON RESISTANCE (OHMS)

125°C

25°C

–55°C

80 70 60 50 40 30 20 10

0

1211109.08.07.06.05.04.03.02.01.00

R

on

, ON RESISTANCE (OHMS)

Figure 1e. Typical On Resistance, VCC = 12 V

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 2. On Resistance Test Set–Up

PLOTTER

MINI COMPUTER

PROGRAMMABLE

POWER

SUPPLY

DC ANALYZER

V

CC

+–

ANALOG IN COMMON OUT

GND

DEVICE

UNDER TEST

125°C

25°C

–55°C

MC54/74HC4066

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

6

Figure 3. Maximum Off Channel Leakage Current,

Any One Channel, Test Set–Up

OFF

7

14

V

CC

A

V

CC

GND

V

CC

SELECTED

CONTROL

INPUT

V

IL

Figure 4. Maximum On Channel Leakage Current,

Test Set–Up

ON

14

V

CC

N/C

A

GND

V

CC

7

SELECTED

CONTROL

INPUT

V

IH

Figure 5. Maximum On–Channel Bandwidth

Test Set–Up

ON

14

V

CC

0.1µF

CL*

f

in

dB

METER

*Includes all probe and jig capacitance.

V

OS

7

SELECTED

CONTROL

INPUT

V

CC

Figure 6. Off–Channel Feedthrough Isolation,

Test Set–Up

OFF

7

14

V

CC

0.1µF

CL*

f

in

dB

METER

*Includes all probe and jig capacitance.

V

OS

R

L

V

IS

SELECTED CONTROL INPUT

Figure 7. Feedthrough Noise, ON/OFF Control to

Analog Out, Test Set–Up

14

V

CC

CL*

*Includes all probe and jig capacitance.

OFF/ON

V

CC

GND

Vin

≤

1 MHz

tr = tf = 6 ns

CONTROL

V

CC/2

R

L

I

S

R

L

V

OS

7

SELECTED

CONTROL

INPUT

V

CC/2

V

CC

GND

ANALOG IN

ANALOG OUT

50%

t

PLH

t

PHL

50%

Figure 8. Propagation Delays, Analog In to

Analog Out

MC54/74HC4066

High–Speed CMOS Logic Data DL129 — Rev 6

7 MOTOROLA

POSITION WHEN TESTING t

PLZ

AND t

PZL

Figure 9. Propagation Delay Test Set–Up

ON

14

V

CC

*Includes all probe and jig capacitance.

TEST

POINT

ANALOG OUTANALOG IN

CL*

7

SELECTED

CONTROL

INPUT

V

CC

t

r

t

f

V

CC

GND

HIGH IMPEDANCE

V

OL

V

OH

HIGH IMPEDANCE

CONTROL

ANALOG

OUT

90%

50%

10%

50%

10%

90%

t

PZH

t

PHZ

t

PZL

t

PLZ

Figure 10. Propagation Delay, ON/OFF Control

to Analog Out

ON/OFF

V

CC

TEST

POINT

14

V

CC

1 k

Ω

POSITION WHEN TESTING t

PHZ

AND t

PZH

CL*

1 2

Figure 11. Propagation Delay Test Set–Up

1 2

7

SELECTED CONTROL INPUT

Figure 12. Crosstalk Between Any Two Switches,

Test Set–Up

R

L

ON

14

VCC OR GND

CL*

*Includes all probe and jig capacitance.

OFF

R

L

R

L

V

IS

R

L

CL*

V

OS

f

in

0.1

µ

F

V

CC/2

V

CC/2

7

SELECTED CONTROL INPUT

V

CC/2

Figure 13. Power Dissipation Capacitance

Test Set–Up

14

V

CC

N/C

OFF/ON

A

N/C

7

SELECTED

CONTROL

INPUT

ON/OFF CONTROL

ON

V

CC

0.1 µF

CL*

f

in

R

L

TO

DISTORTION

METER

*Includes all probe and jig capacitance.

V

OS

V

IS

7

SELECTED

CONTROL

INPUT

V

CC

Figure 14. Total Harmonic Distortion, Test Set–Up

*Includes all probe and jig capacitance.

V

CC

V

CC/2

MC54/74HC4066

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

8

0 –10 –20 –30 –40 –50

1.0 2.0 FREQUENCY (kHz)

dBm

–60 –70 –80 –90

FUNDAMENTAL FREQUENCY

DEVICE SOURCE

Figure 15. Plot, Harmonic Distortion

3.0

APPLICATION INFORMATION

The ON/OFF Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog i nputs and outputs to VCC or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked–up by the unused I/O pins.

The maximum analog voltage swings are determined by the supply voltages VCC and GND. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In the example

below, the difference between VCC and GND is twelve volts. Therefore, using the configuration in Figure 16, a maximum analog signal of twelve volts peak–to–peak can be controlled.

When voltage transients above VCC and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended a s shown in Figure 17. T hese diodes should be small signal, fast turn–on types able to absorb the maximum a nticipated c urrent surges during c lipping. An alternate method would be to replace the Dx diodes with MOsorbs ( Motorola high current s urge protectors). MOsorbs are fast turn–on devices ideally suited for precise DC protection with no inherent wear out mechanism.

ANALOG O/I

ON

14

VCC = 12 V

ANALOG I/O

+ 12 V

0 V

+ 12 V

0 V

OTHER CONTROL

INPUTS

(VCC OR GND)

ON

16

V

CC

D

x

D

x

V

CC

D

x

Figure 16. 12 V Application Figure 17. Transient Suppressor Application

7

SELECTED CONTROL INPUT

D

x

OTHER CONTROL

INPUTS

(VCC OR GND)

7

SELECTED CONTROL INPUT

V

CC

MC54/74HC4066

High–Speed CMOS Logic Data DL129 — Rev 6

9 MOTOROLA

+5 V

14

HC4016

CONTROL

INPUTS

7

5

6 14 15

LSTTL/

NMOS

ANALOG SIGNALS

R* R* R* R*

ANALOG

SIGNALS

HCT

BUFFER

R* = 2 TO 10 k

Ω

VDD = 5 V VCC = 5 TO 12 V

ANALOG SIGNALS

1 16 14

HC4016

CONTROL

INPUTS

78

MC14504

13

3 5 7

9 11 14

2 4 6

10

5

6 14 15

CHANNEL 4

CHANNEL 3

CHANNEL 2

CHANNEL 1

1 OF 4

SWITCHES

COMMON I/O

1 2 3 4

CONTROL INPUTS

INPUT

OUTPUT

0.01

µ

F

LF356 OR

EQUIVALENT

a. Using Pull-Up Resistors b. Using HCT Buffer

Figure 18. LSTTL/NMOS to HCMOS Interface

Figure 19. TTL/NMOS–to–CMOS Level Converter

Analog Signal Peak–to–Peak Greater than 5 V

(Also see HC4316)

Figure 20. 4–Input Multiplexer Figure 21. Sample/Hold Amplifier

+

–

1 OF 4

SWITCHES

+5 V

14

HC4016

CONTROL

INPUTS

7

5

6 14 15

LSTTL/ NMOS

ANALOG

SIGNALS

ANALOG

SIGNALS

1 OF 4

SWITCHES

1 OF 4

SWITCHES

1 OF 4

SWITCHES

MC54/74HC4066

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

10

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC DIP PACKAGE

CASE 632–08

ISSUE Y

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

A B C D F G J K L M N

0.785

0.280

0.200

0.020

0.065

0.015

0.170 15

°

0.040

0.750

0.245

0.155

0.015

0.055

0.008

0.125 0

°

0.020

19.94

7.11

5.08

0.50

1.65

0.38

4.31 15

°

1.01

19.05

6.23

3.94

0.39

1.40

0.21

3.18 0

°

0.51

0.100 BSC

0.300 BSC

2.54 BSC

7.62 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMESNION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.

14 8

1 7

-A-

-B-

-T-

SEATING

PLANE

F G

N

K

C

L

M

0.25 (0.010) T A

M

S

0.25 (0.010) T B

M

S

J 14 PL

D 14 PL

N SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

4. ROUNDED CORNERS OPTIONAL.

1 7

14 8

B

A

F

H G D

K

C

N

L

J

M

SEATING PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 19.56 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L 0.300 BSC 7.62 BSC M 0 10 0 10 N 0.015 0.039 0.39 1.01

_ _ _ _

MC54/74HC4066

High–Speed CMOS Logic Data DL129 — Rev 6

11 MOTOROLA

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A B C D

F

G

J K M

P R

8.55

3.80

1.35

0.35

0.40

0.19

0.10 0

°

5.80

0.25

8.75

4.00

1.75

0.49

1.25

0.25

0.25 7

°

6.20

0.50

0.337

0.150

0.054

0.014

0.016

0.008

0.004 0°

0.228

0.010

0.344

0.157

0.068

0.019

0.049

0.009

0.009 7°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

–A–

–B–

P 7 PL

G

C

K

SEATING PLANE

D 14 PL

M

J

R

X 45°

1

7

814

0.25 (0.010) T B A

M

S S

B0.25 (0.010)

M M

F

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948G–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C ––– 1.20 ––– 0.047 D 0.05 0.15 0.002 0.006

F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024

J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.

_ _ _ _

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V

S

T

L

–U–

SEATING PLANE

0.10 (0.004)

–T–

SECTION N–N

DETAIL E

J

J1

K

K1

DETAIL E

F

M

–W–

0.25 (0.010)

8

14

7

1

PIN 1 IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

–V–

14X REFK

N

MC54/74HC4066

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

12

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MC54/74HC4066/D

*MC54/74HC4066/D*

◊

CODELINE

Datasheet MC74HC4066ND, MC74HC4066FL2, MC74HC4066FR1, MC74HC4066FR2, MC74HC4066FEL Datasheet (MOTOROLA)

Specifications and Main Features

Frequently Asked Questions

User Manual