Datasheet MC74HC4060ADTEL, MC74HC4060AF, MC74HC4060ADR2, MC74HC4060AN, MC74HC4060AFEL Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 2

1 Publication Order Number:

MC74HC4060A/D

MC74HC4060A

14-Stage Binary Ripple
Counter With Oscillator

High–Performance Silicon–Gate CMOS

The MC74C4060A is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.

This device consists of 14 master–slave flip–flops and an oscillator
with a frequency that is controlled either by a crystal or by an RC
circuit connected externally. The output of each flip–flop feeds the
next and the frequency at each output is half of that of the preceding
one. The state of the counter advances on the negative–going edge of
the Osc In. The active–high Reset is asynchronous and disables the
oscillator to allow very low power consumption during stand–by
operation.

State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with Osc Out 2 of the
HC4060A.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance With JEDEC Standard No. 7A Requirements

• Chip Complexity: 390 FETs or 97.5 Equivalent Gates

1516 14 13 12 11 10

21 34567

V

CC

9

8

Q10 Q8 Q9 Reset Osc In

Osc

Out 1

Osc

Out 2

Q12 Q13 Q14 Q6 Q5 Q7 Q4

GND

Pinout: 16–Lead Plastic Package (Top View)

FUNCTION TABLE

Clock Reset Output State

X

L
L
H

No Charge

Advance to Next State

All Outputs Are Low

SO–16

D SUFFIX

CASE 751B

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TSSOP–16
DT SUFFIX
CASE 948F

1

16

PDIP–16
N SUFFIX
CASE 648

1

16

1

16

MARKING

DIAGRAMS

1

16

MC74HC4060AN

AWLYYWW

1

16

HC4060A

AWLYWW

A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week

HC40

60A

ALYW

1

16

Device Package Shipping

ORDERING INFORMATION

MC74HC4060AN PDIP–16 2000 / Box
MC74HC4060AD SOIC–16

48 / Rail
MC74HC4060ADR2 SOIC–16 2500 / Reel
MC74HC4060ADT TSSOP–16 96 / Rail
MC74HC4060ADTR2 TSSOP–16

2500 / Reel

LOGIC DIAGRAM

Q4

7

Q5

5

Q6

4

Q7

6

Q8

14

Q9

13

Q10

15

Q12

1

Q13

2

Q14

3

Osc In

11

Reset

12

Pin 16 = V

CC

Pin 8 = GND

Osc Out 1 Osc Out 2

910

MC74HC4060A

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2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎ

Î

750
500
450

Î

Î

mW

T

stg

Storage Temperature Range

– 65 to + 150

_

C

ÎÎ

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

ÎÎÎ

Î

260

Î

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.5*

ÎÎ

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature Range, All Package Types

– 55

ÎÎ

+ 125

_

C

ÎÎ

Î

tr, t

f

ООООООООООООО

Î

Input Rise/Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

Î

Î

0
0
0

ÎÎ

ÎÎ

1000

500
400

Î

Î

ns

*The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested

at 2.0 V by driving Pin 11 with an external clock source.

DC CHARACTERISTICS (Voltages Referenced to GND)

V

Guaranteed Limit

Symbol Parameter Condition

V

CC

V

–55 to 25°C ≤85°C ≤125°C

Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1V or VCC –0.1V

|I

out

| ≤ 20µA

2.0

3.0

4.5

6.0

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1V or VCC – 0.1V

|I

out

| ≤ 20µA

2.0

3.0

4.5

6.0

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

V

V

OH

Minimum High–Level Output
Voltage (Q4–Q10, Q12–Q14)

Vin = VIH or V

IL

|I

out

| ≤ 20µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin =VIH or V

IL

|I

out

| ≤ 2.4mA

|I

out

| ≤ 4.0mA

|I

out

| ≤ 5.2mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

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3

DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol Unit

Guaranteed Limit

V

CC
V

ConditionParameterSymbol Unit≤125°C≤85°C–55 to 25°C

V

CC
V

ConditionParameter

V

OL

Maximum Low–Level Output
Voltage (Q4–Q10, Q12–Q14)

Vin = VIH or V

IL

|I

out

| ≤ 20µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or V

IL|Iout

| ≤ 2.4mA

|I

out

| ≤ 4.0mA

|I

out

| ≤ 5.2mA

3.0

4.5

6.0

0.26

0.26

0.26

0.33

0.33

0.33

0.40

0.40

0.40

V

OH

Minimum High–Level Output
Voltage (Osc Out 1, Osc Out 2)

Vin = VCC or GND
|I

out

| ≤ 20µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin =VCC or GND |I

out

| ≤ 0.7mA

|I

out

| ≤ 1.0mA

|I

out

| ≤ 1.3mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

V

OL

Maximum Low–Level Output
Voltage (Osc Out 1, Osc Out 2)

Vin = VCC or GND
|I

out

| ≤ 20µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin =VCC or GND |I

out

| ≤ 0.7mA

|I

out

| ≤ 1.0mA

|I

out

| ≤ 1.3mA

3.0

4.5

6.0

0.26

0.26

0.26

0.33

0.33

0.33

0.40

0.40

0.40

I

in

Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0µA

6.0 4 40 160 µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

AC CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

V

Guaranteed Limit

Symbol Parameter

V

CC

V

–55 to 25°C ≤85°C ≤125°C

Unit

f

max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

2.0

3.0

4.5

6.0

6.0
10
30
50

9.0
14
28
45

8.0
12
25
40

MHz

t

PLH

,

t

PHL

Maximum Propagation Delay, Osc In to Q4*
(Figures 1 and 4)

2.0

3.0

4.5

6.0

300
180

60
51

375
200

75
64

450
250

90
75

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Osc In to Q14*
(Figures 1 and 4)

2.0

3.0

4.5

6.0

500
350
250
200

750
450
275
220

1000

600
300
250

ns

t

PHL

Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)

2.0

3.0

4.5

6.0

195

75
39
33

245
100

49
42

300
125

61
53

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Qn to Qn+1
(Figures 3 and 4)

2.0

3.0

4.5

6.0

75
60
15
13

95
75
19
16

125

95
24
20

ns

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4

AC CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns) – continued

V

Guaranteed Limit

Symbol Parameter

V

CC

V

–55 to 25°C ≤85°C ≤125°C

Unit

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output
(Figures 1 and 4)

2.0

3.0

4.5

6.0

75
27
15
13

95
32
19
16

110

36
22
19

ns

C

in

Maximum Input Capacitance 10 10 10 pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

* For TA = 25°C and CL = 50 pF , typical propagation delay from Clock to other Q outputs may be calculated with the following equations:

VCC = 2.0 V: tP = [93.7 + 59.3 (n–1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n–1)] ns
VCC = 3.0 V: tP = [61.5+ 34.4 (n–1)] ns VCC = 6.0 V: tP = [24.4 + 12 (n–1)] ns

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Package)*

35

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (Input t

r

= tf = 6 ns)

V

Guaranteed Limit

Symbol Parameter

V

CC

V

–55 to 25°C ≤85°C ≤125°C

Unit

t

rec

Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)

2.0

3.0

4.5

6.0

100

75
20
17

125
100

25
21

150
120

30
25

ns

t

w

Minimum Pulse Width, Clock
(Figure 1)

2.0

3.0

4.5

6.0

75
27
15
13

95
32
19
16

110

36
23
19

ns

t

w

Minimum Pulse Width, Reset
(Figure 2)

2.0

3.0

4.5

6.0

75
27
15
13

95
32
19
16

110

36
23
19

ns

tr, t

f

Maximum Input Rise and Fall Times
(Figure 1)

2.0

3.0

4.5

6.0

1000

800
500
400

1000

800
500
400

1000

800
500
400

ns

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

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5

PIN DESCRIPTIONS

INPUTS
Osc In (Pin 11)

Negative–edge triggering clock input. A high–to–low
transition on this input advances the state of the counter. Osc
In may be driven by an external clock source.

Reset (Pin 12)

Active–high reset. A high level applied to this input
asynchronously resets the counter to its zero state (forcing
all Q outputs low) and disables the oscillator.

OUTPUTS
Q4—Q10, Q12–Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3)

Active–high outputs. Each Qn output divides the Clock
input frequency by 2N. The user should note the Q1, Q2, Q3
and Q11 are not available as outputs.

Osc Out 1, Osc Out 2 (Pins 9, 10)

Oscillator outputs. These pins are used in conjunction
with Osc In and the external components to form an
oscillator. When Osc In is being driven with an external
clock source, Osc Out 1 and Osc Out 2 must be left open
circuited. With the crystal oscillator configuration in Figure
6, Osc Out 2 must be left open circuited.

SWITCHING W AVEFORMS

t

w

t

f

Osc In

Q

V

CC

GND

90%
50%
10%

t

r

t

w

90%

50%

10%

t

PHL

1/f

MAX

t

PLH

t

TLH

t

THL

Reset

V

CC

GND

t

PHL

50%

Figure 1. Figure 2.

Q

V

CC

GND

50%

Osc In 50%

t

rec

50%

Qn

V

CC

GND

50%

Qn+1

CL*

*Includes all probe and jig capacitance

TEST

POINT

DEVICE
UNDER

TEST

OUTPUT

Figure 3. Figure 4. Test Circuit

t

PLH

t

PHL

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6

Figure 5. Expanded Logic Diagram

C

C

R

Osc Out 2

9

Q

Q

C

C

R

Q

Q

C

CQQ

C

CQQ

C

CQQ

C

C

Q

Q4

7

Q5

5

Q12

1

Q13

2

Q14

3

Q6 = Pin 4
Q7 = Pin 6
Q8 = Pin 14
Q9 = Pin 13

Q10 = Pin 15
VCC = Pin 16
GND = Pin 8

Osc Out 1

10

Osc In

11

Reset

12

Figure 6. Oscillator Circuit Using RC Configuration

Reset

12

Osc In 11 Osc Out 1 10 Osc Out 2 9

R

tc

C

tc

R

S

For 2.0V ≤ VCC ≤ 6.0V

10Rtc > RS > 2R

tc

400Hz ≤ f ≤ 400Khz:

f

[

1

3RtcC

tc

(f in Hz, Rtcin ohms, Ctcin farads)

The formula may vary for other frequencies.

Figure 7. Pierce Crystal Oscillator Circuit

Reset

12

Osc In 11 Osc Out 1 10 9 Osc Out 2

R

f

C1 C2

R1

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7

TABLE 1. CRYSTAL OSCILLATOR AMPLIFIER SPECIFICATIONS (T

A

= 25°C; Input = Pin 11, Output = Pin 10)

Type

Positive Reactance (Pierce)

Input Resistance, R

in

60MΩ Minimum

Output Impedance, Z

out

(4.5V Supply) 200Ω (See Text)

Input Capacitance, C

in

5pF Typical

Output Capacitance, C

out

7pF Typical

Series Capacitance, C

a

5pF Typical

Open Loop Voltage Gain with Output at Full Swing, α 3Vdc Supply

4Vdc Supply
5Vdc Supply
6Vdc Supply

5.0 Expected Minimum

4.0 Expected Minimum

3.3 Expected Minimum

3.1 Expected Minimum

PIERCE CRYSTAL OSCILLATOR DESIGN

Figure 8. Equivalent Crystal Networks

R

S

LSC

S

Re Xe 212121

C

O

Value are supplied by crystal manufacturer (parallel resonant crystal).

Figure 9. Series Equivalent Crystal Load Figure 10. Parasitic Capacitances of the Amplifier

Z

load

–jX

Co

–jX

C2

R

–jX

C

–jX

Cs

jX

Ls

R

S

R

load

X

load

NOTE: C = C1 + Cin and R = R1 + R

out

. Co is considered as part of

the load. Ca and Rf typically have minimal effect below 2MHz.

C

in

C

out

C

a

Values are listed in Table 1.

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8

DESIGN PROCEDURES

The following procedure applies for oscillators operating below 2MHz where Z is a resistor R1. Above 2MHz, additional

impedance elements should be considered: C

out

and Ca of the amp, feedback resistor Rf, and amplifier phase shift error from

180°C.

Step 1: Calculate the equivalent series circuit of the crystal at the frequency of oscillation.

Ze+

*

jX

C

o

(Rs)

jX

L

s

*

jX

C

s

)

*

jX

C

o

)

Rs)

jX

L

s

*

jX

C

s

+

Re)

jX

e

Reactance jXe should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency.
The maximum Rs for the crystal should be used in the equation.

Step 2: Determine β, the attenuation, of the feedback network. For a closed-loop gain of 2,Aνβ = 2,β = 2/Aν where Aν is

the gain of the HC4060A amplifier.

Step 3: Determine the manufacturer’s loading capacitance. For example: A manufacturer may specify an external load

capacitance of 32pF at the required frequency.

Step 4: Determine the required Q of the system, and calculate R

load

, For example, a manufacturer specifies a crystal Q of

100,000. In-circuit Q is arbitrarily set at 20% below crystal Q or 80,000. Then R

load

= (2πfoLS/Q) – Rs where Ls and Rs are

crystal parameters.

Step 5: Simultaneously solve, using a computer,

b

+

XC@

X

C2

R@Re)

XC2(Xe*

XC)

( Eq 1 )(with feedback phase shift = 180°)

Xe+

XC2)

XC)

ReX

C2

R

+

X

C

load

( Eq 2 )(where the loading capacitor is an external load, not including Co)

R

load

+

RX

C

o

XC2[(XC)

XC2)(XC)

X

C

o

)*XC(XC)

X

C

o

)

XC2)]

X

2

C2(XC

)

X

C

o

)2)

R2(XC)

X

C

o

)

XC2)

2

( Eq 3 )

Here R = R

out

+ R1. R

out

is amp output resistance, R1 is Z. The C corresponding to XC is given by C = C1 + Cin.

Alternately , pick a value for R1 (i.e, let R1 = RS). Solve Equations 1 and 2 for C1 and C2. Use Equation 3 and the fact that

Q = 2πfoLs/(Rs + R

load

) to find in-circuit Q. If Q is not satisfactory pick another value for R1 and repeat the procedure.

CHOOSING R1

Power is dissipated in the effective series resistance of the
crystal. The drive level specified by the crystal manufacturer
is the maximum stress that a crystal can withstand without
damage or excessive shift in frequency . R1 limits the drive
level.

To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at Osc Out 2 (Pin 9). The frequency
should increase very slightly as the dc supply voltage is
increased. An overdriven crystal will decrease in frequency
or become unstable with an increase in supply voltage. The
operating supply voltage must be reduced or R1 must be
increased in value if the overdriven condition exists. The
user should note that the oscillator start-up time is
proportional to the value of R1.

SELECTING R

f

The feedback resistor, Rf, typically ranges up to 20MΩ. R

f

determines the gain and bandwidth of the amplifier. Proper
bandwidth insures oscillation at the correct frequency plus
roll-off to minimize gain at undesirable frequencies, such as

the first overtone. Rf must be large enough so as to not affect
the phase of the feedback network in an appreciable manner.

ACKNOWLEDGEMENTS AND RECOMMENDED

REFERENCES

The following publications were used in preparing this
data sheet and are hereby acknowledged and recommended
for reading:

Technical Note TN-24, Statek Corp.

Technical Note TN-7, Statek Corp.

D. Babin, “Designing Crystal Oscillators”, Machine
Design, March 7, 1985.

D. Babin, “Guidelines for Crystal Oscillator Design”,
Machine Design, April 25, 1985.

ALSO RECOMMENDED FOR READING:

E. Hafner, “The Piezoelectric Crystal Unit-Definitions
and Method of Measurement”, Proc. IEEE, Vol. 57, No. 2,
Feb., 1969.

D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”, Electro-T echnology, June, 1969.

P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May , 1966.

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9

Clock
Reset

Q4

1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384

Q5
Q6
Q7
Q8

Q9
Q10
Q12
Q13
Q14

Figure 11. Timing Diagram

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10

P ACKAGE DIMENSIONS

PDIP–16

N SUFFIX

CASE 648–08

ISSUE R

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

A
B
C
D

F
G
H
J
K
L
M
S

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50
0°

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74
10°

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295
0°

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305
10°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

B

18

916

F

H

G

D

16 PL

S

C

–T

–

SEATING
PLANE

K

J

M

L

TA0.25 (0.010)

M M

0.25 (0.010) T B A

M

S S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F
G
J
K
M
P
R

9.80

3.80

1.35

0.35

0.40

0.19

0.10
0°

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

0.25
7°

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004
0°

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.009
7°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

1

8

916

–A

–

–B

–

D

16 PL

K

C

G

–T

–

SEATING

PLANE

R X 45°

M

J

F

P 8 PL

0.25 (0.010) B

M M

SOIC–16

D SUFFIX

CASE 751B–05

ISSUE J

MC74HC4060A

http://onsemi.com

11

P ACKAGE DIMENSIONS

TSSOP–16

DT SUFFIX

CASE 948F–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006

F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011

J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.

____

SECTION N–N

SEATING
PLANE

IDENT.

PIN 1

1

8

16

9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

DETAIL E

F

M

L

2X L/2

–U–

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V

S

T

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

N

N

MC74HC4060A

http://onsemi.com

12

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