Datasheet MC74HC393FL2, MC74HC393FR1, MC74HC393FR2, MC74HC393FEL, MC74HC393DTR2 Datasheet (MOTOROLA)



SEMICONDUCTOR TECHNICAL DATA

1

REV 6

 Motorola, Inc. 1995

10/95

 
  

High–Performance Silicon–Gate CMOS

The MC54/74HC393 is identical in pinout to the LS393. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.

This device consists of two independent 4–bit binary ripple counters with
parallel outputs from each counter stage. A ÷ 256 counter can be obtained
by cascading the two binary counters.

Internal flip–flops are triggered by high–to–low transitions of the clock
input. R eset for the counters is asynchronous and active–high. S tate
changes of the Q outputs do not occur simultaneously because of internal
ripple delays. Therefore, decoded output signals are subject to decoding
spikes and should not be used as clocks or as strobes except when gated
with the Clock of the HC393.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 236 FETs or 59 Equivalent Gates

LOGIC DIAGRAM

Q1
Q2
Q3
Q4

CLOCK

RESET

1, 13

2, 12

3, 11
4, 10

5, 9
6, 8

PIN 14 = V

CC

PIN 7 = GND

BINARY

COUNTER



PIN ASSIGNMENT

FUNCTION TABLE

Inputs

Clock Reset Outputs

X H L
H L No Change
L L No Change

L No Change
L Advance to

Next State

11

12

13

14

8

9

105

4

3

2

1

7

6

Q2

b

Q1

b

RESET b

CLOCK b

V

CC

Q4

b

Q3

b

Q2

a

Q1

a

RESET a

CLOCK a

GND

Q3

a

Q4

a

D SUFFIX

SOIC PACKAGE

CASE 751A–03

N SUFFIX

PLASTIC PACKAGE

CASE 646–06

ORDERING INFORMATION

MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD

Ceramic
Plastic
SOIC

1

14

1

14

J SUFFIX

CERAMIC PACKAGE

CASE 632–08

1

14

MC54/74HC393

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

P

D

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

750
500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic or SOIC DIP)

(Ceramic DIP)

260
300

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

0
0
0

1000

500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

0.3

0.9

1.2

0.3

0.9

1.2

0.3

0.9

1.2

V

V

OH

Minimum High–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin = VIH or VIL|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.70

5.20

V

OL

Maximum Low–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or VIL|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

4.5

6.0

0.26

0.26

0.33

0.33

0.40

0.40

I

in

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

6.0

8

80

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC54/74HC393

High–Speed CMOS Logic Data
DL129 — Rev 6

3 MOTOROLA

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

f

max

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 3)

2.0

4.5

6.0

5.4
27
32

4.4
22
26

3.6
18
21

MHz

t

PLH

,

t

PHL

Maximum Propagation Delay, Clock to Q1

(Figures 1 and 3)

2.0

4.5

6.0

120

24
20

150

30
26

180

36
31

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Clock to Q2

(Figures 1 and 3)

2.0

4.5

6.0

190

38
32

240

48
41

285

57
48

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Clock to Q3

(Figures 1 and 3)

2.0

4.5

6.0

240

48
41

300

60
51

360

72
61

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Clock to Q4

(Figures 1 and 3)

2.0

4.5

6.0

290

58
49

365

73
62

435

87
74

ns

t

PHL

Maximum Propagation Delay, Reset to any Q

(Figures 2 and 3)

2.0

4.5

6.0

165

33
28

205

41
35

250

50
43

ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

2.0

4.5

6.0

75
15
13

95
19
16

110

22
19

ns

C

in

Maximum Input Capacitance

—

10

10

10

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Counter)*

40

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (Input t

r

= tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

t

rec

Minimum Recovery Time, Reset Inactive to Clock

(Figure 2)

2.0

4.5

6.0

50
10

9

65
13
11

75
15
13

ns

t

w

Minimum Pulse Width, Clock

(Figure 1)

2.0

4.5

6.0

80
16
14

100

20
17

120

24
20

ns

t

w

Minimum Pulse Width, Reset

(Figure 2)

2.0

4.5

6.0

125

25
21

155

31
26

190

38
32

ns

tr, t

f

Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

1000

500
400

1000

500
400

1000

500
400

ns

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC393

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

4

PIN DESCRIPTIONS

INPUTS
Clock (Pins 1, 13)

Clock input. The internal flip–flops are toggled and the
counter state advances on high–to–low transitions of the
clock input.

CONTROL INPUTS
Reset (Pins 2, 12)

Active–high, asynchronous reset. A separate reset is pro-

vided for each counter. A high at the Reset input prevents
counting and forces all four outputs low.

OUTPUTS

Q1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)

Parallel binary outputs Q4 is the most significant bit.

SWITCHING WAVEFORMS

t

PHL

V

CC

GND

V

CC

GND

50%

50%

50%

t

rec

CLOCK

Q

RESET

Figure 1. Figure 2.

Figure 3. Test Circuit

Q1

Q2

Q3

Q4

CLOCK

RESET

1, 13

2, 12

3, 11

4, 10

5, 9

6, 8

EXPANDED LOGIC DIAGRAM

*Includes all probe and jig capacitance

CL*

TEST

POINT

DEVICE
UNDER

TEST

OUTPUT

CLOCK

Q

90%90%
50%

10%

t

f

t

r

V

CC

GND

t

w

1/f

max

t

PLH

t

PHL

90%

50%

10%

t

TLH

t

THL

C

D Q

t

w

Q

C

D Q

Q

C

D Q

Q

C

D Q

Q

MC54/74HC393

High–Speed CMOS Logic Data
DL129 — Rev 6

5 MOTOROLA

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0

CLOCK

RESET

Q1

Q2

Q3

Q4

TIMING DIAGRAM

COUNT SEQUENCE

Outputs

Count

Q4 Q3 Q2 Q1

0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
8 H L L L

9 H L L H
10 H L H L
11 H L H H
12 H H L L
13 H H L H
14 H H H L
15 H H H H

MC54/74HC393

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

6

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC DIP PACKAGE

CASE 632–08

ISSUE Y

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

A
B
C
D
F
G
J
K
L
M
N

0.785

0.280

0.200

0.020

0.065

0.015

0.170
15

°

0.040

0.750

0.245

0.155

0.015

0.055

0.008

0.125
0

°

0.020

19.94

7.11

5.08

0.50

1.65

0.38

4.31
15

°

1.01

19.05

6.23

3.94

0.39

1.40

0.21

3.18
0

°

0.51

0.100 BSC

0.300 BSC

2.54 BSC

7.62 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMESNION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

14 8

1 7

-A-

-B-

-T-

SEATING

PLANE

F G

N

K

C

L

M

0.25 (0.010) T A

M

S

0.25 (0.010) T B

M

S

J 14 PL

D 14 PL

N SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

4. ROUNDED CORNERS OPTIONAL.

1 7

14 8

B

A

F

H G D

K

C

N

L

J

M

SEATING
PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
M 0 10 0 10
N 0.015 0.039 0.39 1.01

_ _ _ _

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F
G

J
K
M
P
R

8.55

3.80

1.35

0.35

0.40

0.19

0.10
0

°

5.80

0.25

8.75

4.00

1.75

0.49

1.25

0.25

0.25
7

°

6.20

0.50

0.337

0.150

0.054

0.014

0.016

0.008

0.004
0

°

0.228

0.010

0.344

0.157

0.068

0.019

0.049

0.009

0.009
7°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

P 7 PL

G

C

K

SEATING
PLANE

D 14 PL

M

J

R

X 45°

1

7

814

0.25 (0.010) T B A

M

S S

B0.25 (0.010)

M M

F

MC54/74HC393

High–Speed CMOS Logic Data
DL129 — Rev 6

7 MOTOROLA

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MC54/74HC393/D

*MC54/74HC393/D*

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