Datasheet MC74HC374A Datasheet (ON Semiconductor)

MC74HC374A

2

Octal 3−State Non−Inverting D Flip−Flop

High−Performance Silicon−Gate CMOS

The MC74HC374A is identical in pinout to the LS374. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

Data meeting the setup time is clocked to the outputs with the rising edge of the clock. The Output Enable input does not affect the states of

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MARKING

DIAGRAMS

the flip−flops, but when Output Enable is high, the outputs are forced to the high−impedance state; thus, data may be stored even when the outputs are not enabled.

The HC374A is identical in function to the HC574A which has the input pins on the opposite side of the package from the output. This

0

1

PDIP−20

N SUFFIX

CASE 738

20

MC74HC374AN

AWLYYWWG

1

device is similar in function to the HC534A which has inverting outputs.

Features

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

20

SOIC−20

DW SUFFIX

1

CASE 751D

74HC374A

AWLYYWWG

1

• Low Input Current: 1.0 mA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 266 FETs or 66.5 Equivalent Gates

• Pb−Free Packages are Available*

20

TSSOP−20 DT SUFFIX

1

CASE 948E

20

HC

374A

ALYWG

G

1

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

July, 2005 − Rev. 10

1 Publication Order Number:

20

1

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

SOEIAJ−20

F SUFFIX

CASE 967

A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb−Free Package G = Pb−Free Package (Note: Microdot may be in either location)

ORDERING INFORMATION

74HC374A

AWLYWWG

1

MC74HC374A/D

D0

D1

D2

DATA

INPUTS

OUTPUT ENABLE

D3

D4

D5

D6

D7

CLOCK

LOGIC DIAGRAM

3

4

7

8

13

14

17

18

11

1

2

5

6

9

12

15

16

19

MC74HC374A

Q0

Q1

Q2

Q3

NONINVERTING

Q4

Q5

Q6

Q7

OUTPUTS

PIN 20 = V PIN 10 = GND

CC

PIN ASSIGNMENT

OUTPUT

ENABLE

Q0

D0

D1

Q1 5

Q2

D2

D3

Q3

GND

1

2

3

4

6

7

8

9

10

20

V

CC

19

Q7

18

D7

17

D6

16

Q6

15

Q5

14

D5

13

D4

12

Q4

11

CLOCK

FUNCTION TABLE

Inputs Output

Output Enable Clock D Q

LHH LLL L L,H, X No Change

HXXZ

X = don’t care Z = high impedance

ORDERING INFORMATION

Device Package Shipping

MC74HC374AN PDIP−20 18 Units / Box MC74HC374ANG PDIP−20

(Pb−Free) MC74HC374ADW SOIC−20 WIDE 38 Units / Rail MC74HC374ADWG SOIC−20 WIDE

(Pb−Free) MC74HC374ADWR2 SOIC−20 WIDE 1000 Tape & Reel MC74HC374ADWR2G SOIC−20 WIDE

(Pb−Free) MC74HC374ADT TSSOP−20* 75 Units / Rail MC74HC374ADTG TSSOP−20* 75 Units / Rail MC74HC374ADTR2 TSSOP−20* 2500 Tape & Reel MC74HC374ADTR2G TSSOP−20* 2500 Tape & Reel MC74HC374AF SOEIAJ−20 40 Units / Rail MC74HC374AFG SOEIAJ−20

(Pb−Free) MC74HC374AFEL SOEIAJ−20 2000 Tape & Reel MC74HC374AFELG SOEIAJ−20

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

18 Units / Box

38 Units / Rail

1000 Tape & Reel

40 Units / Rail

2000 Tape & Reel

†

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2

MC74HC374A

Î

l

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

MAXIMUM RATINGS

Symbol

V

ÎÎ

DC Supply Voltage (Referenced to GND)

CC

V

DC Input Voltage (Referenced to GND)

in

DC Output Voltage (Referenced to GND)

out

I

DC Input Current, per Pin

in

I

DC Output Current, per Pin

out

I

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air, Plastic DIP†

D

ОООООООООООО

T

Storage Temperature

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

(Plastic DIP, SOIC, SSOP or TSSOP Package)

ОООООООООООО

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

Parameter

SOIC Package†

TSSOP Package†

Value

– 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5

± 20 ± 35 ± 75

750 500

ÎÎÎ

450

– 65 to + 150

260

ÎÎÎ

Unit

mW

Î

V V

V mA mA mA

_C _C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V

should be constrained to the

V

out

range GND v (V

in

or V

) v VCC.

out

in

and

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V

CC

Unused outputs must be left open.

).

RECOMMENDED OPERATING CONDITIONS

Symbol

V

CC

Vin, V

T

A

tr, t

f

ÎÎ

DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND)

out

Operating Temperature, All Package Types Input Rise and Fall Time VCC = 2.0 V

(Figure 1) V

ОООООООООООО

Parameter

CC

V

CC

= 4.5 V = 6.0 V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎ

Symbo

V

ÎÎ

V

ÎÎ

V

OH

ÎÎ

V

OL

ÎÎ

ОООООООО

Parameter

Minimum High−Level Input Voltage

IH

ОООООООО

Maximum Low−Level Input Voltage

IL

ОООООООО

Minimum High−Level Output Voltage

ОООООООО

Maximum Low−Level Output

ОООООООО

Voltage

ОООООООО

ООООООО

Test Conditions

V

= 0.1 V or VCC – 0.1 V

out

ООООООО

|I

| v 20 mA

out

ООООООО

V

= 0.1 V or VCC – 0.1 V

out

ООООООО

|I

| v 20 mA

out

ООООООО

Vin = VIH or V |I

| v 20 mA

out

ООООООО

Vin = VIH or V

ООООООО

Vin = VIH or V

ООООООО

|I

| v 20 mA

out

ООООООО

Vin = VIH or V

ООООООО

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Min

2.0 0

– 55

0 0

Î

0

IL

IL|Iout

|I

out

|I

out

IL

IL|Iout

|I

out

|I

out

3

Max

6.0

V

CC

+ 125

1000

500

Î

400

| v 2.4 mA | v 6.0 mA | v 7.8 mA

Unit

Î

V

2.0

Î

3.0

4.5

Î

6.0

2.0

Î

3.0

4.5

Î

6.0

2.0

4.5

Î

6.0

3.0

Î

4.5

6.0

2.0

Î

4.5

6.0

Î

3.0

4.5

Î

6.0

_C

CC

V V

ns

Guaranteed Limit

– 55 to

25_C

1.50

ÎÎ

2.10

3.15

ÎÎ

4.20

0.50

ÎÎ

0.90

1.35

ÎÎ

1.80

1.90

4.40

ÎÎ

5.90

2.48

ÎÎ

2.98

5.48

0.10

ÎÎ

0.10

ÎÎ

0.26

ÎÎ

0.26

v 85_C

1.50

ÎÎ

2.10

3.15

ÎÎ

4.20

0.50

ÎÎ

0.90

1.35

ÎÎ

1.80

1.90

4.40

ÎÎ

5.90

2.34

ÎÎ

3.84

5.34

0.10

ÎÎ

0.10

ÎÎ

0.33

ÎÎ

0.33

v 125_C

1.50

ÎÎ

2.10

3.15

ÎÎ

4.20

0.50

ÎÎ

0.90

1.35

ÎÎ

1.80

1.90

4.40

ÎÎ

5.90

2.20

ÎÎ

3.70

5.20

0.10

ÎÎ

0.10

ÎÎ

0.40

ÎÎ

0.40

Unit

V

MC74HC374A

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

l

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

V

6.0

CC

– 55 to

25_C

± 0.1 ± 0.5

ÎÎ

4

ÎÎ

v 85_C

± 1.0 ± 5.0

ÎÎ

40

ÎÎ

v 125_C

± 1.0

± 10

ÎÎ

160

ÎÎ

Unit

mA mA

mA

V

Symbol

I

in

I

OZ

ÎÎ

I

CC

ÎÎ

Parameter

Maximum Input Leakage Current Maximum Three−State

ОООООООО

Leakage Current

Maximum Quiescent Supply

ОООООООО

Current (per Package)

Vin = VCC or GND Output in High−Impedance State

V V

Vin = VCC or GND I

Test Conditions

ООООООО

= VIL or V

in

= VCC or GND

out

ООООООО

= 0 mA

out

IH

Î

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book

(DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

= 50 pF, Input tr = tf = 6.0 ns)

L

Guaranteed Limit

ÎÎ

Symbo

f

max

ÎÎ

t

PLH

t

PHL

ÎÎ

t

PLZ

t

PHZ

ÎÎ

t

PLZ

t

PHZ

ÎÎ

t

TLH

t

THL

ÎÎ

C

ÎÎ

C

out

ÎÎ

ОООООООООООООООО

Parameter

Maximum Clock Frequency (50% Duty Cycle)

ОООООООООООООООО

Maximum Propagation Delay, Input Clock to Q

(Figures 1 and 5)

ОООООООООООООООО

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

ОООООООООООООООО

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

ОООООООООООООООО

Maximum Output Transition Time, Any Output

(Figures 1 and 5)

ОООООООООООООООО

Maximum Input Capacitance

in

ОООООООООООООООО

Maximum Three−State Output Capacitance

ОООООООООООООООО

(Output in High−Impedance State)

Î

V

Î

ÎÎÎÎ

V

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

CC

– 55 to

25_C

ÎÎ

6

15

ÎÎ

30 35

ÎÎ

125

80

ÎÎ

25 21

ÎÎ

150 100

ÎÎ

30 26

ÎÎ

150 100

ÎÎ

30 26

ÎÎ

75 27

ÎÎ

15 13

ÎÎ

10 15

v 85_C

ÎÎ

5

10

ÎÎ

24 28

ÎÎ

155 110

ÎÎ

31 26

ÎÎ

190 125

ÎÎ

38 33

ÎÎ

190 125

ÎÎ

38 33

ÎÎ

95 32

ÎÎ

19 16

ÎÎ

10

ÎÎ

15

ÎÎ

v 125_C

ÎÎ

4 8

ÎÎ

20 24

ÎÎ

190 130

ÎÎ

38 32

ÎÎ

225 150

ÎÎ

45 38

ÎÎ

225 150

ÎÎ

45 38

ÎÎ

110

36

ÎÎ

22 19

ÎÎ

10

ÎÎ

15

ÎÎ

Unit

MHz

ns

pF pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

C

Power Dissipation Capacitance (Per Enabled Output)*

PD

*Used to determine the no−load dynamic power consumption: PD = CPD V

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

CC

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4

Typical @ 25°C, VCC = 5.0 V

34

2

f + ICC VCC. For load considerations, see Chapter 2 of the

pF

MC74HC374A

Î

l

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

TIMING REQUIREMENTS (C

ÎÎ

Symbo

t

su

ÎÎ

t

ÎÎ

t

ÎÎ

tr, t

ÎÎ

ООООООООООО

Minimum Setup Time, Data to Clock

ООООООООООО

Minimum Hold Time, Clock to Data

h

ООООООООООО

Minimum Pulse Width, Clock

w

ООООООООООО

Maximum Input Rise and Fall Times

f

ООООООООООО

= 50 pF, Input tr = tf = 6.0 ns)

L

Parameter

SWITCHING WAVEFORMS

Î

Figure

3

Î

3

Î

1

Î

1

Î

V

Volts

Î

2.0

3.0

Î

4.5

6.0

Î

2.0

3.0

Î

4.5

6.0

Î

2.0

3.0

Î

4.5

6.0

Î

2.0

3.0

Î

4.5

6.0

Î

CC

– 55 to 25_C

Min

Max

50 40

Î

10

Î

9

Î

5.0

Î

5.0

Î

60 23

Î

12 10

Î

1000

800

Î

500 400

Î

Guaranteed Limit

v 85_C

Min

Max

65 50

Î

13 11

Î

5.0 5 0

Î

5.0

Î

75 27

Î

15 13

Î

1000

800

Î

500 400

Î

v 125_C

Min

75 60

Î

15 13

Î

5.0

Î

5.0

Î

90 32

Î

18 15

Î

Max

Î

1000

800

Î

500 400

Î

Unit

ns

CLOCK

t

r

90%

50%

10%

t

W

t

90%

Q

50%

10%

1/f

max

PLH

t

TLH

Figure 1.

t

f

V

CC

GND

OUTPUT

ENABLE

50%

t

PZL

t

PLZ

V

CC

GND

HIGH IMPEDANCE

50%

t

PZHtPHZ

10%

90%

V

OL

V

OH

HIGH IMPEDANCE

t

PHL

t

Q

THL

Figure 2.

VALID

V

CC

DATA

50%

GND

CLOCK

t

su

50%

t

h

V

CC

GND

Figure 3.

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5

MC74HC374A

TEST CIRCUITS

OUTPUT

DEVICE UNDER

TEST

*Includes all probe and jig capacitance

Figure 4.

Clock

Output Enable

D0

3

DQ

11

1

D1

C

2

Q0

TEST POINT

4

DQ

C

CL*

Q1

D2

5

7

DQ

TEST POINT

CONNECT TO VCC WHEN TESTING t CONNECT TO GND WHEN TESTING t

PLZ

PHZ

AND t

PZL

PZH

.

DEVICE

UNDER

TEST

OUTPUT

*Includes all probe and jig capacitance

1 kW

CL*

Figure 5.

D3

8

DQ

C

6

Q2

D4

13

DQ

C

9

Q3

D5

14

DQ

C

12

Q4

D6

17

DQ

C

15

Q5

D7

18

DQ

C

Q6

C

16

19

Q7

Figure 6. Expanded Logic Diagram

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6

MC74HC374A

SOIC−20

PACKAGE DIMENSIONS

PDIP−20

N SUFFIX

PLASTIC DIP PACKAGE

CASE 738−03

ISSUE E

−T−

SEATING PLANE

−A−

20

11

B

1

10

C

L

K

M

E

FG

N

D 20 PL

0.25 (0.010) T

J

20 PL

0.25 (0.010) T

M

A

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

DIM MIN MAX MIN MAX

A 25.66 27.171.010 1.070 B 6.10 6.600.240 0.260 C 3.81 4.570.150 0.180 D 0.39 0.550.015 0.022 E F G 2.54 BSC0.100 BSC J 0.21 0.380.008 0.015 K 2.80 3.550.110 0.140 L 7.62 BSC0.300 BSC M 0 15 0 15 N 0.51 1.010.020 0.040

M

B

MILLIMETERSINCHES

1.27 BSC0.050 BSC

1.27 1.770.050 0.070

____

DW SUFFIX

CASE 751D−05

ISSUE G

H10X

M

B

M

0.25

D

20

A

11

q

_

E

1

B20X

M

T

0.25

10

SAS

B

h X 45

A

L

18X

SEATING

e

A1

T

PLANE

C

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS

DIM MIN MAX

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49 C 0.23 0.32 D 12.65 12.95 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90

q 0 7

__

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7

MC74HC374A

TSSOP−20

PACKAGE DIMENSIONS

DT SUFFIX

CASE 948E−02

ISSUE B

20X REFK

S

U0.15 (0.006) T

0.10 (0.004) V

M

S

U

T

S

K

2X

L/2

L

PIN 1 IDENT

110

1120

B

JJ1

−U−

N

S

U0.15 (0.006) T

A

K1

SECTION N−N

0.25 (0.010)

M

−V− N

F

DETAIL E

C

G

H

DETAIL E

0.100 (0.004)

SEATING

−T−

PLANE

D

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.

MILLIMETERS

−W−

DIMAMIN MAX MIN MAX

B 4.30 4.50 0.169 0.177 C 1.20 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

6.60 0.260

6.40 0.252

−−− −−−

____

INCHES

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8

MC74HC374A

SOEIAJ−20

PACKAGE DIMENSIONS

F SUFFIX

CASE 967−01

ISSUE O

20

110

Z

D

e

b

0.13 (0.005)

M

11

H

E

A

0.10 (0.004)

M

VIEW P

A

1

NOTES:

L

E

Q

_

L

DETAIL P

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

1

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD

c

TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

−−− 2.05 −−− 0.081

A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

12.35 12.80 0.486 0.504

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L

1.10 1.50 0.043 0.059

E

M

Q

1

Z

10

0

_

0.70 0.90 0.028 0.035

−−− 0.81 −−− 0.032

INCHES

10

0

_

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MC74HC374A

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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MC74HC373A/D

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Datasheet MC74HC374A Datasheet (ON Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual