Datasheet MC74HC373ADT, MC74HC373ADTEL, MC74HC373ADTR2, MC74HC373AH, MC74HC373AFR1 Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 8

1 Publication Order Number:

MC74HC373A/D

MC74HC373A

Octal 3-State Non-Inverting
Transparent Latch

High–Performance Silicon–Gate CMOS

The MC74HC373A is identical in pinout to the LS373. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.

These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.

The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
high–impedance state. Thus, data may be latched even when the
outputs are not enabled.

The HC373A is identical in function to the HC573A which has the
data inputs on the opposite side of the package from the outputs to
facilitate PC board layout.

The HC373A is the non–inverting version of the HC533A.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 186 FETs or 46.5 Equivalent Gates

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MARKING

DIAGRAMS

1

20

A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week

SOIC WIDE–20

DW SUFFIX
CASE 751D

HC373A

AWLYYWW

PDIP–20
N SUFFIX
CASE 738

1

20

MC74HC373AN

AWLYYWW

TSSOP–20
DT SUFFIX

CASE 948G

1

20

1

20

1

20

Device Package Shipping

ORDERING INFORMATION

MC74HC373AN PDIP–20 1440 / Box
MC74HC373ADW SOIC–WIDE

38 / Rail
MC74HC373ADWR2 SOIC–WIDE 1000 / Reel
MC74HC373ADT TSSOP–20 75 / Rail
MC74HC373ADTR2 TSSOP–20

2500 / Reel

HC

373A

ALYW

1

20

MC74HC373A

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2

LOGIC DIAGRAM

DATA

INPUTS

D0
D1
D2
D3
D4
D5
D6
D7

18

17

14

13

8

7

4

3

1

OUTPUT ENABLE

19

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

16

15

12

9

6

5

2

PIN 20 = V

CC

PIN 10 = GND

NONINVERTING

OUTPUTS

11

LATCH ENABLE

FUNCTION TABLE

Inputs Output

Output Latch
Enable Enable D Q

LHHH
LHLL
L L X No Change
HXXZ

X = Don’t Care
Z = High Impedance

PIN ASSIGNMENT

Q2

D1

D0

Q0

OUTPUT

ENABLE

GND

Q3

D3

D2

Q1 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q6

D6

D7

Q7

V

CC

LATCH
ENABLE

Q4

D4

D5

Q5

Design Criteria

Value

Units

Internal Gate Count*

46.5

ea

Internal Gate Propagation Delay

1.5

ns

Internal Gate Power Dissipation

5.0

µW

Speed Power Product

0.0075

pJ

*Equivalent to a two–input NAND gate.

MC74HC373A

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3

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎ

Î

750
500
450

Î

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

ÎÎ

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC, SSOP or TSSOP Package)

ÎÎÎ

Î

260

Î

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

ÎÎ

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

ÎÎ

+ 125

_

C

ÎÎ

Î

tr, t

f

ООООООООООООО

Î

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

Î

Î

0
0
0

ÎÎ

ÎÎ

1000

500
400

Î

Î

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Î

Symbol

ООООООО

Î

Parameter

ООООООО

Î

Test Conditions

ÎÎ

Î

V

CC
V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

Î

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎ

Î

ÎÎ

Î

V

IH

ООООООО

Î

ООООООО

Î

Minimum High–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

ÎÎÎ

Î

Î

Î

Î

Î

Î

1.5

2.1

3.15

4.2

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

Î

Î

Î

Î

V

ÎÎ

Î

ÎÎ

Î

V

IL

ООООООО

Î

ООООООО

Î

Maximum Low–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.8

ÎÎÎ

Î

Î

Î

Î

Î

Î

0.5

0.9

1.35

1.8

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.8

Î

Î

Î

Î

V

ÎÎ

Î

V

OH

ООООООО

Î

Minimum High–Level Output
Voltage

ООООООО

Î

Vin = V

IH

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

1.9

4.4

5.9

ÎÎÎ

Î

Î

Î

1.9

4.4

5.9

ÎÎ

Î

1.9

4.4

5.9

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = V

IH

|I

out

| v 2.4 mA

|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

2.48

3.98

5.48

ÎÎÎ

Î

Î

Î

2.34

3.84

5.34

ÎÎ

Î

2.2

3.7

5.2

Î

Î

ÎÎ

Î

V

OL

ООООООО

Î

Maximum Low–Level Output
Voltage

ООООООО

Î

Vin = V

IL

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

0.1

0.1

0.1

ÎÎÎ

Î

Î

Î

0.1

0.1

0.1

ÎÎ

Î

0.1

0.1

0.1

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = V

IL

|I

out

| v 2.4 mA

|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

0.26

0.26

0.26

ÎÎÎ

Î

Î

Î

0.33

0.33

0.33

ÎÎ

Î

0.4

0.4

0.4

Î

Î

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HC373A

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4

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Unit

v

125_C

ÎÎÎ

v

85_C

– 55 to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

ÎÎ

Î

I

in

ООООООО

Î

Maximum Input Leakage
Current

ООООООО

Î

Vin = VCC or GND

ÎÎ

Î

6.0

ÎÎ

Î

± 0.1

ÎÎÎ

Î

Î

Î

± 1.0

ÎÎ

Î

± 1.0

Î

Î

µA

ÎÎ

Î

I

OZ

ООООООО

Î

Maximum Three–State
Leakage Current

ООООООО

Î

Output in High–Impedance State
Vin = VIL or V

IH

V

out

= VCC or GND

ÎÎ

Î

6.0

ÎÎ

Î

± 0.5

ÎÎÎ

Î

Î

Î

± 5.0

ÎÎ

Î

± 10

Î

Î

µA

ÎÎ

Î

I

CC

ООООООО

Î

Maximum Quiescent Supply
Current (per Package)

ООООООО

Î

Vin = VCC or GND
I

out

= 0 µA

ÎÎ

Î

6.0

ÎÎ

Î

4.0

ÎÎÎ

Î

Î

Î

40

ÎÎ

Î

160

Î

Î

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

ÎÎÎ

v

85_Cv 125_C

Unit

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

t

PHL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Input D to Q

(Figures 1 and 5)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

125

80
25
21

ÎÎÎ

Î

Î

Î

Î

Î

Î

155
110

31
26

ÎÎ

Î

ÎÎ

Î

190
130

38
32

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

t

PHL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Latch Enable to Q

(Figures 2 and 5)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

140

90
28
24

ÎÎÎ

Î

Î

Î

Î

Î

Î

175
120

35
30

ÎÎ

Î

ÎÎ

Î

210
140

42
36

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PLZ

t

PHZ

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

150
100

30
26

ÎÎÎ

Î

Î

Î

Î

Î

Î

190
125

38
33

ÎÎ

Î

ÎÎ

Î

225
150

45
38

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PZL

t

PZH

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

150
100

30
26

ÎÎÎ

Î

Î

Î

Î

Î

Î

190
125

38
33

ÎÎ

Î

ÎÎ

Î

225
150

45
38

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

TLH

t

THL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Output Transition Time, Any Output

(Figures 1 and 5)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

60
23
12
10

ÎÎÎ

Î

Î

Î

Î

Î

Î

75
27
15
13

ÎÎ

Î

ÎÎ

Î

90
32
18
15

Î

Î

Î

Î

ns

C

in

Maximum Input Capacitance

10

ÎÎÎ

10

10

pF

ÎÎÎ

Î

C

out

ОООООООООООООО

Î

Maximum Three–State Output Capacitance
(Output in High–Impedance State)

ÎÎÎÎÎ

Î

15

ÎÎÎ

Î

Î

Î

15

ÎÎ

Î

15

Î

Î

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Enabled Output)*

36

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

MC74HC373A

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5

TIMING REQUIREMENTS (C

L

= 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

ÎÎ

– 55 to 25_C

v

85_C

v

125_C

ÎÎ

Symbol

Parameter

Fig.

V

CC

Volts

Min

Max

Min

Max

Min

Max

ÎÎ

Unit

ÎÎ

Î

ÎÎ

Î

t

su

ООООООООООО

Î

ООООООООООО

Î

Minimum Setup Time, Input D to Latch Enable

Î

Î

Î

Î

4

Î

Î

Î

Î

2.0

3.0

4.5

6.0

Î

Î

Î

Î

25
20

5.0

5.0

Î

Î

Î

Î

Î

Î

Î

Î

30
25

6.0

6.0

Î

Î

Î

Î

Î

Î

Î

Î

40
30

8.0

7.0

Î

Î

Î

Î

ÎÎ

ÎÎ

ÎÎ

ns

ÎÎ

Î

ÎÎ

Î

t

h

ООООООООООО

Î

ООООООООООО

Î

Minimum Hold Time, Latch Enable to Input D

Î

Î

Î

Î

4

Î

Î

Î

Î

2.0

3.0

4.5

6.0

Î

Î

Î

Î

5.0

5.0

5.0

5.0

Î

Î

Î

Î

Î

Î

Î

Î

5.0

5.0
5 0

5.0

Î

Î

Î

Î

Î

Î

Î

Î

5.0

5.0

5.0

5.0

Î

Î

Î

Î

ÎÎ

ÎÎ

ÎÎ

ns

ÎÎ

Î

ÎÎ

Î

t

w

ООООООООООО

Î

ООООООООООО

Î

Minimum Pulse Width, Latch Enable

Î

Î

Î

Î

2

Î

Î

Î

Î

2.0

3.0

4.5

6.0

Î

Î

Î

Î

60
23
12
10

Î

Î

Î

Î

Î

Î

Î

Î

75
27
15
13

Î

Î

Î

Î

Î

Î

Î

Î

90
32
18
15

Î

Î

Î

Î

ÎÎ

ÎÎ

ÎÎ

ns

ÎÎ

Î

ÎÎ

Î

tr, t

f

ООООООООООО

Î

ООООООООООО

Î

Maximum Input Rise and Fall Times

Î

Î

Î

Î

1

Î

Î

Î

Î

2.0

3.0

4.5

6.0

Î

Î

Î

Î

Î

Î

Î

Î

1000

800
500
400

Î

Î

Î

Î

Î

Î

Î

Î

1000

800
500
400

Î

Î

Î

Î

Î

Î

Î

Î

1000

800
500
400

ÎÎ

ÎÎ

ÎÎ

ns

SWITCHING W AVEFORMS

Figure 1. Figure 2.

V

CC

GND

t

f

t

r

INPUT D

Q

10%

50%

90%

10%

50%

90%

t

TLH

t

PLH

t

PHL

t

THL

V

CC

GND

50%

LATCH ENABLE

t

PLH

t

PHL

Q

t

w

50%

Figure 3. Figure 4.

50%

50%

1.3 V

Q

t

PZL

t

PLZ

t

PZHtPHZ

10%

90%

V

CC

GND
HIGH

IMPEDANCE
V

OL

V

OH

HIGH
IMPEDANCE

Q

OUTPUT
ENABLE

50%

INPUT D

LATCH ENABLE

V

CC

V

CC

GND

GND

VALID

t

h

t

su

50%

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6

TEST CIRCUITS

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 5. Figure 6.

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

CONNECT TO VCC WHEN
TESTING t

PLZ

AND t

PZL

.
CONNECT TO GND WHEN
TESTING t

PHZ

AND t

PZH

.

1 kΩ

EXPANDED LOGIC DIAGRAM

D0

3

DQ

LE

2

Q0

11

1

D1

4

DQ

LE

5

Q1

D2

7

DQ

LE

6

Q2

D3

8

DQ

LE

9

Q3

D4

13

DQ

LE

12

Q4

D5

14

DQ

LE

15

Q5

D6

17

DQ

LE

16

Q6

D7

18

DQ

LE

19

Q7

MC74HC373A

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7

P ACKAGE DIMENSIONS

SO–20

DW SUFFIX

CASE 751D–05

ISSUE F

PDIP–20

N SUFFIX

PLASTIC DIP PACKAGE

CASE 738–03

ISSUE E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

M

L

J

20 PL

M

B

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022

G 2.54 BSC0.100 BSC
J 0.21 0.380.008 0.015
K 2.80 3.550.110 0.140
L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040

____

E

1.27 1.770.050 0.070

1

11

10

20

–A–

SEATING
PLANE

K

N

FG

D

20 PL

–T–

M

A

M

0.25 (0.010) T

E

B

C

F

1.27 BSC0.050 BSC

20

1

11

10

B20X

H10X

C

L

18X

A1

A

SEATING
PLANE

q

h X 45

_

E

D

M

0.25

M

B

M

0.25

SAS

B

T

e

T

B

A

DIM MIN MAX

MILLIMETERS

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90

q

0 7

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.

__

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8

P ACKAGE DIMENSIONS

TSSOP–20
DT SUFFIX

CASE 948E–02

ISSUE A

DIMAMIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B 4.30 4.50 0.169 0.177
C 1.20 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED

0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.

110

1120

PIN 1
IDENT

A

B

–T–

0.100 (0.004)

C

D

G

H

SECTION N–N

K

K1

JJ1

N

N

M

F

–W–

SEATING
PLANE

–V–

–U–

S

U

M

0.10 (0.004) V

S

T

20X REFK

L

L/2

2X

S

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252
––– –––

S

U0.15 (0.006) T

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