Datasheet MC74HC373A Datasheet (ON Semiconductor)

MC74HC373A

2

Octal 3−State Non−Inverting
Transparent Latch

High−Performance Silicon−Gate CMOS

The MC74HC373A is identical in pinout to the LS373. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.

These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.

The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
high−impedance state. Thus, data may be latched even when the

0

1

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20

PDIP−20
N SUFFIX
CASE 738

1

MARKING

DIAGRAMS

MC74HC373AN

AWLYYWWG

outputs are not enabled.

The HC373A is identical in function to the HC573A which has the
data inputs on the opposite side of the package from the outputs to
facilitate PC board layout.

The HC373A is the non−inverting version of the HC533A.

Features

20

20

SOIC−20

DW SUFFIX

1

CASE 751D

74HC373A

AWLYYWWG

1

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 mA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the JEDEC Standard No. 7.0 A Requirements

• Chip Complexity: 186 FETs or 46.5 Equivalent Gates

20

TSSOP−20
DT SUFFIX

1

CASE 948E

20

HC

373A

ALYWG

G

1

• Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2005

July, 2005 − Rev. 12

1 Publication Order Number:

20

20

1

See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.

SOEIAJ−20

F SUFFIX

CASE 967

A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)

ORDERING INFORMATION

74HC373A

AWLYWWG

1

MC74HC373A/D

MC74HC373A

PIN ASSIGNMENT

D0

D1

D2

DATA

INPUTS

LATCH ENABLE

OUTPUT ENABLE

D3

D4

D5

D6

D7

LOGIC DIAGRAM

3

4

7

8

13

14

17

18

11

1

2

Q0

5

Q1

6

Q2

9

Q3

12

Q4

15

Q5

16

Q6

19

Q7

PIN 20 = V
PIN 10 = GND

NONINVERTING

OUTPUTS

CC

OUTPUT

ENABLE

Q0

D0

D1

Q1 5

Q2

D2

D3

Q3

GND

1

2

3

4

6

7

8

9

10

20

V

CC

19

Q7

18

D7

17

D6

16

Q6

15

Q5

14

D5

13

D4

12

Q4

LATCH

11

ENABLE

FUNCTION TABLE

Inputs Output

Output Latch
Enable Enable D Q

LHHH
LHLL
L L X No Change

HXXZ

X = Don’t Ca r e
Z = High Impedance

Design Criteria

Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product

*Equivalent to a two−input NAND gate.

Value

46.5

1.5

5.0

0.0075

Units

ea
ns

mW

pJ

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2

MC74HC373A

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

MAXIMUM RATINGS

Symbol

V

V

ÎÎ

ÎÎ

DC Supply Voltage (Referenced to GND)

CC

V

DC Input Voltage (Referenced to GND)

in

DC Output Voltage (Referenced to GND)

out

I

DC Input Current, per Pin

in

I

DC Output Current, per Pin

out

I

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air, Plastic DIP†

D

ОООООООООООО

ОООООООООООО

T

Storage Temperature

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

(Plastic DIP, SOIC, SSOP or TSSOP Package)

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

V

Vin, V

T

tr, t

ÎÎ

ÎÎ

DC Supply Voltage (Referenced to GND)

CC

DC Input Voltage, Output Voltage (Referenced to GND)

out

Operating Temperature, All Package Types

A

Input Rise and Fall Time VCC = 2.0 V

f

ОООООООООООО

(Figure 1) VCC = 4.5 V

ОООООООООООО

Parameter

Parameter

SOIC Package†

TSSOP Package†

VCC = 6.0 V

Value

– 0.5 to + 7.0
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5

± 20
± 35
± 75

750

ÎÎÎ

500
450

ÎÎÎ

– 65 to + 150

260

Min

2.0

– 55

Î

Î

Max

6.0

0

V

CC

+ 125

0

1000

Î

0

500

0

400

Î

Unit

mA
mA
mA

mW

Î

Î

Unit

V

V
_C
ns

Î

Î

_C
_C

This device contains protection
V
V
V

circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir­cuit. For proper operation, Vin and
V

should be constrained to the

out

range GND v (Vin or V

) v VCC.

out

Unused inputs must always be

tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

ORDERING INFORMATION

Device Package Shipping

MC74HC373AN PDIP−20 18 Units / Box
MC74HC373ANG PDIP−20

18 Units / Box

(Pb−Free)
MC74HC373ADW SOIC−20 WIDE 38 Units / Rail
MC74HC373ADWG SOIC−20 WIDE

38 Units / Rail

(Pb−Free)
MC74HC373ADWR2 SOIC−20 WIDE 1000 Units / Reel
MC74HC373ADWR2G SOIC−20 WIDE

1000 Units / Reel

(Pb−Free)
MC74HC373ADT TSSOP−20* 75 Units / Rail
MC74HC373ADTG TSSOP−20* 75 Units / Rail
MC74HC373ADTR2 TSSOP−20* 2500 Units / Reel
MC74HC373ADTR2G TSSOP−20* 2500 Units / Reel
MC74HC373AF SOEIAJ−20 40 Units / Rail
MC74HC373AFG SOEIAJ−20

40 Units / Rail

(Pb−Free)
MC74HC373AFEL SOEIAJ−20 2000 Units / Reel
MC74HC373AFELG SOEIAJ−20

2000 Units / Reel

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

†

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3

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l

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PD

MC74HC373A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

V

CC

Symbol

V

IH

ÎÎ

ÎÎ

V

IL

ÎÎ

V

OH

ÎÎ

ÎÎ

ÎÎ

ÎÎ

V

OL

ÎÎ

ÎÎ

ÎÎ

I

in

I

OZ

ÎÎ

I

CC

Minimum High−Level Input
Voltage

ООООООО

ООООООО

Maximum Low−Level Input
Voltage

ООООООО

Minimum High−Level Output

ООООООО

Voltage

ООООООО

ООООООО

ООООООО

Maximum Low−Level Output
Voltage

ООООООО

ООООООО

ООООООО

Maximum Input Leakage Current
Maximum Three−State

Leakage Current

ООООООО

Maximum Quiescent Supply
Current (per Package)

Parameter

Test Conditions

V

= VCC – 0.1 V

out

|I

| v 20 mA

out

ООООООО

ООООООО

V

= 0.1 V

out

|I

| v 20 mA

out

ООООООО

Vin = V

IH

ООООООО

|I

| v 20 mA

out

ООООООО

Vin = V

IH

ООООООО

Vin = V

IL

|I

| v 20 mA

out

ООООООО

Vin = V

IL

ООООООО

|I

| v 2.4 mA

out

|I

| v 6.0 mA

out

|I

| v 7.8 mA

out

|I

| v 2.4 mA

out

|I

| v 6.0 mA

out

|I

| v 7.8 mA

out

Vin = VCC or GND
Output in High−Impedance State

Vin = VIL or V
V

= VCC or GND

out

ООООООО

IH

Vin = VCC or GND
I

= 0 mA

out

NOTE:Information on t ypical p arametric v alues can be found i n Chapter 2 of the ON Se m iconductor High−Speed CMOS D ata Book ( DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

Symbo

t

PLH

ÎÎ

t

PHL

ÎÎ

t

PLH

t

PHL

ÎÎ

ÎÎ

t

PLZ

t

PHZ

ÎÎ

t

PZL

ÎÎ

t

PZH

ÎÎ

t

TLH

t

THL

ÎÎ

ÎÎ

C

in

C

out

Maximum Propagation Delay, Input D to Q

ООООООООООООООО

(Figures 1 and 5)

ООООООООООООООО

Maximum Propagation Delay, Latch Enable to Q

(Figures 2 and 5)

ООООООООООООООО

ООООООООООООООО

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

ООООООООООООООО

Maximum Propagation Delay, Output Enable to Q

ООООООООООООООО

(Figures 3 and 6)

ООООООООООООООО

Maximum Output Transition Time, Any Output

(Figures 1 and 5)

ООООООООООООООО

ООООООООООООООО

Maximum Input Capacitance
Maximum Three−State Output Capacitance

Parameter

= 50 pF, Input tr = tf = 6.0 ns)

L

(Output in High−Impedance State)

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

C

*Used to determine the no− load dynamic power consumption: PD = CPD V

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

Power Dissipation Capacitance (Per Enabled Output)*

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CC

4

V

2.0

3.0

Î

4.5

Î

6.0

2.0

3.0

Î

4.5

6.0

2.0

Î

4.5

6.0

Î

3.0

4.5

6.0

Î

2.0

4.5

6.0

Î

3.0

4.5

Î

6.0

6.0

6.0

Î

6.0

V

2.0

Î

3.0

4.5

Î

6.0

2.0

3.0

Î

4.5

Î

6.0

2.0

3.0

Î

4.5

6.0

2.0

Î

3.0

4.5

Î

6.0

2.0

3.0

Î

4.5

Î

6.0

CC

V

– 55 to 25_C

1.5

2.1

ÎÎÎ

3.15

ÎÎÎ

4.2

0.5

0.9

ÎÎÎ

1.35

1.8

1.9

ÎÎÎ

4.4

5.9

ÎÎÎ

2.48

3.98

5.48

ÎÎÎ

0.1

0.1

0.1

ÎÎÎ

0.26

0.26

ÎÎÎ

0.26

± 0.1
± 0.5

ÎÎÎ

4.0

– 55 to 25_C

125

ÎÎÎ

80
25

ÎÎÎ

21

140

90

ÎÎÎ

28

ÎÎÎ

24

150
100

ÎÎÎ

30
26

150

ÎÎÎ

100

30

ÎÎÎ

26
60

23

ÎÎÎ

12

ÎÎÎ

10
10
15

v 85_C

1.5

2.1

ÎÎ

3.15

ÎÎ

4.2

0.5

0.9

ÎÎ

1.35

1.8

1.9

ÎÎ

4.4

5.9

ÎÎ

2.34

3.84

5.34

ÎÎ

0.1

0.1

0.1

ÎÎ

0.33

0.33

ÎÎ

0.33

± 1.0
± 5.0

ÎÎ

40

Guaranteed Limit

v 85_C

155

ÎÎ

110

31

ÎÎ

26

175
120

ÎÎ

35

ÎÎ

30

190
125

ÎÎ

38
33

190

ÎÎ

125

38

ÎÎ

33
75

27

ÎÎ

15

ÎÎ

13
10
15

v 125_C

v 125_C

Typical @ 25°C, VCC = 5.0 V

36

2

f + ICC VCC. For load considerations, see Chapter 2 of t h e

1.5

2.1

ÎÎ

3.15

ÎÎ

4.2

0.5

0.9

ÎÎ

1.35

1.8

1.9

ÎÎ

4.4

5.9

ÎÎ

2.2

3.7

5.2

ÎÎ

0.1

0.1

0.1

ÎÎ

0.4

0.4

ÎÎ

0.4

± 1.0

± 10

ÎÎ

160

190

ÎÎ

130

38

ÎÎ

32

210
140

ÎÎ

42

ÎÎ

36

225
150

ÎÎ

45
38

225

ÎÎ

150

45

ÎÎ

38
90

32

ÎÎ

18

ÎÎ

15
10
15

Unit

V

V

V

V

mA
mA

mA

Unit

ns

ns

ns

ns

ns

pF
pF

pF

MC74HC373A

Î

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TIMING REQUIREMENTS (C

ÎÎ

ÎÎ

Symbo

t

su

ÎÎ

ÎÎ

t

ÎÎ

ÎÎ

t

ÎÎ

ÎÎ

tr, t

ÎÎ

ÎÎ

ООООООООООО

ООООООООООО

Minimum Setup Time, Input D to Latch Enable

ООООООООООО

ООООООООООО

Minimum Hold Time, Latch Enable to Input D

h

ООООООООООО

ООООООООООО

Minimum Pulse Width, Latch Enable

w

ООООООООООО

ООООООООООО

Maximum Input Rise and Fall Times

f

ООООООООООО

ООООООООООО

= 50 pF, Input tr = tf = 6.0 ns)

L

Parameter

SWITCHING WAVEFORMS

Î

Î

Figure

4

Î

Î

4

Î

Î

2

Î

Î

1

Î

Î

Î

V

Volts

Î

2.0

3.0

Î

4.5

6.0

Î

2.0

3.0

Î

4.5

6.0

Î

2.0

3.0

Î

4.5

6.0

Î

2.0

3.0

Î

4.5

6.0

Î

CC

– 55 to 25_C

Min

Max

25
20

Î

Î

5.0

5.0

Î

Î

5.0

5.0

Î

Î

5.0

5.0

Î

Î

60
23

Î

Î

12
10

Î

Î

1000

800

Î

Î

Î

500
400

Î

Guaranteed Limit

v 85_C

Min

Max

30
25

Î

Î

6.0

6.0

Î

Î

5.0

5.0

Î

Î

5 0

5.0

Î

Î

75
27

Î

Î

15
13

Î

Î

1000

800

Î

Î

Î

500
400

Î

v 125_C

Min

40
30

Î

8.0

7.0

Î

5.0

5.0

Î

5.0

5.0

Î

90
32

Î

18
15

Î

Î

Î

Max

Î

Î

Î

Î

Î

Î

1000

800

Î

500
400

Î

Unit

ns

ns

ns

ns

INPUT D

OUTPUT
ENABLE

t

r

90%

50%

10%

t

PLH

Q

t

TLH

50%

10%

90%

t

f

V

CC

LATCH ENABLE

GND

t

PHL

Q

t

THL

50%

50%

t

w

V

CC

GND

t

PLH

t

PHL

Figure 1. Figure 2.

V

CC

50%

t

GND

t

PLZ

PZL

Q

Q

50%

1.3 V

t

PZHtPHZ

10%

90%

HIGH
IMPEDANCE

V

OL

V

OH

HIGH

INPUT D

LATCH ENABLE

50%

VALID

V

CC

t

su

t

h

GND

V

CC

50%

GND

IMPEDANCE

Figure 3. Figure 4.

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5

MC74HC373A

TEST CIRCUITS

TEST POINT

OUTPUT

DEVICE

UNDER

TEST

*Includes all probe and jig capacitance

Figure 5. Figure 6.

D0

3

DQ

11

1

LE

D1

4

DQ

LE

2

Q0

CL*

Q1

D2

7

5

DQ

LE

Q2

D3

8

6

DQ

LE

Q3

DEVICE
UNDER

TEST

D4

13

9

TEST POINT

CL*

DQ

LE

1 kW

D6

17

DQ

15

Q5

OUTPUT

*Includes all probe and jig capacitance

D5

14

DQ

LE

12

Q4

CONNECT TO VCC WHEN
TESTING t
CONNECT TO GND WHEN
TESTING t

LE

Q6

D7

18

16

AND t

PLZ

AND t

PHZ

DQ

LE

PZL

PZH

.

.

19

Q7

Figure 7. EXPANDED LOGIC DIAGRAM

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6

MC74HC373A

SOIC−20

PACKAGE DIMENSIONS

PDIP−20

N SUFFIX

PLASTIC DIP PACKAGE

CASE 738−03

ISSUE E

−T−

SEATING
PLANE

−A−

20

11

B

1

10

C

L

K

M

E

FG

N

D 20 PL

0.25 (0.010) T

J 20 PL

M

M

A

0.25 (0.010) T

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

DIM MIN MAX MIN MAX

A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022

E
F

G 2.54 BSC0.100 BSC

J 0.21 0.380.008 0.015

K 2.80 3.550.110 0.140

L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040

M

B

MILLIMETERSINCHES

1.27 BSC0.050 BSC

1.27 1.770.050 0.070

____

DW SUFFIX

CASE 751D−05

ISSUE G

H10X

M

B

M

0.25

D

20

A

11

q

_

E

1

B20X

M

0.25

T

10

SAS

B

B

h X 45

A

L

18X

SEATING

e

A1

T

PLANE

C

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.

MILLIMETERS

DIM MIN MAX

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90

q 0 7

__

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MC74HC373A

TSSOP−20

PACKAGE DIMENSIONS

DT SUFFIX

CASE 948E−02

ISSUE B

20X REFK

S

U0.15 (0.006) T

0.10 (0.004) V

M

S

U

T

S

K

L/22X

L

PIN 1
IDENT

110

1120

B

JJ1

−U−

N

S

U0.15 (0.006) T

A

K1

SECTION N−N

0.25 (0.010)

M

−V−
N

F

DETAIL E

C

G

H

DETAIL E

0.100 (0.004)

SEATING

−T−

PLANE

D

NOTES:

1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION:
MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.

4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.

5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.

6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.

MILLIMETERS

−W−

DIMAMIN MAX MIN MAX

B 4.30 4.50 0.169 0.177
C 1.20 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

6.60 0.260

6.40 0.252

−−− −−−

____

INCHES

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8

MC74HC373A

SOEIAJ−20

PACKAGE DIMENSIONS

F SUFFIX

CASE 967−01

ISSUE O

20

110

Z

D

e

b

0.13 (0.005)

M

11

H

E

E

A

0.10 (0.004)

M

VIEW P

A

1

NOTES:

L

E

Q

_

L

DETAIL P

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

1

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD

c

TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

−−− 2.05 −−− 0.081

A
A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

12.35 12.80 0.486 0.504

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L

L

1.10 1.50 0.043 0.059

E

M
Q

1

Z

10

0

_

0.70 0.90 0.028 0.035

−−− 0.81 −−− 0.032

INCHES

0 _10

_

_

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9

MC74HC373A

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74HC373A/D

10