Page 1
SEMICONDUCTOR TECHNICAL DATA
$ "
! #
High–Performance Silicon–Gate CMOS
The MC74HC367A is identical in pinout to the LS367. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is arranged into 2–bit and 4–bit sections, each having its own
active–low Output Enable. When either of the enables is high, the affected
buffer outputs are placed into high–impedance states. The HC367A has
noninverting outputs.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 92 FETs or 23 Equivalent Gates
LOGIC DIAGRAM
3
Y0A0
5
Y1
7
Y2
A1
A2
2
4
6
N SUFFIX
PLASTIC PACKAGE
16–LEAD
CASE 648–08
D SUFFIX
SOIC PACKAGE
16–LEAD
CASE 751B–05
DT SUFFIX
TSSOP PACKAGE
16–LEAD
CASE 948F–01
ORDERING INFORMATION
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
PIN ASSIGNMENT
OUTPUT
ENABLE 1
A0
Y0
A1
Y1
A2
Y2
GND
1
2
3
4
6
7
8
16
15
14
13
125
11
10
9
Plastic
SOIC
TSSOP
V
CC
OUTPUT
ENABLE 2
A5
Y5
A4
Y4
A3
Y3
10
A3
12
A4
14
A5
OUTPUT ENABLE 1
OUTPUT ENABLE 2
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
3/97
1
15
Motorola, Inc. 1997
9
Y3
11
Y4
13
Y5
PIN 16 = V
PIN 8 = GND
1
CC
FUNCTION TABLE
Inputs Output
Enable 1,
Enable 2 A Y
LLL
LHH
HXZ
X = don’t care
Z = high impedance
REV 0.1
Page 2
MC74HC367A
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
MAXIMUM RATINGS*
Symbol
V
V
I
I
Î
Î
T
Î
Î
DC Supply Voltage (Referenced to GND)
CC
V
DC Input Voltage (Referenced to GND)
in
DC Output Voltage (Referenced to GND)
out
I
DC Input Current, per Pin
in
DC Output Current, per Pin
out
DC Supply Current, VCC and GND Pins
CC
P
Power Dissipation in Still Air, Plastic DIP†
D
ОООООООООООО
ОООООООООООО
Storage Temperature
stg
ОООООООООООО
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
ОООООООООООО
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Parameter
SOIC Package†
TSSOP Package†
Plastic DIP, SOIC or TSSOP Package
Value
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
± 20
± 25
± 50
750
500
ÎÎÎÎ
450
ÎÎÎÎ
– 65 to + 150
ÎÎÎÎ
ÎÎÎÎ
260
Unit
V
V
V
mA
mA
mA
mW
Î
Î
_
C
Î
_
C
Î
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
should be constrained to the
out
range GND v (Vin or V
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
) v VCC.
out
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
Vin, V
T
A
tr, t
ÎÎ
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
out
Operating Temperature, All Package Types
Input Rise and Fall Time VCC = 2.0 V
f
(Figure 1) VCC = 4.5 V
ОООООООООООО
Parameter
VCC = 6.0 V
Min
2.0
0
– 55
0
0
Î
0
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
ÎÎ
V
IH
ÎÎ
ÎÎ
ÎÎ
V
IL
ÎÎ
ÎÎ
V
OH
ÎÎ
ÎÎ
ÎÎÎОООООООÎООООООО
ООООООО
Minimum High–Level Input
ООООООО
Voltage
ООООООО
ООООООО
Maximum Low–Level Input
ООООООО
Voltage
ООООООО
Minimum High–Level Output
ООООООО
Voltage
ООООООО
Parameter
Test Conditions
ООООООО
V
= VCC – 0.1 V
out
ООООООО
|I
| v 20 µA
out
ООООООО
ООООООО
V
= 0.1 V
out
ООООООО
|I
| v 20 µA
out
ООООООО
Vin = V
IH
ООООООО
|I
| v 20 µA
out
ООООООО
Vin = V
IH
|I
| v 3.6 mA
out
|I
| v 6.0 mA
out
|I
| v 7.8 mA
out
Max
6.0
V
CC
+ 125
1000
500
Î
400
Unit
V
V
_
C
ns
Î
V
CC
V
ÎÎ
2.0
ÎÎ
3.0
ÎÎ
4.5
6.0
ÎÎ
2.0
ÎÎ
3.0
4.5
ÎÎ
6.0
2.0
ÎÎ
4.5
6.0
ÎÎ
3.0
4.5
ÎÎ
6.0
Guaranteed Limit
– 55 to
25_C
ÎÎ
ÎÎ
ÎÎ
3.15
ÎÎ
0.50
ÎÎ
0.90
1.35
ÎÎ
1.5
2.1
4.2
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
1.80
1.9
ÎÎ
ÎÎ
4.4
5.9
ÎÎ
ÎÎ
2.48
3.98
ÎÎ
5.48
ÎÎ
v
85_C
1.5
2.1
3.15
4.2
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.34
3.84
5.34
v
125_C
ÎÎ
1.5
ÎÎ
2.1
ÎÎ
3.15
4.2
ÎÎ
0.50
ÎÎ
0.90
1.35
ÎÎ
1.80
1.9
ÎÎ
4.4
5.9
ÎÎ
2.20
3.70
ÎÎ
5.20
Unit
Î
Î
Î
Î
Î
Î
Î
Î
Î
V
V
V
MOTOROLA High–Speed CMOS Logic Data
2
DL129 — Rev 6
Page 3
MC74HC367A
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
V
CC
Symbol
Symbol
V
OL
ÎÎ
ÎÎ
ÎÎ
I
in
ÎÎ
I
OZ
ÎÎ
ÎÎ
I
CC
ÎÎ
Parameter
Parameter
Maximum Low–Level Output
Voltage
ООООООО
ООООООО
ООООООО
Maximum Input Leakage Current
ООООООО
Maximum Three–State
ООООООО
Leakage Current
ООООООО
Maximum Quiescent Supply
Current (per Package)
ООООООО
Test Conditions
Test Conditions
Vin = V
IL
|I
| v 20 µA
out
ООООООО
Vin = V
IL
ООООООО
ООООООО
Vin = VCC or GND
ООООООО
Output in High–Impedance State
ООООООО
Vin = VIL or V
V
= VCC or GND
ООООООО
out
|I
| v 3.6 mA
out
|I
| v 6.0 mA
out
|I
| v 7.8 mA
out
IH
Vin = VCC or GND
I
= 0 µA
out
ООООООО
CC
2.0
4.5
ÎÎ
6.0
3.0
4.5
ÎÎ
6.0
ÎÎ
6.0
ÎÎ
6.0
ÎÎ
ÎÎ
6.0
ÎÎ
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
– 55 to
V
V
25_C
0.1
0.1
ÎÎ
0.1
0.26
0.26
ÎÎ
0.26
ÎÎ
± 0.1
ÎÎ
± 0.5
ÎÎ
ÎÎ
v
85_C
0.1
0.1
ÎÎ
0.1
0.33
0.33
ÎÎ
0.33
ÎÎ
± 1.0
ÎÎ
± 5.0
ÎÎ
ÎÎ
v
125_C
0.1
0.1
ÎÎ
0.1
0.40
0.40
ÎÎ
0.40
ÎÎ
± 1.0
ÎÎ
± 10
ÎÎ
ÎÎ
160
ÎÎ4ÎÎ40ÎÎ
Unit
Unit
Î
Î
Î
µA
Î
µA
Î
Î
µA
Î
V
AC ELECTRICAL CHARACTERISTICS (C
= 50 pF, Input tr = tf = 6 ns)
L
Guaranteed Limit
Symbol
ÎÎ
t
,
PLH
t
PHL
ÎÎ
ÎÎ
t
,
PLZ
ÎÎ
t
PHZ
ÎÎ
ÎÎ
t
,
PZL
ÎÎ
t
PZH
ÎÎ
t
,
TLH
ÎÎ
t
THL
ÎÎ
C
in
C
out
ÎÎ
ООООООООООООООО
Parameter
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
ООООООООООООООО
ООООООООООООООО
Maximum Propagation Delay, Output Enable to Output Y
ООООООООООООООО
(Figures 2 and 4)
ООООООООООООООО
ООООООООООООООО
Maximum Propagation Delay, Output Enable to Output Y
ООООООООООООООО
(Figures 2 and 4)
ООООООООООООООО
Maximum Output Transition Time, Any Output
ООООООООООООООО
(Figures 1 and 3)
ООООООООООООООО
Maximum Input Capacitance
Maximum Three–State Output Capacitance
ООООООООООООООО
(Output in High–Impedance State)
V
CC
ÎÎ
2.0
3.0
ÎÎ
4.5
6.0
ÎÎ
2.0
ÎÎ
3.0
ÎÎ
4.5
6.0
ÎÎ
2.0
ÎÎ
3.0
4.5
ÎÎ
6.0
2.0
ÎÎ
3.0
4.5
ÎÎ
6.0
—
—
ÎÎ
– 55 to
V
25_C
ÎÎ
120
60
ÎÎ
24
20
ÎÎ
175
ÎÎ
90
ÎÎ
35
30
ÎÎ
190
ÎÎ
95
38
ÎÎ
32
60
ÎÎ
22
12
ÎÎ
10
10
ÎÎ15ÎÎ
v
85_C
ÎÎ
150
75
ÎÎ
30
26
ÎÎ
220
ÎÎ
110
ÎÎ
44
37
ÎÎ
240
ÎÎ
120
48
ÎÎ
21
75
ÎÎ
28
15
ÎÎ
13
10
15
v
125_C
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
180
90
36
31
265
135
53
45
285
150
57
48
90
34
18
15
10
15
Unit
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
pF
pF
Î
ns
ns
ns
ns
C
PD
Power Dissipation Capacitance (Per Buffer)*
*Used to determine the no–load dynamic power consumption: PD = CPD V
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
Typical @ 25°C, VCC = 5.0 V
35
2
f + ICC VCC. For load considerations, see Chapter 2 of the
CC
pF
3 MOTOROLA
Page 4
MC74HC367A
t
r
INPUT A
t
PLH
OUTPUT Y
t
TLH
SWITCHING WAVEFORMS
t
90%
50%
10%
90%
50%
10%
f
t
PHL
t
THL
V
CC
GND
OUTPUT ENABLE
OUTPUT Y
OUTPUT Y
Figure 1. Figure 2.
50%
t
50%
t
50%
TEST CIRCUITS
t
PZL
PLZ
PZHtPHZ
10%
90%
V
CC
GND
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
*Includes all probe and jig capacitance
CL*
Figure 3. Figure 4.
LOGIC DETAIL
TO OTHER
BUFFERS
DEVICE
UNDER
TEST
TEST POINT
1 k
OUTPUT
*Includes all probe and jig capacitance
Ω
CL*
CONNECT TO VCC WHEN
TESTING t
CONNECT TO GND WHEN
TESTING t
ONE OF 6
BUFFERS
V
CC
PLZ
PHZ
AND t
AND t
PZL
PZH
.
.
Y
A
OUTPUT ENABLE
MOTOROLA High–Speed CMOS Logic Data
4
DL129 — Rev 6
Page 5
–A
–
916
B
18
F
C
S
–T
H
G
1
–A
D
16 PL
–
K
M M
916
–B
–
8
G
K
–T
SEATING
–
PLANE
D 16 PL
0.25 (0.010) T B A
M
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
SEATING
PLANE
–
J
TA0.25 (0.010)
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
P 8 PL
0.25 (0.010) B
C
S S
M M
M
L
R X 45°
MC74HC367A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
MIN MINMAX MAX
DIM
A
0.740
B
0.250
C
0.145
D
0.015
F
0.040
G
M
F
J
H
J
0.008
K
0.110
L
0.295
M
0
°
S
0.020
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
18.80
6.35
3.69
0.39
1.02
0.21
2.80
7.50
0.51
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7
6.20
0.50
2.54 BSC
1.27 BSC
0
°
°
19.55
6.85
4.44
0.53
1.77
0.38
3.30
7.74
10
1.01
0.386
0.150
0.054
0.014
0.016
0.008
0.004
0
0.229
0.010
0.770
0.270
0.175
0.021
0.070
0.100 BSC
0.050 BSC
0.015
0.130
0.305
10
°
0.040
MILLIMETERS INCHES
MIN MINMAX MAX
9.80
3.80
1.35
0.35
0.40
1.27 BSC 0.050 BSC
0.19
0.10
0
°
5.80
0.25
°
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7
°
°
0.244
0.019
High–Speed CMOS Logic Data
DL129 — Rev 6
5 MOTOROLA
Page 6
MC74HC367A
ÇÇ
L
0.10 (0.004)
SEATING
–T–
PLANE
U0.15 (0.006) T
PIN 1
IDENT.
U0.15 (0.006) T
D
S
2X L/2
S
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X REFK
T
U
B
–U–
S
H
N
S
J
N
DETAIL E
DETAIL E
J1
0.25 (0.010)
F
K
K1
SECTION N–N
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
INCHESMILLIMETERS
–W–
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
____
0.10 (0.004) V
16
1
M
9
8
A
–V–
C
G
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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MOTOROLA High–Speed CMOS Logic Data
6
◊
MC74HC367A/D
DL129 — Rev 6
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