Page 1
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 6
Motorola, Inc. 1995
10/95
# !# $!"
# "#! %# !
High–Performance Silicon–Gate CMOS
The MC74HC299 is identical in pinout to the LS299. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
The HC299 features a multiplexed parallel input/output data port to
achieve full 8–bit handling in a 20 pin package. Due to the large output drive
capability and the 3–state feature, this device is ideally suited for interface
with bus lines in a bus–oriented system.
Two Mode–Select inputs and two Output Enable inputs a re used to
choose the mode of operation as listed in the Function Table. Synchronous
parallel loading is accomplished by taking both Mode–Select lines, S1 and
S2, high. This places the outputs in the high–impedance state, which permits
data applied to the data port to be clocked into the register. Reading out of
the register can be accomplished when the outputs are enabled. The
active–low asynchronous Reset overrides all other inputs.
• Output Drive Capability: 15 LSTTL Loads for QA through Q
H
10 LSTTL Loads for QA′ and QH′
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
LOGIC DIAGRAM
7
13
6
14
5
15
4
16
8
17
11
18
12
9
1
19
2
3
PG/Q
G
PE/Q
E
PC/Q
C
PA/Q
A
Q
A
′
Q
H
′
PH/Q
H
PF/Q
F
PD/Q
D
PB/Q
B
SERIAL
DATA
INPUTS
SA (SHIFT RIGHT)
SH (SHIFT LEFT)
RESET
S
1
S
2
OE1
OE2
MODE
SELECT
OUTPUT
ENABLES
CLOCK
3–STATE
PARALLEL DATA PORT
(INPUTS/OUTPUTS)
SERIAL DATA
OUTPUTS
PIN 20 = V
CC
PIN 10 = GND
PIN ASSIGNMENT
PC/Q
C
PG/Q
G
OE2
OE1
S1
GND
RESET
Q
A
′
PA/Q
A
PE/QE5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
PH/Q
H
Q
H
′
S
H
S2
V
CC
S
A
CLOCK
PB/Q
B
PD/Q
D
PF/Q
F
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXDW
Plastic
SOIC
1
20
1
20
Page 2
MC74HC299
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 35
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
P
D
Power Dissipation in Still Air Plastic DIP†
SOIC Package†
750
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_C
v
125_C
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
Vin = VIH or VIL|I
out
| v 6.0 mA (P/Q)
|I
out
| v 7.8 mA (P/Q)
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
Vin = VIH or VIL|I
out
| v 4.0 mA (Q′)
|I
out
| v 5.2 mA (Q′)
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL|I
out
| v 6.0 mA (P/Q)
|I
out
| v 7.8 mA (P/Q)
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
Vin = VIH or VIL|I
out
| v 4.0 mA (Q′)
|I
out
| v 5.2 mA (Q′)
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
I
OZ
Maximum Three–State Leakage
Current (QA thru QH)
Output in High–Impedance State
Vin = VIL or V
IH
V
out
= VCC or GND
6.0
± 0.5
± 5.0
± 10
µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
I
out
= 0 µA
6.0
8
80
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.
V
V
Minimum High–Level Output
OH
Voltage
Maximum Low–Level Output
OL
Voltage
V
V
Page 3
MC74HC299
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3 MOTOROLA
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
– 55 to
25_C
v
85_C
v
125_C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
2.0
4.5
6.0
5.0
25
29
4.0
20
24
3.4
17
20
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to QA′ or QH′
(Figures 1 and 5)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to QA thru Q
H
(Figures 1 and 5)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
t
PHL
Maximum Propagation Delay, Reset to QA or Q
H
(Figures 2 and 5)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
t
PHL
Maximum Propagation Delay, Reset to QA′ thru QH′
(Figures 2 and 5)
2.0
4.5
6.0
190
38
32
240
48
41
285
57
48
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, OE1, OE2, S1, or S2 to QA thru Q
H
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, OE1, OE2, S1, or S2 to QA thru Q
H
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
TLH
,
t
THL
Maximum Output Transition Time, QA thru Q
H
(Figures 1 and 5)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
TLH
,
t
THL
Maximum Output Transition Time, QA′ or QH′
(Figures 1 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
in
Maximum Input Capacitance
—
10
10
10
pF
C
out
Maximum Three–State Output Capacitance
(Output in High–Impedance State), QA thru Q
H
—
15
15
15
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
240
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
C
PD
Power Dissipation Capacitance (Per Package)*, Outputs Enabled
pF
Page 4
MC74HC299
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–4
TIMING REQUIREMENTS (Input t
r
= tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
– 55 to
25_C
v
85_C
v
125_C
Unit
t
su
Minimum Setup Time, Mode Select S1 or S2 to Clock
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
su
Minimum Setup Time, Data Inputs SA, SH, PA thru PH to Clock
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
h
Minimum Hold Time, Clock to Mode Select S1 or S2
(Figure 4)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
ns
t
h
Minimum Hold Time, Clock to Data Inputs, SA, SH, PA thru P
H
(Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
t
rec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
t
w
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
w
Minimum Pulse Width, Reset
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tf, t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Page 5
MC74HC299
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5 MOTOROLA
FUNCTION TABLE
Inputs Response
Mode
Select
Output
Enables
Serial
Inputs
Mode
Reset
S2S1OE1† OE2†
Clock
DAD
H
PA/QAPB/QBPC/QCPD/QDPE/QEPF/QFPG/QGPH/QHQA′
QH′
L X L L L X X X L L L L L L L L L L
L L X L L X X X L L L L L L L L L L
L H H X X X X X QA through QH = Z L L
H L H H X D X Shift Right: QA through QH = Z; DA ³ FA; FA ³ FB; etc. D Q
G
H L H X H D X Shift Right: QA through QH = Z; DA ³ FA; FA ³ FB; etc. D Q
G
H L H L L D X Shift Right: DA ³ FA = QA; FA ³ FB = QB; etc. D Q
G
H H L H X X D Shift Left: QA through QH = Z; DH ³ FH; FH ³ FG; etc. QBD
H H L X H X D Shift Left: QA through QH = Z; DH ³ FH; FH ³ FG; etc. QBD
H H L L L X D Shift Left: DH ³ FH = QH; FH ³ FG = QG; etc. QBD
Parallel
Load
H H H X X X X Parallel Load: PN ³ F
N
PAP
H
H L L H X X X X Hold: QA through QH = Z; FN = F
N
PAP
H
H L L X H X X X Hold: QA through QH = Z; FN = F
N
PAP
H
H L L L L X X X Hold: QN = Q
N
PAP
H
Z = high impedance
D = data on serial input
F = flip–flop (see Logic Diagram)
†When one or both output controls are high the eight input/output terminals are disabled to the high impedance state, however, sequential
operation or clearing of the register is not affected.
PIN DESCRIPTIONS
DATA INPUTS
SA (Pin 11)
Serial data input (Shift Right). Data on this input is shifted
into the shift register on the rising edge of Clock when S2 is
low and S1 is high (shift right mode).
SH (Pin 18)
Serial data input (Shift Left). Data on this input is shifted
into the shift register on the rising edge of Clock when S2 is
high and S1 is low (shift left mode).
PA through PH (Pins 7, 13, 6, 14, 5, 15, 4, 16)
Parallel data port inputs. Data on these pins can be parallel loaded into the shift register on the rising edge of Clock
when both S1 and S2 are high. For any other combination of
S1 and S 2, these pins serve as the outputs of the shift
register.
CONTROL INPUTS
Clock (Pin 12)
Clock input. A low–to–high transition on this pin shifts the
data at each stage to the next stage (shift right or left mode)
or loads the data at the parallel data inputs into the shift register (parallel load mode).
OE1, OE2 (Pins 2, 3)
Active–low output enables. When both OE1 and OE2 are
low, the Outputs QA through QH are enabled. When one or
both output enables are high, the outputs are forced to the
high–impedance state; however, sequential operation or
clearing of the register is not affected.
Reset (Pin 9)
Active–low reset. A low on this pin resets all stages of the
register to a low level. The reset operation is asynchronous.
S1, S2 (Pins 1, 19)
Mode select inputs. The levels present at these pins deter-
mine the shift register’s mode of operation:
S1 = S2 = Low. Hold.
S1 = Low, S2 High. Shift left.
S1 = High, S2 Low. Shift right.
S1 = S2 = High. Parallel load.
OUTPUTS
QA′, QH′ (Pins 8, 17)
Serial data outputs. These are the outputs of the first and
last stages of the shift register, respectively. These outputs
are not 3–state outputs and have standard drive capabilities.
QA through QH (Pins 7, 13, 6, 14, 5, 15, 4, 16)
Parallel data port outputs. Shifted data is present at these
pins when OE1 and OE2 are low. For all other combinations
of OE1 and OE2 these outputs are in the high–impedance
state.
Reset
Shift
Right
Shift
Left
Hold
Page 6
MC74HC299
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–6
SWITCHING WAVEFORMS
Figure 6. Test Circuit
Figure 5. Test Circuit
Figure 1. Figure 2.
Figure 3a. Figure 3b.
V
CC
GND
S1 OR S
2
Figure 4.
50%
MODE SELECT
OR DATA
CLOCK
V
CC
V
CC
GND
GND
VALID
t
h
t
su
t
r
t
f
V
CC
GND
t
THL
t
TLH
90%
50%
10%
90%
50%
10%
CLOCK
t
PLH
t
PHL
t
w
50%
t
PHL
V
CC
GND
V
CC
GND
CLOCK
RESET
50%
50%
t
rec
Q
A
′
, QH′
,
QA–Q
H
t
w
1/f
max
50%
50%
50%
OE1 OR OE2
QA–Q
H
t
PZL
t
PLZ
t
PZHtPHZ
10%
90%
V
CC
GND
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
50%
50%
50%
S2 OR S
1
QA–Q
H
t
PZLtPLZ
t
PZHtPHZ
10%
90%
V
CC
GND
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
QA′
, QH′
,
QA–Q
H
50%
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO VCC WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
1 k
Ω
Page 7
MC74HC299
High–Speed CMOS Logic Data
DL129 — Rev 6
3–7 MOTOROLA
S
A
CLOCK
RESET
A
B
C
D
S
1
S
2
OE1
OE2
S
H
18
2
3
1
19
11
12
9
CLK
CLK
R
O
A
B
C
D
SR H
LD SL
8
7
13
6
14
5
15
4
16
17
PG/Q
G
PE/Q
E
PC/Q
C
PA/Q
A
Q
A
′
QH′
PH/Q
H
PF/Q
F
PD/Q
D
PB/Q
B
DETAIL OF DEMULTILPLEXER
SR H
DEMUX O
LD SL
CLK CLK
D
F
A
Q
R
Q
EXPANDED LOGIC DIAGRAM
SR H
DEMUX O
LD SL
CLK CLK
D
F
B
Q
R
Q
SR H
DEMUX O
LD SL
CLK CLK
D
F
C
Q
R
Q
SR H
DEMUX O
LD SL
CLK CLK
D
F
D
Q
R
Q
SR H
DEMUX O
LD SL
CLK CLK
D
F
E
Q
R
Q
SR H
DEMUX O
LD SL
CLK CLK
D
F
F
Q
R
Q
SR H
DEMUX O
LD SL
CLK CLK
D
F
G
Q
R
Q
SR H
DEMUX O
LD SL
CLK CLK
D
F
H
Q
R
Q
Page 8
MC74HC299
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–8
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J
20 PL
M
B
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022
G 2.54 BSC0.100 BSC
J 0.21 0.380.008 0.015
K 2.80 3.550.110 0.140
L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040
_ __ _
E
1.27 1.770.050 0.070
1
11
10
20
–A–
SEATING
PLANE
K
N
FG
D
20 PL
–T–
M
A
M
0.25 (0.010) T
E
B
C
F
1.27 BSC0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
–B–
20
1
11
10
S
A
M
0.010 (0.25) B
S
T
D20X
M
B
M
0.010 (0.25)
P10X
J
F
G
18X
K
C
–T–
SEATING
PLANE
M
R
X 45
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
_ _
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MC74HC299/D
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