Datasheet MC74HC280D Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA

1

REV 6

 Motorola, Inc. 1995

10/95

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 

High–Performance Silicon–Gate CMOS

The MC74HC280 is identical in pinout to the LS280. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.

This circuit consists of 9 data–bit inputs (A through I) and 2 outputs (Even
Parity and Odd Parity) to allow both odd and even parity applications. Words
greater than 9–bits can be accommodated by cascading other HC280
devices.

This device can be used in systems utilizing the LS180 parity generator/
checker. A lthough t he H C280 does n ot h ave expander inputs, t he
corresponding function is provided by an input at pin 4 and the absence of
any connection at pin 3. This permits the HC280 to be substituted for the
LS180 to produce a similar function, even if the HC280s are mixed with
existing LS180s. NOTE: Pullup resistors must be used on the LS180 outputs
to interface with the HC280.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 226 FETs or 56.5 Equivalent Gates

FUNCTION TABLE

Outputs

Number of Inputs A through

I That are High

Even

Parity

Odd

Parity

0, 2, 4, 6, 8 H L
1, 3, 5, 7, 9 L H



PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

C

D

E

F

V

CC

A

B

I

NC

H

G

GND

ODD PARITY

EVEN PARITY

NC = NO CONNECTION

D SUFFIX

SOIC PACKAGE

CASE 751A–03

N SUFFIX

PLASTIC PACKAGE

CASE 646–06

1

14

1

14

ORDERING INFORMATION

MC74HCXXXN
MC74HCXXXD

Plastic
SOIC

LOGIC DIAGRAM

A
B
C
D
E
F
G
H

I

8

9
10
11
12
13

1

2

4

5
6

EVEN PARITY
ODD PARITY

PARITY

OUTPUTS

9–BIT
DATA–
WORD

INPUTS

VCC = PIN 14
GND = PIN 7
NO CONNECTION = PIN 3

MC74HC280

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

P

D

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

750
500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

0
0
0

1000

500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

0.3

0.9

1.2

0.3

0.9

1.2

0.3

0.9

1.2

V

V

OH

Minimum High–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin = VIH or VIL|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.70

5.20

V

OL

Maximum Low–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or VIL|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

4.5

6.0

0.26

0.26

0.33

0.33

0.40

0.40

I

in

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

6.0

8

80

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HC280

High–Speed CMOS Logic Data
DL129 — Rev 6

3 MOTOROLA

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

t

PLH

,

t

PHL

Maximum Propagation Delay, Data Inputs to Parity Outputs

(Figures 1 and 2)

2.0

4.5

6.0

205

41
35

255

51
43

310

62
53

ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output

(Figures 1 and 2)

2.0

4.5

6.0

75
15
13

95
19
16

110

22
19

ns

C

in

Maximum Input Capacitance

—

10

10

10

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Package)*

60

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

PIN DESCRIPTIONS

INPUTS
A, B, C, D, E, F, G, H, I (Pins 8–13, 1, 2, 4)

Nine–bit data–word inputs. The data word placed on these

pins is checked for even or odd parity.

OUTPUTS
Even Parity (Pin 5)

Even–parity output. This pin goes high if the data word has

even parity and low if the data word has odd parity.

Odd Parity (Pin 6)

Odd–parity output. This pin goes high if the data word has

odd parity and low if the data word has even parity.

Figure 1. Switching Waveforms Figure 2. Test Circuit

PARITY OUTPUT

t

PHL

t

THL

t

TLH

t

PLH

GND

V

CC

t

f

t

r

90%

50%

10%

10%

50%

90%

DATA INPUT

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

MC74HC280

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

4

A

8

ODD

PARITY

PIN 14 = V

PIN 7 = GND

PIN 3 = NC

CC

EXPANDED LOGIC DIAGRAM

B

C

D

E

F

G

H

I

9

10

11

12

13

1

2

4

6

5

EVEN

PARITY

MC74HC280

High–Speed CMOS Logic Data
DL129 — Rev 6

5 MOTOROLA

A
B
C
D
E

F
G
H

I

8
9

10

11
12
13

1
2
4

5

6

HC280

9–BIT

DATA–WORD

INPUT

EVEN PARITY

ODD PARITY

PARITY
OUTPUTS

TYPICAL APPLICATIONS

CASCADED 17–BIT ODD/EVEN PARITY

GENERATOR/CHECKER

CASCADED 33–BIT ODD/EVEN PARITY

GENERATOR/CHECKER

A
B

C
D
E

F
G
H

I

8
9

10

11
12
13

1
2
4

5

6

HC280

8–BIT

DATA–WORD

INPUT

EVEN PARITY

ODD PARITY

A
B
C
D
E

F
G
H

I

8

9
10
11
12
13

1

2

4

5

6

HC280

9–BIT

DATA–WORD

INPUT

EVEN PARITY

ODD PARITY

A
B

C
D
E

F
G
H

I

8

9
10
11
12
13

1

2

4

5

6

HC280

8–BIT

DATA–WORD

INPUT

EVEN PARITY

ODD PARITY

A
B

C
D
E

F
G
H

I

8

9
10
11
12
13

1

2

4

5

6

HC280

8–BIT

DATA–WORD

INPUT

EVEN PARITY

ODD PARITY

PARITY
OUTPUTS

A
B

C
D
E

F
G
H

I

8

9
10
11
12
13

1

2

4

5

6

HC280

8–BIT

DATA–WORD

INPUT

EVEN PARITY

ODD PARITY

MC74HC280

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

6

OUTLINE DIMENSIONS

N SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

4. ROUNDED CORNERS OPTIONAL.

1 7

14 8

B

A
F

H G D

K

C

N

L

J

M

SEATING
PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53

F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41

J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43

L 0.300 BSC 7.62 BSC
M 0 10 0 10
N 0.015 0.039 0.39 1.01

_ _ _ _

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F
G
J
K
M
P
R

8.55

3.80

1.35

0.35

0.40

0.19

0.10
0

°

5.80

0.25

8.75

4.00

1.75

0.49

1.25

0.25

0.25
7

°

6.20

0.50

0.337

0.150

0.054

0.014

0.016

0.008

0.004
0

°

0.228

0.010

0.344

0.157

0.068

0.019

0.049

0.009

0.009
7

°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

P 7 PL

G

C

K

SEATING
PLANE

D 14 PL

M

J

R

X 45°

1

7

814

0.25 (0.010) T B A

M

S S

B0.25 (0.010)

M M

F

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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MC74HC280/D

*MC74HC280/D*

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