Page 1
MC74HC273A
LOGIC DIAGRAM
Octal D Flip-Flop with
Common Clock and Reset
High−Performance Silicon−Gate CMOS
The MC74HC273A is identical in pinout to the LS273. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of eight D flip−flops with common Clock and
Reset inputs. Each flip−flop is loaded with a low−to−high transition of
the Clock input. Reset is asynchronous and active low.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
• Chip Complexity: 264 FETs or 66 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
3
D0
4
D1
7
D2
DATA
INPUTS
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
*Equivalent to a two−input NAND gate.
8
D3
13
D4
14
D5
17
D6
18
D7
11
CLOCK
1
RESET
Design Criteria
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
PIN 20 = V
PIN 10 = GND
Value
66
1.5
5.0
.0075
NONINVERTING
OUTPUTS
CC
Units
ea
ns
mW
pJ
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SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
RESET
Q0
D0
D1
Q1 5
Q2
D2
D3
Q3
GND
1
2
3
4
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CLOCK
MARKING DIAGRAMS
20
HC273A
AWLYYWWG
1
SOIC−20 TSSOP−20
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
20
HC
273A
ALYWG
G
1
FUNCTION TABLE
Inputs Output
Reset Clock D Q
LXX L
HHH
HLL
H L X No Change
H X No Change
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 17
1 Publication Order Number:
MC74HC273A/D
Page 2
MC74HC273A
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
CC
V
DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V
in
DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V
out
I
DC Input Current, per Pin ±20 mA
in
I
DC Output Current, per Pin ±25 mA
out
I
DC Supply Current, VCC and GND Pins ±50 mA
CC
P
Power Dissipation in Still Air, SOIC Package†
D
TSSOP Package†
T
Storage Temperature –65 to +150 °C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
SOIC or TSSOP Package
500
450
260
mW
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/°C from 65° to 125°C
TSSOP Package: −6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
Vin, V
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
CC
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
out
T
Operating Temperature, All Package Types –55 +125 °C
A
tr, tfInput Rise and Fall Time VCC = 2.0 V
(Figure 1) V
V
= 4.5 V
CC
= 6.0 V
CC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
V
CC
Symbol Parameter Test Conditions
V
Minimum High−Level Input Voltage V
IH
V
Maximum Low−Level Input Voltage V
IL
V
Minimum High−Level Output
OH
Voltage
V
Maximum Low−Level Output
OL
Voltage
= VCC – 0.1 V
out
|I
| v 20 mA
out
= 0.1 V
out
|I
| v 20 mA
out
Vin = V
IH
|I
| v 20 mA
out
Vin = V
IH
Vin = V
IL
|I
| v 20 mA
out
Vin = V
IL
|I
| v 2.4 mA
out
| v 6.0 mA
|I
out
|I
| v 7.8 mA
out
|I
| v 2.4 mA
out
| v 6.0 mA
|I
out
|I
| v 7.8 mA
out
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, V
V
should be constrained to the
out
range GND v (V
in
or V
out
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
Unused outputs must be left open.
CC
0
0
0
1000
500
400
Guaranteed Limit
–55 to
25°C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
v 85°C v 125°C Unit
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
and
in
) v VCC.
CC
V
ns
).
V
V
V
V
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2
Page 3
MC74HC273A
l
l
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
–55 to
25°C
V
Symbol Unitv 125°Cv 85°C
I
Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0
in
I
Maximum Quiescent Supply
CC
Current (per Package)
Vin = VCC or GND
I
= 0 mA
out
Test ConditionsParameter
6.0 4.0 40 160
mA
mA
AC ELECTRICAL CHARACTERISTICS (C
Symbo
f
Maximum Clock Frequency (50% Duty Cycle)
max
= 50 pF, Input tr = tf = 6.0 ns)
L
Parameter
(Figures 1 and 4)
t
t
t
Maximum Propagation Delay, Clock to Q
PLH
PHL
PHL
(Figures 1 and 4)
Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)
t
t
C
Maximum Output Transition Time, Any Output
TLH
THL
C
in
PD
(Figures 1 and 4)
Maximum Input Capacitance 10 10 10 pF
Power Dissipation Capacitance (Per Enabled Output)*
*Used to determine the no−load dynamic power consumption: PD = CPD V
2
f + ICC VCC.
CC
V
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
–55 to
CC
25°C
6.0
15
30
35
145
90
29
25
145
90
29
25
75
27
15
13
Typical @ 25°C, VCC = 5.0 V
v 85°C v 125°C
5.0
10
24
28
180
120
36
31
180
120
36
31
95
32
19
16
4.0
8.0
20
24
220
140
44
38
220
140
44
38
110
36
22
19
48
Unit
MHz
ns
ns
ns
pF
TIMING REQUIREMENTS (C
Symbo
t
su
t
h
t
rec
t
w
Minimum Setup Time, Data to Clock 3 2.0
Minimum Hold Time, Clock to Data 3 2.0
Minimum Recovery Time, Reset Inactive to
Clock
Minimum Pulse Width, Clock 1 2.0
Parameter Figure
= 50 pF, Input tr = tf = 6.0 ns)
L
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V
CC
Volts
3.0
4.5
6.0
3.0
4.5
6.0
2 2.0
3.0
4.5
6.0
3.0
4.5
6.0
3
Guaranteed Limit
–55 to 25°C v 85°C v 125°C
Min Max Min Max Min Max
60
23
12
10
3.0
3.0
3.0
3.0
5.0
5.0
5.0
5.0
60
23
12
10
75
27
15
13
3.0
3.0
3.0
3.0
5.0
5.0
5.0
5.0
75
27
15
13
90
32
18
15
3.0
3.0
3.0
3.0
5.0
5.0
5.0
5.0
90
32
18
15
Unit
ns
ns
ns
ns
Page 4
MC74HC273A
TIMING REQUIREMENTS (C
Symbol Unit
t
Minimum Pulse Width, Reset 2 2.0
w
tr, tfMaximum Input Rise and Fall Times 1 2.0
= 50 pF, Input tr = tf = 6.0 ns)
L
V
CC
FigureParameter
Volts
3.0
4.5
6.0
3.0
4.5
6.0
60
23
12
10
1000
800
500
400
75
27
15
13
1000
800
500
400
MaxMinMaxMinMaxMin
90
32
18
15
1000
800
500
400
ns
ns
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4
Page 5
CLOCK
MC74HC273A
SWITCHING WAVEFORMS
t
50%
10%
90%
t
r
t
w
t
PLH
t
f
V
CC
RESET
GND
1/f
max
t
PHL
Q
90%
Q
50%
10%
t
TLH
t
THL
CLOCK
50%
w
50%
t
PHL
V
CC
GND
t
rec
50%
V
CC
GND
DATA
CLOCK
50%
DEVICE
UNDER
TEST
Figure 1.
VALID
t
su
Figure 3.
OUTPUT
t
h
50%
TEST POINT
CL*
V
CC
GND
V
CC
GND
DATA
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7
Figure 2.
C
3
4
7
8
13
14
17
18
Q
D
R
C
Q
D
R
C
Q
D
R
C
Q
D
R
C
Q
D
R
C
Q
D
R
C
Q
D
R
C
Q
D
R
11
2
Q0
5
Q1
6
Q2
9
Q3
NONINVERTING
OUTPUTS
12
Q4
15
Q5
16
Q6
19
Q7
*Includes all probe and jig capacitance
Figure 4. Test Circuit
1
Figure 5. Expanded Logic Diagram
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5
Page 6
MC74HC273A
ORDERING INFORMATION
Device Package Shipping
MC74HC273ADWG SOIC−20 WB
(Pb−Free)
MC74HC273ADWR2G SOIC−20 WB
(Pb−Free)
NLV74HC273ADWR2G* SOIC−20 WB
(Pb−Free)
MC74HC273ADTG TSSOP−20
(Pb−Free)
MC74HC273ADTR2G TSSOP−20
(Pb−Free)
NLV74HC273ADTR2G* TSSOP−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
38 Units / Rail
1000 / Tape & Reel
1000 / Tape & Reel
75 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
†
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6
Page 7
MC74HC273A
TSSOP−20
PACKAGE DIMENSIONS
DT SUFFIX
CASE 948E−02
ISSUE C
20X REFK
S
U0.15 (0.006) T
2X
L/2
L
PIN 1
IDENT
110
0.10 (0.004) V
M
S
U
T
1120
S
JJ1
B
−U−
N
K
K1
SECTION N−N
0.25 (0.010)
M
S
U0.15 (0.006) T
A
−V−
N
F
DETAIL E
C
G
H
DETAIL E
0.100 (0.004)
−T−
SEATING
PLANE
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
MILLIMETERS
−W−
DIMAMIN MAX MIN MAX
B 4.30 4.50 0.169 0.177
C 1.20 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
6.60 0.260
6.40 0.252
--- ---
____
INCHES
SOLDERING FOOTPRINT*
7.06
1
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
0.65
PITCH
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7
Page 8
MC74HC273A
SOIC−20
T
P
al
PACKAGE DIMENSIONS
DW SUFFIX
CASE 751D−05
ISSUE G
H10X
M
B
M
0.25
D
20
A
11
q
_
E
1
B20X
M
T
0.25
10
SAS
B
B
h X 45
A
L
18X
SEATING
e
A1
PLANE
C
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
MILLIMETERS
DIM MIN MAX
A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90
q 0 7
__
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MC74HC273A/D
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