Page 1
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
"! ! !
"!$ #!
!! "!"!
High–Performance Silicon–Gate CMOS
The MC54/74HC251 is identical in pinout to the LS251. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device selects one of the eight binary Data Inputs, as determined by
the Address Inputs. The Output Enable pin must be a low level for the
selected data to appear at the outputs. If Output Enable is high, both the Y
and the Y
outputs are in the high–impedance state. This 3–state feature
allows the HC251 to be used in bus–oriented systems.
The HC251 is similar i n function t o the HC151 which does not have
3–state outputs.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 134 FETs or 33.5 Equivalent Gates
LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
OUTPUT ENABLE
Y
Y
DATA
OUTPUTS
DATA
INPUTS
ADDRESS
INPUTS
5
6
4
3
2
1
15
14
13
12
11
10
9
7
PIN 16 = V
CC
PIN 8 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Outputs
Output
A2 A1 A0 Enable Y Y
X X X H Z Z
L L L L D0 D0
L L H L D1 D1
L H L L D2 D2
L H H L D3 D3
H L L L D4 D4
H L H L D5 D5
H H L L D6 D6
H H H L D7 D7
Z = high impedance
D0, D1, …, D7 = the level of the respective
D input.
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
D7
D6
D5
D4
V
CC
A2
A1
A0
D0
D1
D2
D3
GND
OUTPUT
ENABLE
Y
Y
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
1
16
1
16
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
Page 2
MC54/74HC251
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 25
mA
I
out
DC Output Current, per Pin
± 50
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
P
D
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
OH
Minimum High–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
V
OL
Maximum Low–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
I
OZ
Maximum Three–State
Leakage Current
Output in High–Impedance State
Vin = VIL or V
IH
V
out
= VCC or GND
6.0
± 0.5
± 5.0
± 10
µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
I
out
= 0 µA
6.0
8
80
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Page 3
MC54/74HC251
High–Speed CMOS Logic Data
DL129 — Rev 6
3 MOTOROLA
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Input D to Output Y or Y
(Figures 1, 2 and 5)
2.0
4.5
6.0
185
37
31
230
46
39
280
56
48
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A to Output Y or Y
(Figures 3 and 5)
2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
2.0
4.5
6.0
195
39
33
245
49
42
295
59
50
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
in
Maximum Input Capacitance
—
10
10
10
pF
C
out
Maximum Three–State Output Capacitance
(Output in High–Impedance
State)
—
15
15
15
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
36
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS
D0, D1, …, D7 (Pins 4, 3, 2, 1, 15, 14, 13, 12)
Data inputs. Data on one of these eight binary inputs may
be selected to appear on the output.
CONTROL INPUTS
A0, A1, A2 (Pins 11, 10, 9)
Address inputs. The data on these pins are the binary ad-
dress of the selected input (see the Function Table).
Output Enable (Pin 7)
Output Enable. This input pin must be at a low level for the
selected data to appear at the outputs. If the Output Enable
pin is high, both the Y and Y
outputs are taken to the high–
impedance state.
OUTPUTS
Y, Y
(Pins 5, 6)
Data outputs. The selected data is presented at these pins
in both true (Y output) and complemented (Y
output) forms.
Page 4
MC54/74HC251
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
SWITCHING WAVEFORMS
Figure 1. Figure 2.
Figure 3.
V
CC
GND
t
f
t
r
INPUT D
OUTPUT Y
10%
50%
90%
10%
50%
90%
t
TLH
t
PLH
t
PHL
t
THL
t
r
t
f
V
CC
GND
INPUT D
OUTPUT Y
t
PHL
t
PLH
t
TLH
t
THL
10%
50%
90%
10%
50%
90%
V
CC
GND
50%
INPUT A
t
PLH
t
PHL
50%
OUTPUT
Y OR Y
Figure 4.
VALIDVALID
OUTPUT
ENABLE
Y OR Y
Y OR Y
50%
50%
50%
90%
10%
t
PZL
t
PLZ
t
PZHtPHZ
V
CC
GND
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
TEST CIRCUITS
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 5.
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 6.
CONNECT TO VCC WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
1 k
Ω
Page 5
MC54/74HC251
High–Speed CMOS Logic Data
DL129 — Rev 6
5 MOTOROLA
Y
Y
5
6
D0
D1
D2
D3
D4
D5
D6
D7
A
B
C
4
3
2
1
15
14
13
12
11
10
9
7
DATA
INPUTS
EXPANDED LOGIC DIAGRAM
DATA
OUTPUTS
OUTPUT
ENABLE
Page 6
MC54/74HC251
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
6
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
19.05
6.10
—
0.39
1.40
0.21
3.18
19.93
7.49
5.08
0.50
1.65
0.38
4.31
0
°
0.51
15
°
1.01
1.27 BSC
2.54 BSC
7.62 BSC
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
0.750
0.240
—
0.015
0.055
0.008
0.125
0.785
0.295
0.200
0.020
0.065
0.015
0.170
0.050 BSC
0.100 BSC
0.300 BSC
A
B
C
D
E
F
G
J
K
L
M
N
0
°
0.020
15
°
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
1 8
916
–A
–
–B
–
C
K
N
G
E
F
D 16 PL
–T
–
SEATING
PLANE
M
L
J 16 PL
0.25 (0.010) T A
M
S
0.25 (0.010) T B
M
S
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
M
S
18.80
6.35
3.69
0.39
1.02
0.21
2.80
7.50
0
°
0.51
19.55
6.85
4.44
0.53
1.77
0.38
3.30
7.74
10
°
1.01
0.740
0.250
0.145
0.015
0.040
0.008
0.110
0.295
0
°
0.020
0.770
0.270
0.175
0.021
0.070
0.015
0.130
0.305
10
°
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
2.54 BSC
1.27 BSC
0.100 BSC
0.050 BSC
–A
–
B
1 8
916
F
H
G
D
16 PL
S
C
–T
–
SEATING
PLANE
K
J
M
L
T A0.25 (0.010)
M M
0.25 (0.010) T B A
M
S S
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
9.80
3.80
1.35
0.35
0.40
0.19
0.10
0
°
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7
°
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004
0
°
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7
°
0.244
0.019
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
916
–A
–
–B
–
D 16 PL
K
C
G
–T
–
SEATING
PLANE
R X 45°
M
J
F
P 8 PL
0.25 (0.010) B
M M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
Page 7
MC54/74HC251
High–Speed CMOS Logic Data
DL129 — Rev 6
7 MOTOROLA
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and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
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MC54/74HC251/D
*MC54/74HC251/D*
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