Datasheet MC74HC242N Datasheet (Motorola)

Page 1

SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
   
The MC74HC242 is identical in pinout to the LS242. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This quad bus transceiver is designed for asynchronous two–way communications between data buses. The states of the Output Enables (A–to–B Enable and B–to–A Enable) determine both the direction of data flow (from A to B or from B to A) and the modes of the Data Ports (input, output, or high–impedance).
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
Low Input Current: 1µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 130 FETs or 32.5 Equivalent Gates
LOGIC DIAGRAM
Pin 14 = VCC Pin 7 = GND Pins 2, 12 = No Connection
A1
3
Output
EnableS
B Data Port
A2
4
A3
5
A4
6
A–TO–B ENABLE
1
B–TO–A ENABLE
13
B1
11
B2
10
B3
9
B4
8
A Data
Port
Pinout: 14–Lead Plastic Package (Top View)
1314 12 11 10 9 8
21 3 4 5 6 7
V
CC
B–to–A Enable
NC B1 B2 B3 B4
A–to–B Enable
NC A1 A2 A3 A4 GND
NC = No Connection
H L H L
H H L L
O Z Z
I
I Z Z O
I = Input; O = Output, O = Inverting Output Z = High Impedance

FUNCTION TABLE
Control Inputs Data Port Status
A–to–B
Enable
B–to–A
Enable
A
B
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
1
14
ORDERING INFORMATION
MC74HCXXXN Plastic
Page 2
MC74HC242
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
V
I/O
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
I/O
DC Output Current, per Pin
± 35
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
P
D
Power Dissipation in Still Air Plastic DIP†
750
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP Package
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature Range, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise/Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
0 0 0
1000
500 400
ns
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol Parameter Condition
V
CC V
–55 to 25°C 85°C 125°C Unit
V
IH
Minimum High–Level Input Voltage V
out
= 0.1V or VCC –0.1V
|I
out
| 20µA
2.0
4.5
6.0
1.50
3.15
4.20
1.50
3.15
4.20
1.50
3.15
4.20
V
V
IL
Maximum Low–Level Input Voltage V
out
= 0.1V or VCC – 0.1V
|I
out
| 20µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
OH
Minimum High–Level Output Voltage
Vin = VIH or V
IL
|I
out
| 20µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin =VIH or VIL|I
out
| 6.0mA
|I
out
| 7.8mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
V
OL
Maximum Low–Level Output Voltage
Vin = VIH or V
IL
|I
out
| 20µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL|I
out
| 6.0mA
|I
out
| 7.8mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
I
in
Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
I
OZ
Maximum Three–State Leakage Current
Output in High–Impedance State Vin = VIL or V
IH
V
out
= VCC or GND
6.0 ±0.5 ±5.0 ±10.0 µA
I
CC
Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND I
out
= 0µA
6.0 8 80 160 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance cir­cuit. For proper operation, Vin and V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Page 3
MC74HC242
High–Speed CMOS Logic Data DL129 — Rev 6
3 MOTOROLA
AC CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol Parameter
V
CC V
–55 to 25°C 85°C 125°C Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, A to B or B to A (Figures 2 and 4)
2.0
4.5
6.0
100
20 17
125
25 21
150
30 26
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Output A or B (Figures 3 and 5)
2.0
4.5
6.0
150
30 26
190
38 33
225
45 38
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Output A or B (Figures 3 and 5)
2.0
4.5
6.0
150
30 26
190
38 33
225
45 38
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output (Figures 2 and 4)
2.0
4.5
6.0
60 12 10
75 15 13
90 18 15
ns
C
in
Maximum Input Capacitance 10 10 10 pF
C
out
Maximum Three–State Output Capacitance (Output in High Impedance State)
15 15 15 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Transceiver)*
31
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
DATA PORTS A1–A4 (Pins 3,4,5,6) and B1–B4 (Pins 11,10,9,8)
Data on these pins may be transferred between d ata buses. Depending upon the states of the Output Enables, these pins may be inputs, outputs or open circuits (high–im­pedance).
CONTROL INPUTS A–to–B Enable (Pin 1) and B–to–A Enable (Pin 13)
Data on these Output Enables determine both the direc­tion of the data flow (from A to B or from B to A) and the states of the outputs (standard or high impedance), accord­ing to the Function Table.
Page 4
MC74HC242
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
Figure 1. Expanded Logic Diagram
One of Four
Transceivers
A (I/O)
V
CC
B (I/O)
V
CC
A–to–B
Enable
B–to–A
Enable
1
13
SWITCHING WAVEFORMS
Figure 2.
V
CC
GND
Input A or B
Output A or B
t
PHL
CL*
*Includes all probe and jig capacitance
TEST
POINT
Output
Enable
50%
V
CC
GND
Output A or B
t
PZL
Output A or B
t
PZH
High Impedance
V
OL
V
OH
High Impedance
10%
90%
t
PLZ
t
PHZ
50%
50%
t
PLH
90%
50%
10%
t
r
t
THL
t
f
t
TLH
Figure 3.
DEVICE UNDER
TEST
OUTPUT
TEST CIRCUITS
Figure 4. Figure 5.
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
1k
CONNECT TO VCC WHEN TESTING t
PLZ
AND t
PZL
. CONNECT TO GND WHEN TESTING t
PHZ
and t
PZH
.
90%
50%
10%
50%
Page 5
MC74HC242
High–Speed CMOS Logic Data DL129 — Rev 6
5 MOTOROLA
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
4. ROUNDED CORNERS OPTIONAL.
1 7
14 8
B
A
F
H G D
K
C
N
L
J
M
SEATING PLANE
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.715 0.770 18.16 19.56 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L 0.300 BSC 7.62 BSC M 0 10 0 10 N 0.015 0.039 0.39 1.01
_ _ _ _
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MC74HC242/D
*MC74HC242/D*
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