Datasheet MC54HC241AJ, MC74HC241ADW Datasheet (Motorola)



SEMICONDUCTOR TECHNICAL DATA

1

REV 7

 Motorola, Inc. 1997

2/97

     " 
! "
 "

High–Performance Silicon–Gate CMOS

The MC54/74HC241A is identical in pinout to the LS241. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.

This octal noninverting buffer/line driver/line receiver is designed to be
used with 3–state memory address drivers, clock drivers, and other
sub–oriented systems. The device has noninverted outputs and two output
enables. Enable A is active–low and Enable B is active–high.

The HC241A is similar in function to the HC244A and HC240A.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 134 FETs or 33.5 Equivalent Gates

LOGIC DIAGRAM

DATA

INPUTS

A1

A2

A3

A4

B1

B2

B3

B4

17

15

13

11

8

6

4

218

16

14

12

9

7

5

3

YB4

YB3

YB2

YB1

YA4

YA3

YA2

YA1

NONINVERTING
OUTPUTS

PIN 20 = V

CC

PIN 10 = GND

OUTPUT

ENABLES

ENABLE A
ENABLE B

1
19



PIN ASSIGNMENT

A3

A2

YB4

A1

ENABLE A

GND

YB1

A4

YB2

YB3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

YA2

B4

YA1

ENABLE B

V

CC

B1

YA4

B2

YA3

B3

FUNCTION TABLE

Inputs Output Inputs Output

Enable Enable

AAYA BBYB

LLL HLL
LHH HHH

HXZ LXZ

Z = high impedance

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ORDERING INFORMATION

MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW

Ceramic
Plastic
SOIC

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

1

20

1

20

1

20

MC54/74HC241A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

Î

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

ÎÎÎÎ

Î

750
500

Î

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

Î

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

(Ceramic DIP)

ÎÎÎÎ

Î

260
300

Î

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

ÎÎ

Î

tr, t

f

ОООООООООООО

Î

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

Î

Î

0
0
0

Î

Î

1000

500
400

Î

Î

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC

V

– 55 to

25_C

v

85_Cv 125_C

Unit

ÎÎ

Î

ÎÎ

Î

V

IH

ООООООО

Î

ООООООО

Î

Minimum High–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

1.5

2.1

3.15

4.2

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

Î

Î

Î

Î

V

ÎÎ

Î

ÎÎ

Î

V

IL

ООООООО

Î

ООООООО

Î

Maximum Low–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

0.5

0.9

1.35

1.8

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.8

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.8

Î

Î

Î

Î

V

ÎÎ

Î

V

OH

ООООООО

Î

Minimum High–Level Output
Voltage

ООООООО

Î

Vin = V

IH

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

1.9

4.4

5.9

ÎÎ

Î

1.9

4.4

5.9

ÎÎ

Î

1.9

4.4

5.9

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = V

IH

|I

out

| v 2.4 mA

|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

2.48

3.98

5.48

ÎÎ

Î

2.34

3.84

5.34

ÎÎ

Î

2.2

3.7

5.2

Î

Î

ÎÎ

Î

V

OL

ООООООО

Î

Maximum Low–Level Output
Voltage

ООООООО

Î

Vin = V

IL

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

0.1

0.1

0.1

ÎÎ

Î

0.1

0.1

0.1

ÎÎ

Î

0.1

0.1

0.1

Î

Î

V

ÎÎ

Î

ÎÎ

Î

ООООООО

Î

ООООООО

Î

ООООООО

Î

ООООООО

Î

Vin = V

IL

|I

out

| v 2.4 mA

|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

ÎÎ

Î

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

ÎÎ

0.26

0.26

0.26

ÎÎ

Î

ÎÎ

Î

0.33

0.33

0.33

ÎÎ

Î

ÎÎ

Î

0.4

0.4

0.4

Î

Î

Î

Î

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC54/74HC241A

High–Speed CMOS Logic Data
DL129 — Rev 6

3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Unit

v

125_C

v

85_C

– 55 to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

I

in

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

ÎÎ

Î

ÎÎ

Î

I

OZ

ООООООО

Î

ООООООО

Î

Maximum Three–State Leakage
Current

ООООООО

Î

ООООООО

Î

Output in High–Impedance State
Vin = VIL or V

IH

V

out

= VCC or GND

ÎÎ

Î

ÎÎ

Î

6.0

ÎÎ

ÎÎ

± 0.5

ÎÎ

Î

ÎÎ

Î

± 5.0

ÎÎ

Î

ÎÎ

Î

± 10

Î

Î

Î

Î

µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

6.0

4.0

40

160

µA

NOTE: Information on typical parametric values along with high frequency or heavy load considerations, can be found in Chapter 2 of the Motorola

High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

ÎÎ

Î

Symbol

ООООООООООООООО

Î

Parameter

ÎÎ

Î

V

CC

V

ÎÎ

– 55 to

25_C

ÎÎ

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎ

Î

ÎÎ

Î

t

PLH

,

t

PHL

ООООООООООООООО

Î

ООООООООООООООО

Î

Maximum Propagation Delay, Input A to Output Y

(Figures 1 and 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

90
45
18
15

ÎÎ

Î

ÎÎ

Î

115

60
23
20

ÎÎ

Î

ÎÎ

Î

135

70
27
23

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

PLZ

,

t

PHZ

ООООООООООООООО

Î

ООООООООООООООО

Î

Maximum Propagation Delay, Output Enable to Y

(Figures 2 and 4)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

120

60
24
20

ÎÎ

Î

ÎÎ

Î

150

70
30
26

ÎÎ

Î

ÎÎ

Î

180

80
36
31

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

PZL

,

t

PZH

ООООООООООООООО

Î

ООООООООООООООО

Î

Maximum Propagation Delay, Output Enable to Y

(Figures 2 and 4)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

90
60
18
15

ÎÎ

Î

ÎÎ

Î

115

70
23
20

ÎÎ

Î

ÎÎ

Î

135

80
27
23

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

TLH

,

t

THL

ООООООООООООООО

Î

ООООООООООООООО

Î

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

60
23
12
10

ÎÎ

Î

ÎÎ

Î

75
27
15
13

ÎÎ

Î

ÎÎ

Î

90
32
18
15

Î

Î

Î

Î

ns

C

in

Maximum Input Capacitance

—

10

10

10

pF

ÎÎ

C

out

ООООООООООООООО

Maximum Three–State Output Capacitance
(Output in High–Impedance State)

ÎΗÎÎ15ÎÎ15ÎÎ15Î

pF

NOTE:For propagation delays with loads other than 50 pF , and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Transceiver Channel)*

34

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC241A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

4

SWITCHING W AVEFORMS

Figure 1. Figure 2.

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

Figure 3. Test Circuit

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

Figure 4. Test Circuit

CONNECT TO VCC WHEN
TESTING t

PLZ

AND t

PZL

.
CONNECT TO GND WHEN
TESTING t

PHZ

AND t

PZH

.

1 k

Ω

ENABLE A

ENABLE B

OUTPUT Y

OUTPUT Y

V

CC

GND
V

CC

GND
HIGH

IMPEDANCE

HIGH
IMPEDANCE

V

OL

V

OH

50%

50%

50%

50%

90%

10%

t

PZLtPLZ

t

PZHtPHZ

V

CC

GND

t

f

t

r

DATA INPUT

A OR B

OUTPUT

YA OR YB

10%

50%

90%

10%

50%

90%

t

TLH

t

PLH

t

PHL

t

THL

PIN DESCRIPTIONS

INPUTS
A1, A2, A3, A4, B1, B2, B3, B4

(Pins 2, 4, 6, 8, 11, 13, 15, 17)

Data input pins. Data on these pins appear in noninverted
form on the corresponding Y outputs when the outputs are
enabled.

CONTROLS
Enable A (Pin 1)

Output enable (active–low). When a low level is applied to
this pin, the outputs of the “A” devices are enabled and the
devices function as noninverting buffers. When a high level is
applied, the outputs assume the high–impedance state.

Enable 8 (Pin 19)

Output enable (active–high). When a high level is applied
to this pin, the outputs of the “B” devices are enabled and the
devices function as noninverting buffers. When a low level is
applied, the outputs assume the high–impedance state.

OUTPUTS

YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4
(Pins 18, 16, 14, 12, 9, 7, 5, 3)

Device outputs. Depending upon the state of the output–
enable pins, these outputs are either noninverting outputs or
high–impedance outputs.

MC54/74HC241A

High–Speed CMOS Logic Data
DL129 — Rev 6

5 MOTOROLA

LOGIC DETAIL

DATA

INPUT

A

OUTPUT

ENABLES

TO THREE OTHER

“B” BUFFERS

TWO OF 8 BUFFERS

YA

V

CC

DATA

INPUT

B

YB

V

CC

ENABLE A

TO THREE OTHER

“A” BUFFERS

ENABLE B

MC54/74HC241A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

6

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

ISSUE E

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ISSUE E

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D–04

ISSUE E

NOTES:

1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

3. DIMENSIONS A AND B INCLUDE MENISCUS.

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 23.88 25.15 0.940 0.990
B 6.60 7.49 0.260 0.295
C 3.81 5.08 0.150 0.200
D 0.38 0.56 0.015 0.022
F 1.40 1.65 0.055 0.065
G 2.54 BSC 0.100 BSC
H 0.51 1.27 0.020 0.050
J 0.20 0.30 0.008 0.012
K 3.18 4.06 0.125 0.160
L 7.62 BSC 0.300 BSC
M 0 15 0 15
N 0.25 1.02 0.010 0.040

____

A

20

110

11

B

F

C

SEATING
PLANE

D

H

G

K

N

J

M

L

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

M

L

J

20 PL

M

B

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022

G 2.54 BSC0.100 BSC
J 0.21 0.380.008 0.015
K 2.80 3.550.110 0.140
L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040

____

E

1.27 1.770.050 0.070

1

11

10

20

–A–

SEATING
PLANE

K

N

FG

D

20 PL

–T–

M

A

M

0.25 (0.010) T

E

B

C

F

1.27 BSC0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.

–A–

–B–

20

1

11

10

S

A

M

0.010 (0.25) B

S

T

D20X

M

B

M

0.010 (0.25)

P10X

J

F

G

18X

K

C

–T–

SEATING
PLANE

M

R

X 45

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019

F 0.50 0.90 0.020 0.035

G 1.27 BSC 0.050 BSC

J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7

P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029

__

__

MC54/74HC241A

High–Speed CMOS Logic Data
DL129 — Rev 6

7 MOTOROLA

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MC74HC241A/D

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