Datasheet MC74HC175AF, MC74HC175ADTEL, MC74HC175ADR2, MC74HC175ADT, MC74HC175AFR2 Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 1999

March, 2000 – Rev. 2

1 Publication Order Number:

MC74HC175A/D

MC74HC175A

Quad D Flip-Flop with
Common Clock and Reset

High–Performance Silicon–Gate CMOS

The MC74HC175A is identical in pinout to the LS175. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.

This device consists of four D flip–flops with common Reset and
Clock inputs, and separate D inputs. Reset (active–low) is
asynchronous and occurs when a low level is applied to the Reset
input. Information at a D input is transferred to the corresponding Q
output on the next positive going edge of the Clock input.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity 166 FETs or 41.5 Equivalent Gates

LOGIC DIAGRAM

PIN 16 = V

CC

PIN 8 = GND

9

4

5
12
13

CLOCK

D0
D1
D2
D3

RESET

1

DATA

INPUTS

2
3

7

6
10
11
15
14

Q0
Q0

Q1
Q1
Q2

Q2
Q3
Q3

INVERTING

AND

NONINVERTING

OUTPUTS

FUNCTION TABLE

Inputs Outputs

Reset Clock D Q Q

LXXLH
HHHL
HLLH
H L X No Change

SO–16

D SUFFIX

CASE 751B

http://onsemi.com

TSSOP–16
DT SUFFIX
CASE 948F

1

16

PDIP–16
N SUFFIX
CASE 648

1

16

1

16

MARKING

DIAGRAMS

1

16

MC74HC175AN

AWLYYWW

1

16

HC175A

AWLYWW

A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week

HC

175A

ALYW

1

16

Device Package Shipping

ORDERING INFORMATION

MC74HC175AN PDIP–16 2000 / Box
MC74HC175AD SOIC–16

48 / Rail
MC74HC175ADR2 SOIC–16 2500 / Reel
MC74HC175ADT TSSOP–16 96 / Rail
MC74HC175ADTR2 TSSOP–16

2500 / Reel

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

D2

D3

Q3

Q3

V

CC

CLOCK

Q2

Q2

D0

Q0

Q0

RESET

GND

Q1

Q1

D1

MC74HC175A

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2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎ

Î

750
500
450

Î

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

ÎÎ

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

ÎÎÎ

Î

260

Î

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

ÎÎ

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

ÎÎ

+ 125

_

C

ÎÎ

Î

tr, t

f

ООООООООООООО

Î

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 3.0 V

VCC = 4.5 V
VCC = 6.0 V

Î

Î

0
0
0

ÎÎ

ÎÎ

1000

600
500
400

Î

Î

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Î

Symbol

ООООООО

Î

Parameter

ООООООО

Î

Test Conditions

ÎÎ

Î

V

CC
V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

Î

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎ

Î

ÎÎ

Î

V

IH

ООООООО

Î

ООООООО

Î

Minimum High–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

ÎÎÎ

Î

Î

Î

Î

Î

Î

1.5

2.1

3.15

4.2

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15
4 2

Î

Î

Î

Î

V

ÎÎ

Î

ÎÎ

Î

V

IL

ООООООО

Î

ООООООО

Î

Maximum Low–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.80

ÎÎÎ

Î

Î

Î

Î

Î

Î

0.5

0.9

1.35

1.80

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.80

Î

Î

Î

Î

V

ÎÎ

Î

V

OH

ООООООО

Î

Minimum High–Level Output
Voltage

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

1.9

4.4

5.9

ÎÎÎ

Î

Î

Î

1.9

4.4

5.9

ÎÎ

Î

1.9

4.4

5.9

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

2.48

3.98

5.48

ÎÎÎ

Î

Î

Î

2.34

3.84

5.34

ÎÎ

Î

2.20

3.70

5.20

Î

Î

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HC175A

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3

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Unit

Guaranteed Limit

V

CC

V

Test Conditions

Parameter

Symbol

Unit

v

125_C

ÎÎÎ

v

85_C

– 55 to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

ÎÎ

Î

ÎÎ

Î

V

OL

ООООООО

Î

ООООООО

Î

Maximum Low–Level Output
Voltage

ООООООО

Î

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

0.1

0.1

0.1

ÎÎÎ

Î

Î

Î

Î

Î

Î

0.1

0.1

0.1

ÎÎ

Î

ÎÎ

Î

0.1

0.1

0.1

Î

Î

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

0.26

0.26

0.26

ÎÎÎ

Î

Î

Î

0.33

0.33

0.33

ÎÎ

Î

0.40

0.40

0.40

Î

Î

ÎÎ

Î

I

in

ООООООО

Î

Maximum Input Leakage
Current

ООООООО

Î

Vin = VCC or GND

ÎÎ

Î

6.0

ÎÎ

Î

± 0.1

ÎÎÎ

Î

Î

Î

± 1.0

ÎÎ

Î

± 1.0

Î

Î

µA

ÎÎ

Î

I

CC

ООООООО

Î

Maximum Quiescent Supply
Current (per Package)

ООООООО

Î

Vin = VCC or GND
I

out

= 0 µA

ÎÎ

Î

6.0

ÎÎ

Î

4

ÎÎÎ

Î

Î

40

ÎÎ

Î

160

Î

Î

µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

ÎÎÎ

Î

Symbol

ОООООООООООООО

Î

Parameter

ÎÎ

Î

V

CC
V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

Î

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎÎ

Î

ÎÎÎ

Î

f

max

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

6
10
30
35

ÎÎÎ

Î

Î

Î

Î

Î

Î

4.8

8.0
24
28

ÎÎ

Î

ÎÎ

Î

4

6
20
24

Î

Î

Î

Î

MHz

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Clock to Q or Q

(Figures 1 and 4)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

150

75
26
22

ÎÎÎ

Î

Î

Î

Î

Î

Î

190

90
32
28

ÎÎ

Î

ÎÎ

Î

225
110

38
33

Î

Î

Î

Î

ns

ÎÎÎ

Î

t

PHL

ОООООООООООООО

Î

Maximum Propagation Delay, Reset to Q or Q

(Figures 2 and 4)

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

125

70
22
19

ÎÎÎ

Î

Î

Î

155

85
27
24

ÎÎ

Î

190
110

34
30

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

TLH

,

t

THL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

75
27
15
13

ÎÎÎ

Î

Î

Î

Î

Î

Î

95
32
19
16

ÎÎ

Î

ÎÎ

Î

110

36
22
19

Î

Î

Î

Î

ns

C

in

Maximum Input Capacitance

—

10

ÎÎÎ

10

10

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Flip–Flop)*

35

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

MC74HC175A

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4

TIMING REQUIREMENTS (Input t

r

= tf = 6 ns)

Guaranteed Limit

ÎÎÎ

Î

Symbol

ОООООООООООООО

Î

Parameter

ÎÎ

Î

V

CC
V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

Î

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎÎ

Î

t

su

ОООООООООООООО

Î

Minimum Setup Time, Data to Clock

(Figure 3)

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

100

45
20
17

ÎÎÎ

Î

Î

Î

125

65
25
21

ÎÎ

Î

150

85
30
26

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

h

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Hold Time, Clock to Data

(Figure 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

5
3
3
3

ÎÎÎ

Î

Î

Î

Î

Î

Î

5
3
3
3

ÎÎ

Î

ÎÎ

Î

5

3

3

3

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

rec

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Recovery Time, Reset Inactive to Clock

(Figure 2)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

100

45
20
17

ÎÎÎ

Î

Î

Î

Î

Î

Î

125

65
25
21

ÎÎ

Î

ÎÎ

Î

150

85
30
26

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

w

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Pulse Width, Clock

(Figure 1)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

80
45
16
14

ÎÎÎ

Î

Î

Î

Î

Î

Î

100

65
20
17

ÎÎ

Î

ÎÎ

Î

120

85
24
20

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

w

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Pulse Width, Reset

(Figure 2)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

80
45
16
14

ÎÎÎ

Î

Î

Î

Î

Î

Î

100

65
20
17

ÎÎ

Î

ÎÎ

Î

120

85
24
20

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

tr, t

f

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Input Rise and Fall Times

(Figure 1)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1000

800
500
400

ÎÎÎ

Î

Î

Î

Î

Î

Î

1000

800
500
400

ÎÎ

Î

ÎÎ

Î

1000

800
500
400

Î

Î

Î

Î

ns

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

MC74HC175A

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5

SWITCHING W AVEFORMS

Figure 1. Figure 2.

50%

50%

50%

50%

V

CC

V

CC

GND

GND

RESET

Q

Q

CLOCK

t

PLH

t

PHL

50%

DATA

CLOCK

V

CC

V

CC

GND

Figure 3.

GND

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

Figure 4.

1/f

max

CLOCK

Q or Q

t

f

t

r

V

CC

GND

90%

50%

10%

90%

50%

10%

t

PLH

t

PHL

t

TLH

t

THL

t

w

t

w

t

rec

VALID

t

h

t

su

TEST CIRCUIT

MC74HC175A

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6

DQ

C
C

R

D0

CLOCK

D1

D2

D3

RESET

1

13

12

5

9

4

2

3

7

6

10

11

15

14

Q0

Q0

Q1

Q1

Q2

Q2

Q3

Q3

EXPANDED LOGIC DIAGRAM

DQ

C
C

R

DQ

C
C

R

DQ

C
C

R

MC74HC175A

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7

P ACKAGE DIMENSIONS

PDIP–16

N SUFFIX

CASE 648–08

ISSUE R

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

A
B
C
D
F
G
H

J
K
L
M
S

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50
0°

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74
10°

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295
0°

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305
10°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

B

18

916

F

H

G

D

16 PL

S

C

–T

–

SEATING
PLANE

K

J

M

L

TA0.25 (0.010)

M M

0.25 (0.010) T B A

M

S S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F
G
J
K
M
P
R

9.80

3.80

1.35

0.35

0.40

0.19

0.10
0°

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

0.25
7°

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004
0°

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.009
7°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

1

8

916

–A

–

–B

–

D

16 PL

K

C

G

–T

–

SEATING

PLANE

R X 45°

M

J

F

P 8 PL

0.25 (0.010) B

M M

SOIC–16

D SUFFIX

CASE 751B–05

ISSUE J

MC74HC175A

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8

P ACKAGE DIMENSIONS

TSSOP–16
DT SUFFIX

CASE 948F–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.

____

SECTION N–N

SEATING
PLANE

IDENT.

PIN 1

1

8

16

9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

DETAIL E

F

M

L

2X L/2

–U–

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V

S

T

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

N

N

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