Datasheet MC74HC173N, MC74HC173D Datasheet (Motorola)



SEMICONDUCTOR TECHNICAL DATA

1

REV 6

 Motorola, Inc. 1995

10/95

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   

High–Performance Silicon–Gate CMOS

The MC74HC173 is identical in pinout to the LS173. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.

Data, when enabled, are clocked into the four D flip–flops with the rising
edge of t he common Clock. W hen either or b oth of the Output Enable
Controls is high, the outputs are in a high–impedance state. This feature
allows the HC173 to be used in bus–oriented systems. The Reset feature is
asynchronous and active high.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity 208 FETs or 52 Equivalent Gates

FUNCTION TABLE

Inputs Output

Output Enables

Data Enables

Data

OE1 OE2

Reset

Clock

DE1 DE2

Data

D

Q

L L H X X X X L
L L L L X X X No Change

L L L H X X X No Change
L L L H X X No Change
L L L X H X No Change
L L L L L L L
L L L L L H H
L L L X X X No Change
L H X X X X X High Impedance
H L X X X X X High Impedance
H H X X X X X High Impedance



PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

D2

D1

D0

RESET

V

CC

DE1

DE2

D3

Q1

Q0

OE2

OE1

GND

CLOCK

Q3

Q2

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC74HCXXXN
MC74HCXXXD

Plastic
SOIC

1

16

1

16

LOGIC DIAGRAM

VCC = PIN 16
GND = PIN 8

DATA

INPUTS

3–STATE

NONINVERTING

OUTPUTS

D0
D1
D2
D3

14
13
12
11

3
4
5
6

Q0
Q1
Q2
Q3

CLOCK

7

DATA–

ENABLES

OUTPUT

ENABLES

DE1
DE2

OE1
OE2

RESET

9

10
15

1
2

MC74HC173

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

P

D

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

750
500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

0
0
0

1000

500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

0.3

0.9

1.2

0.3

0.9

1.2

0.3

0.9

1.2

V

V

OH

Minimum High–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin = VIH or VIL|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.70

5.20

V

OL

Maximum Low–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or VIL|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

4.5

6.0

0.26

0.26

0.33

0.33

0.40

0.40

I

in

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

I

OZ

Maximum Three–State
Leakage Current

Output in High–Impedance State
Vin = VIL or V

IH

V

out

= VCC or GND

6.0

± 0.5

± 5.0

± 10

µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

6.0

8

80

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HC173

High–Speed CMOS Logic Data
DL129 — Rev 6

3 MOTOROLA

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

f

max

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 5)

2.0

4.5

6.0

6.0
30
35

4.8
24
28

4.0
20
24

MHz

t

PLH

,

t

PHL

Maximum Propagation Delay, Clock to Q

(Figures 1 and 5)

2.0

4.5

6.0

175

35
30

220

44
37

265

53
45

ns

t

PHL

Maximum Propagation Delay, Reset to Q

(Figures 2 and 5)

2.0

4.5

6.0

150

30
26

190

38
33

225

45
38

ns

t

PLZ

,

t

PHZ

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

2.0

4.5

6.0

150

30
26

190

38
33

225

45
38

ns

t

PZL

,

t

PZH

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

2.0

4.5

6.0

150

30
26

190

38
33

225

45
38

ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output

(Figures 1 and 5)

2.0

4.5

6.0

60
12
10

75
15
13

90
18
15

ns

C

in

Maximum Input Capacitance

—

10

10

10

pF

C

out

Maximum Three–State Output Capacitance
(Output in High–Impedance State)

—

15

15

15

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Flip–Flop)*

35

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (Input t

r

= tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

t

su

Minimum Setup Time, Input D or DE to Clock

(Figure 4)

2.0

4.5

6.0

100

20
17

125

25
21

150

30
26

ns

t

h

Minimum Hold Time, Clock to Input D or DE

(Figure 4)

2.0

4.5

6.0

3
3
3

3
3
3

3
3
3

ns

t

rec

Minimum Recovery Time, Reset Inactive to Clock

(Figure 2)

2.0

4.5

6.0

90
18
15

115

23
20

135

27
23

ns

t

w

Minimum Pulse Width, Clock

(Figure 1)

2.0

4.5

6.0

80
16
14

100

20
17

120

24
20

ns

t

w

Minimum Pulse Width, Reset

(Figure 2)

2.0

4.5

6.0

80
16
14

100

20
17

120

24
20

ns

tr, t

f

Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

1000

500
400

1000

500
400

1000

500
400

ns

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

MC74HC173

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

4

PIN DESCRIPTIONS

INPUTS

D0, D1, D2, D3 (Pins 14, 13, 12, 11)

4–bit data inputs. Data on these pins, when enabled by the
Data–Enable Controls, are entered into the flip–flops on the
rising edge of the clock.

CLOCK (Pin 7)

Clock input.

OUTPUTS
Q0, Q1, Q2, Q3 (Pins 3, 4, 5, 6)

3–state register outputs. During normal operation of the
device, the outputs of the D flip–flops appear at these pins.
During 3–state operation, these outputs assume a high–
impedance state.

CONTROL INPUT
Reset (Pin 15)

Asynchronous reset input. A high level on this pin resets all
flip–flops and forces the Q outputs low, if they are not already
in high–impedance state.

DE1, DE2 (Pins 9, 10)

Active–low Data Enable Control inputs. When both Data
Enable Controls are low, data at the D inputs are loaded into
the flip–flops with the rising edge of the Clock input. When
either or both of these controls are high, there is no change in
the state of the flip–flops, regardless of any changes at the D
or Clock inputs.

OE1, OE2 (Pins 1, 2)

Output Enable Control inputs. When either or both of the
Output Enable Controls are high, the Q outputs of the device
are in the high–impedance state. When both controls are
low, the device outputs display the data in the flip–flops.

SWITCHING WAVEFORMS

t

r

t

f

V

CC

GND

t

THL

t

TLH

90%

50%

10%

90%

50%

10%

CLOCK

t

PLH

t

PHL

t

w

50%

t

PHL

V

CC

GND

V

CC

GND

CLOCK

RESET

50%

50%

t

rec

Figure 1. Figure 2.

Q

Q

V

CC
GND
V

CC
GND

50%

50%

CLOCK

INPUT D

OR DE

50%

50%

50%

OE

Q

Q

t

PZLtPLZ

t

PZHtPHZ

10%

90%

V

CC
GND
HIGH

IMPEDANCE
V

OL
V

OH

Figure 3. Figure 4.

t

w

1/f

max

HIGH
IMPEDANCE

VALID

t

su

t

h

MC74HC173

High–Speed CMOS Logic Data
DL129 — Rev 6

5 MOTOROLA

TEST CIRCUITS

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

Figure 5. Figure 6.

OUTPUT

TEST POINT

CL *

1 k

Ω

CONNECT TO VCC WHEN
TESTING t

PLZ

AND t

PZL.

CONNECT TO GND WHEN
TESTING t

PHZ

and t

PZH.

DEVICE
UNDER

TEST

*Includes all probe and jig capacitance

LOGIC DETAIL

D0

14

D1

13

D2

12

D3

11

9

10

DE1
DE2

15

RESET

CLOCK

7

OE1

OE2

1

2

DATA–

ENABLES

OUTPUT

ENABLES

DATA

INPUTS

C
C

R

Q

V

CC

3

Q0

D

C
C

R

Q

D

C
C

R

Q

D

C
C

R

Q

D

V

CC

4

Q1

V

CC

5

Q2

V

CC

6

Q3

MC74HC173

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

6

OUTLINE DIMENSIONS

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

A
B
C
D
F
G
H
J
K
L
M
S

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50
0

°

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74
10

°

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295
0

°

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305
10

°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

B

1 8

916

F

H

G

D

16 PL

S

C

–T

–

SEATING
PLANE

K

J

M

L

T A0.25 (0.010)

M M

0.25 (0.010) T B A

M

S S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F
G
J
K
M
P
R

9.80

3.80

1.35

0.35

0.40

0.19

0.10
0

°

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

0.25
7

°

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004
0

°

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.009
7

°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

1

8

916

–A

–

–B

–

D 16 PL

K

C

G

–T

–

SEATING

PLANE

R X 45°

M

J

F

P 8 PL

0.25 (0.010) B

M M

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

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MC74HC173/D

*MC74HC173/D*

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