Datasheet MC74HC165AN, MC74HC165AD, MC74HC165AFR2, MC74HC165ADT, MC74HC165ADTR2 Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 2

1 Publication Order Number:

MC74HC165A/D

MC74HC165A

8-Bit Serial or
Parallel-Input/
Serial-Output Shift Register

High–Performance Silicon–Gate CMOS

The MC74HC165A is identical in pinout to the LS165. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.

This device is an 8–bit shift register with complementary outputs
from the last stage. Data may be loaded into the register either in
parallel or in serial form. When the Serial Shift/Parallel Load

input is
low, the data is loaded asynchronously in parallel. When the Serial
Shift/Parallel Load

input is high, the data is loaded serially on the

rising edge of either Clock or Clock Inhibit (see the Function Table).

The 2–input NOR clock may be used either by combining two
independent clock sources or by designating one of the clock inputs to
act as a clock inhibit.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 286 FETs or 71.5 Equivalent Gates

Device Package Shipping

ORDERING INFORMATION

MC74HC165AN PDIP–14 2000 / Box
MC74HC165AD SOIC–14

http://onsemi.com

55 / Rail

MC74HC165ADR2 SOIC–14 2500 / Reel

MARKING

DIAGRAMS

A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

MC74HC165ADT TSSOP–14 96 / Rail
MC74HC165ADTR2 TSSOP–14

2500 / Reel

TSSOP–14
DT SUFFIX

CASE 948G

HC

165A

ALYW

1

14

1

14

PDIP–14

N SUFFIX

CASE 646

MC74HC165AN

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

1

14

HC165A

AWLYWW

MC74HC165A

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2

LOGIC DIAGRAM

PIN 16 = V

CC

PIN 8 = GND

11
12
13
14

3
4
5
6

10

A
B
C

D
E
F
G
H

S

A

PARALLEL

DATA

INPUTS

SERIAL

DATA

INPUT

SERIAL SHIFT/

PARALLEL LOAD

1

2

15

CLOCK

CLOCK INHIBIT

9

7

Q

H

Q

H

SERIAL

DATA

OUTPUTS

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

B

C

D

CLOCK INHIBIT

V

CC

Q

H

S

A

A

F

E

CLOCK

SERIAL SHIFT/

PARALLEL LOAD

GND

Q

H

H

G

FUNCTION TABLE

Inputs Internal Stages Output

Serial Shift/

Parallel Load

Clock

Clock

Inhibit

S

A

A – H Q

A

Q

B

Q

H

Operation

L X X X a … h a b h Asynchronous Parallel Load
H

H

L
L

L
H

X
X

L
H

Q

An

Q

An

Q

Gn

Q

Gn

Serial Shift via Clock

H
H

L
L

L
H

X
X

L
H

Q

An

Q

An

Q

Gn

Q

Gn

Serial Shift via Clock Inhibit

H
H

X
H

H
X

X
X

X
X

No Change Inhibited Clock

H L L X X No Change No Clock

X = don’t care QAn – QGn = Data shifted from the preceding stage

MC74HC165A

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3

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎ

Î

750
500
450

Î

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

ÎÎ

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

ÎÎÎ

Î

260

Î

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

ÎÎ

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

ÎÎ

+ 125

_

C

ÎÎ

Î

tr, t

f

ООООООООООООО

Î

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 3.0 V

VCC = 4.5 V
VCC = 6.0 V

Î

Î

0
0
0

ÎÎ

ÎÎ

1000

600
500
400

Î

Î

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Î

Symbol

ООООООО

Î

Parameter

ООООООО

Î

Test Conditions

ÎÎ

Î

V

CC
V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

Î

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎ

Î

ÎÎ

Î

V

IH

ООООООО

Î

ООООООО

Î

Minimum High–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

ÎÎÎ

Î

Î

Î

Î

Î

Î

1.5

2.1

3.15

4.2

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

Î

Î

Î

Î

V

ÎÎ

Î

ÎÎ

Î

V

IL

ООООООО

Î

ООООООО

Î

Maximum Low–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.80

ÎÎÎ

Î

Î

Î

Î

Î

Î

0.5

0.9

1.35

1.80

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.80

Î

Î

Î

Î

V

ÎÎ

Î

V

OH

ООООООО

Î

Minimum High–Level Output
Voltage

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

1.9

4.4

5.9

ÎÎÎ

Î

Î

Î

1.9

4.4

5.9

ÎÎ

Î

1.9

4.4

5.9

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

2.48

3.98

5.48

ÎÎÎ

Î

Î

Î

2.34

3.84

5.34

ÎÎ

Î

2.20

3.70

5.20

Î

Î

V

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HC165A

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4

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Unit

Guaranteed Limit

V

CC

V

Test Conditions

Parameter

Symbol

Unit

v

125_C

ÎÎÎ

v

85_C

– 55 to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

ÎÎ

Î

ÎÎ

Î

V

OL

ООООООО

Î

ООООООО

Î

Maximum Low–Level Output
Voltage

ООООООО

Î

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

0.1

0.1

0.1

ÎÎÎ

Î

Î

Î

Î

Î

Î

0.1

0.1

0.1

ÎÎ

Î

ÎÎ

Î

0.1

0.1

0.1

Î

Î

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

0.26

0.26

0.26

ÎÎÎ

Î

Î

Î

0.33

0.33

0.33

ÎÎ

Î

0.40

0.40

0.40

Î

Î

ÎÎ

Î

I

in

ООООООО

Î

Maximum Input Leakage
Current

ООООООО

Î

Vin = VCC or GND

ÎÎ

Î

6.0

ÎÎ

Î

± 0.1

ÎÎÎ

Î

Î

Î

± 1.0

ÎÎ

Î

± 1.0

Î

Î

µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

6.0

4

ÎÎÎ

40

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

ÎÎÎ

Î

Symbol

ОООООООООООООО

Î

Parameter

ÎÎ

Î

V

CC
V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

Î

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎÎ

Î

ÎÎÎ

Î

f

max

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 8)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

6
18
30
35

ÎÎÎ

Î

Î

Î

Î

Î

Î

4.8
17
24
28

ÎÎ

Î

ÎÎ

Î

4
15
20
24

Î

Î

Î

Î

MHz

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or Q

H

(Figures 1 and 8)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

150

52
30
26

ÎÎÎ

Î

Î

Î

Î

Î

Î

190

63
38
33

ÎÎ

Î

ÎÎ

Î

225

65
45
38

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Serial Shift/Parallel Load to QH or
Q

H

(Figures 2 and 8)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

175

58
35
30

ÎÎÎ

Î

Î

Î

Î

Î

Î

220

70
44
37

ÎÎ

Î

ÎÎ

Î

265

72
53
45

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Input H to QH or Q

H

(Figures 3 and 8)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

150

52
30
26

ÎÎÎ

Î

Î

Î

Î

Î

Î

190

63
38
33

ÎÎ

Î

ÎÎ

Î

225

65
45
38

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

TLH

,

t

THL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Output Transition Time, Any Output

(Figures 1 and 8)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

75
27
15
13

ÎÎÎ

Î

Î

Î

Î

Î

Î

95
32
19
16

ÎÎ

Î

ÎÎ

Î

110

36
22
19

Î

Î

Î

Î

ns

C

in

Maximum Input Capacitance

—

10

ÎÎÎ

10

10

pF

NOTES:

1. For propagation delays with loads other than 50 pF , see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Package)*

40

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

MC74HC165A

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5

TIMING REQUIREMENTS (Input t

r

= tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC

V

– 55 to

25_C

v

85_Cv 125_C

Unit

ÎÎ

Î

ÎÎ

Î

t

su

ОООООООООООООООО

Î

ОООООООООООООООО

Î

Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load

(Figure 4)

Î

Î

Î

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

75
30
15
13

ÎÎ

Î

ÎÎ

Î

95
40
19
16

Î

Î

Î

Î

110

55
22
19

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

su

ОООООООООООООООО

Î

ОООООООООООООООО

Î

Minimum Setup Time, Input SA to Clock (or Clock Inhibit)

(Figure 5)

Î

Î

Î

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

75
30
15
13

ÎÎ

Î

ÎÎ

Î

95
40
19
16

Î

Î

Î

Î

110

55
22
19

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

su

ОООООООООООООООО

Î

ОООООООООООООООО

Î

Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock
Inhibit)

(Figure 6)

Î

Î

Î

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

75
30
15
13

ÎÎ

Î

ÎÎ

Î

95
40
19
16

Î

Î

Î

Î

110

55
22
19

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

su

ОООООООООООООООО

Î

ОООООООООООООООО

Î

Minimum Setup Time, Clock to Clock Inhibit

(Figure 7)

Î

Î

Î

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

75
30
15
13

ÎÎ

Î

ÎÎ

Î

95
40
19
16

Î

Î

Î

Î

110

55
22
19

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

h

ОООООООООООООООО

Î

ОООООООООООООООО

Î

Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs

(Figure 4)

Î

Î

Î

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

5
5
5
5

ÎÎ

Î

ÎÎ

Î

5
5
5
5

Î

Î

Î

Î

5
5
5
5

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

h

ОООООООООООООООО

Î

ОООООООООООООООО

Î

Minimum Hold Time, Clock (or Clock Inhibit) to Input SA

(Figure 5)

Î

Î

Î

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

5
5
5
5

ÎÎ

Î

ÎÎ

Î

5
5
5
5

Î

Î

Î

Î

5
5
5
5

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

h

ОООООООООООООООО

Î

ОООООООООООООООО

Î

Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel
Load

(Figure 6)

Î

Î

Î

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

5
5
5
5

ÎÎ

Î

ÎÎ

Î

5
5
5
5

Î

Î

Î

Î

5
5
5
5

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

rec

ОООООООООООООООО

Î

ОООООООООООООООО

Î

Minimum Recovery Time, Clock to Clock Inhibit

(Figure 7)

Î

Î

Î

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

75
30
15
13

ÎÎ

Î

ÎÎ

Î

95
40
19
16

Î

Î

Î

Î

110

55
22
19

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

w

ОООООООООООООООО

Î

ОООООООООООООООО

Î

Minimum Pulse Width, Clock (or Clock Inhibit)

(Figure 1)

Î

Î

Î

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

70
27
15
13

ÎÎ

Î

ÎÎ

Î

90
32
19
16

Î

Î

Î

Î

100

36
22
19

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

w

ОООООООООООООООО

Î

ОООООООООООООООО

Î

Minimum Pulse width, Serial Shift/Parallel Load

(Figure 2)

Î

Î

Î

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

70
27
15
13

ÎÎ

Î

ÎÎ

Î

90
32
19
16

Î

Î

Î

Î

100

36
22
19

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

tr, t

f

ОООООООООООООООО

Î

ОООООООООООООООО

Î

Maximum Input Rise and Fall Times

(Figure 1)

Î

Î

Î

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1000

800
500
400

ÎÎ

Î

ÎÎ

Î

1000

800
500
400

Î

Î

Î

Î

1000

800

500

400

Î

Î

Î

Î

ns

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

MC74HC165A

http://onsemi.com

6

PIN DESCRIPTIONS

INPUTS
A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6)

Parallel Data inputs. Data on these inputs are
asynchronously entered in parallel into the internal
flip–flops when the Serial Shift/Parallel Load

input is low.

SA (Pin 10)

Serial Data input. When the Serial Shift/Parallel Load
input is high, data on this pin is serially entered into the first
stage of the shift register with the rising edge of the Clock.

CONTROL INPUTS
Serial Shift/Parallel Load

(Pin 1)

Data–entry control input. When a high level is applied to
this pin, data at the Serial Data input (SA) are shifted into the
register with the rising edge of the Clock. When a low level

is applied to this pin, data at the Parallel Data inputs are
asynchronously loaded into each of the eight internal stages.

Clock, Clock Inhibit (Pins 2, 15)

Clock inputs. These two clock inputs function identically .
Either may be used as an active–high clock inhibit.
However, to avoid double clocking, the inhibit input should
go high only while the clock input is high.

The shift register is completely static, allowing Clock
rates down to DC in a continuous or intermittent mode.

OUTPUTS
QH, Q

H

(Pins 9, 7)

Complementary Shift Register outputs. These pins are the
noninverted and inverted outputs of the eighth stage of the
shift register.

MC74HC165A

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7

SWITCHING W AVEFORMS

t

r

t

f

V

CC

GND

90%

50%

10%

t

PLH

t

PHL

CLOCK

OR CLOCK INHIBIT

90%

50%

10%

t

TLH

t

THL

QH OR Q

H

Figure 1. Serial–Shift Mode

SERIAL SHIFT/

PARALLEL LOAD

QH OR Q

H

50%

t

PLH

50%

V

CC

GND

t

PHL

50%

Figure 2. Parallel–Load Mode

t

r

t

f

INPUT H

90%

50%

10%

90%

50%

10%

V

CC

GND

t

PHL

t

THL

t

TLH

t

PLH

QH OR Q

H

Figure 3. Parallel–Load Mode

50%

V

CC

GND

t

h

V

CC

GND

ASYNCHRONOUS P ARALLEL

LOAD

(LEVEL SENSITIVE)

SERIAL SHIFT/

PARALLEL LOAD

INPUTS A–H

Figure 4. Parallel–Load Mode

INPUT S

A

50%

50%

CLOCK

OR CLOCK INHIBIT

V

CC

GND

V

CC

GND

Figure 5. Serial–Shift Mode

SERIAL SHIFT/

PARALLEL LOAD

CLOCK

OR CLOCK INHIBIT

50%

50%

t

su

V

CC
GND

V

CC
GND

CLOCK 2 INHIBITED

CLOCK INHIBIT

CLOCK

50%

50%

t

su

t

rec

V

CC

GND

V

CC

GND

Figure 6. Serial–Shift Mode

Figure 7. Serial–Shift, Clock–Inhibit Mode Figure 8. Test Circuit

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

t

w

1/f

max

t

w

VALID

t

su

VALID

t

su

t

h

t

h

MC74HC165A

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8

ABCFGH

11 12 13 4 5 6

9

Q

H

7

Q

H

SERIAL SHIFT/

PARALLEL LOAD

1

SERIAL DATA

INPUT S

A

10

CLOCK

2

CLOCK
INHIBIT

15

EXPANDED LOGIC DIAGRAM

CLOCK

CLOCK INHIBIT

S

A

SERIAL SHIFT/

PARALLEL LOAD

A

B
C
D
E
F
G
H

Q

H

Q

H

H
L

H
L

H
L
H
H

HHLLLHHLLHHLLHH

L

PARALLEL LOAD

PARALLEL

DATA

INPUTS

TIMING DIAGRAM

DQ

A

CC

DQ

B

CC

DQ

C

CC

DQ

F

CC

DQ

G

CC

DQ

H

CC

CLOCK

INHIBIT

MODE

SERIAL–SHIFT MODE

MC74HC165A

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9

P ACKAGE DIMENSIONS

PDIP–14

N SUFFIX

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

4. ROUNDED CORNERS OPTIONAL.

17

14 8

B

A

F

HG D

K

C

N

L

J

M

SEATING
PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78

G 0.100 BSC 2.54 BSC

H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC

M 0 10 0 10

N 0.015 0.039 0.39 1.01

____

SOIC–14

D SUFFIX

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

G

P

7 PL

14 8

71

M

0.25 (0.010) B

M

S

B

M

0.25 (0.010) A

S

T

–T–

F

R

X 45

SEATING
PLANE

D 14 PL

K

C

J

M

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

____

MC74HC165A

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10

P ACKAGE DIMENSIONS

TSSOP–14

DT SUFFIX

CASE 948G–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V

S

T

L

–U–

SEATING
PLANE

0.10 (0.004)

–T–

SECTION N–N

DETAIL E

J

J1

K

K1

DETAIL E

F

M

–W–

0.25 (0.010)

8

14

7

1

PIN 1
IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

–V–

14X REFK

N

N

MC74HC165A

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11

Notes

MC74HC165A

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12

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