Page 1
SEMICONDUCTOR TECHNICAL DATA
1
REV 7
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC74HC03A is identical in pinout to the LS03. The device inputs
are compatible with Standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
The HC03A NAND gate has, as its outputs, a high–performance MOS
N–Channel transistor. This NAND gate can, therefore, with a suitable
pullup resistor, be used in wired–AND applications. Having the output
characteristic curves given in this data sheet, this device can be used as
an LED driver or in any other application that only requires a sinking
current.
• Output Drive Capability: 10 LSTTL Loads With Suitable Pullup Resistor
• Outputs Directly Interface to CMOS, NMOS and TTL
• High Noise Immunity Characteristic of CMOS Devices
• Operating Voltage Range: 2 to 6V
• Low Input Current: 1µA
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 28 FETs or 7 Equivalent Gates
DESIGN GUIDE
Criteria Value Unit
Internal Gate Count* 7.0 ea
Internal Gate Propagation Delay 1.5 ns
Internal Gate Power Dissipation 5.0 µW
Speed Power Product 0.0075 pJ
* Equivalent to a two–input NAND gate
PIN 14 = V
CC
PIN 7 = GND
* Denotes open–drain outputs
LOGIC DIAGRAM
3,6,8,11
Y*
1,4,9,12
A
2,5,10,13
B
OUTPUT
PROTECTION
DIODE
V
CC
Pinout: 14–Lead Packages (Top View)
1314 12 11 10 9 8
21 3 4 5 6 7
V
CC
B4 A4 Y4 B3 A3 Y3
A1 B1 Y1 A2 B2 Y2 GND
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
A B
Z
Z
Z
L
Y
Z = High Impedance
D SUFFIX
SOIC PACKAGE
CASE 751A–03
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
ORDERING INFORMATION
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT
Plastic
SOIC
TSSOP
1
14
1
14
1
14
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
Page 2
MC74HC03A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 50
mA
P
D
Power Dissipation in Still Air Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC CHARACTERISTICS (Voltages Referenced to GND)
V
Guaranteed Limit
Symbol Parameter Condition
V
CC
V
–55 to 25°C ≤85°C ≤125°C Unit
V
IH
Minimum High–Level Input Voltage V
out
= 0.1V or VCC –0.1V
|I
out
| ≤ 20µA
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
V
IL
Maximum Low–Level Input Voltage V
out
= 0.1V or VCC – 0.1V
|I
out
| ≤ 20µA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
V
OL
Maximum Low–Level Output
Voltage
V
out
= 0.1V or VCC – 0.1V
|I
out
| ≤ 20µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL|I
out
| ≤ 2.4mA
|I
out
| ≤ 4.0mA
|I
out
| ≤ 5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
I
out
= 0µA
6.0 1.0 10 40 µA
I
OZ
Maximum Three–State Leakage
Current
Output in High–Impedance State
Vin = VIL or V
IH
V
out
= VCC or GND
6.0 ±0.5 ±5.0 ±10 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Page 3
MC74HC03A
High–Speed CMOS Logic Data
DL129 — Rev 6
3 MOTOROLA
AC CHARACTERISTICS (C
L
= 50pF, Input tr = tf = 6ns)
Guaranteed Limit
Symbol Parameter
V
CC
V
–55 to 25°C ≤85°C ≤125°C Unit
t
PLZ
,
t
PZL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
120
45
24
20
150
60
30
26
180
75
36
31
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
C
in
Maximum Input Capacitance 10 10 10 pF
C
out
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
8.0
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
C
PD
Power Dissipation Capacitance (Per Buffer)*
pF
Page 4
MC74HC03A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
Figure 1. Switching Waveforms
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 2. Test Circuit
1k
Ω
R
pd
V
CC
INPUT A
90%
50%
10%
t
f
t
r
GND
V
CC
OUTPUT Y
t
PZL
t
THL
HIGH
IMPEDANCE
V
OL
10%
t
PLZ
90%
50%
10%
VO, OUTPUT VOLTAGE (VOLTS)
0 1 2 3 4 5
0
5
10
15
20
25
I
D
, SINK CURRENT (mA)
Figure 3. Open–Drain Output Characteristics
A1
B1
A2
B2
An
Bn
1/4
HC03
1/4
HC03
1/4
HC03
Y1
Y2
Yn
TYPICAL
T=25
°
C
T=25°C
T=85°C
T=125°C
EXPECTED MINIMUM*
VCC=5V
*The expected minimum curves are not guarantees, but are design aids.
V
CC
PULLUP
RESISTOR
OUTPUT
OUTPUT = Y1
•
Y2 • . . . • Yn
= A1B1
• A2B2 • . . . • AnBn
Figure 4. Wired AND
LED1
1/4
HC03
LED2
LED
ENABLE
V
CC
+
V
R
–
+
V
F
–
1/4
HC03
V
CC
DESIGN EXAMPLE
CONDITIONS: I
D
^
10mA
USING FIGURE NO TAG TYPICAL
CURVE, at ID=10mA, V
DS
^
0.4V
NR+
VCC*
VF*
V
O
I
D
+
5V*1.7V*0.4V
10mA
USE R = 270
Ω
+
290
W
Figure 5. LED Driver With Blanking
Page 5
MC74HC03A
High–Speed CMOS Logic Data
DL129 — Rev 6
5 MOTOROLA
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
1 7
14 8
B
A
F
H G D
K
C
N
L
J
M
SEATING
PLANE
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
M 0 10 0 10
N 0.015 0.039 0.39 1.01
_ _ _ _
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
0.19
0.10
0
°
5.80
0.25
8.75
4.00
1.75
0.49
1.25
0.25
0.25
7
°
6.20
0.50
0.337
0.150
0.054
0.014
0.016
0.008
0.004
0
°
0.228
0.010
0.344
0.157
0.068
0.019
0.049
0.009
0.009
7
°
0.244
0.019
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
P 7 PL
G
C
K
SEATING
PLANE
D 14 PL
M
J
R
X 45°
1
7
814
0.25 (0.010) T B A
M
S S
B0.25 (0.010)
M M
F
Page 6
MC74HC03A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
6
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
_ _ _ _
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V
S
T
L
–U–
SEATING
PLANE
0.10 (0.004)
–T–
SECTION N–N
DETAIL E
J
J1
K
K1
DETAIL E
F
M
–W–
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
–V–
14X REFK
N
N
Page 7
MC74HC03A
High–Speed CMOS Logic Data
DL129 — Rev 6
7 MOTOROLA
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MC74HC03A/D
*MC74HC03A/D*
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