Datasheet MC74F657BJ, MC74F657BN, MC74F657AN, MC74F657BDW, MC74F657ADW Datasheet (Motorola)
...Page 1
4-247
FAST AND LS TTL DATA
OCTAL BIDIRECTIONAL
TRANSCEIVER WITH 8-BIT PARITY
GENERATOR CHECKER
(3-STATE OUTPUTS)
The MC74F657A and MC74F657B are Octal Bidirectional Transceivers
with an 8-bit parity Generator/Checker and 3-state outputs.
The A and B options are faster versions of the F657 and contain eight noninverting buffers with 3-state outputs and an 8-bit parity generator/checker.
These devices are intended for bus-oriented applications. The buffers have
a guaranteed current sinking capability of 24 mA at the A ports and 64 mA at
the B ports. The Transmit/Receiver (T/R
) input determines the direction of the
data flow through the bidirectional transceivers. Transmit (active HIGH) enables data from A ports to B ports; Receive (active LOW) enables data from
B ports to A ports.
• High-Impedance NPN Base Input for Reduced Loading (20 µA in
HIGH and LOW States)
• Ideal in Applications Where High Output Drive and Light Bus Loading
are Required (IIL is 20 µA versus Fast std of 600 µA)
• Combines F245 and F280A Functions in One Package
• 3-State Outputs
• B Outputs, PARITY, ERROR, Sink 64 mA and Source 15 mA
• 15 mA Source Current
• Input Diodes for Termination Effects
• Glitchless Outputs During Power Up and Power Down
• High Impedance Outputs During Power Off
• ESD Protection > 4000 Volts
PIN ASSIGNMENT
22 21 20 19 18 17
1 2 3 4 5 6
7
24 23
8
OE
T/R
B0B1B2B
3
GNDGND B
4
A0A1A2A3A4VCCA
5
9 10
11
12
A6A
7
ERROR
16 15 14 13
B
5
B
7
B
6
PARITY
ODD/
EVEN
LOGIC SYMBOL
OE
EVEN/ODD
PARITY
T/R
B0B1B2B3B4B5B6B
7
24
11
1
23 22 21 20 17 16 15 14
13
ERROR
12
A0A1A2A3A4A5A6A
7
2 3 4 5 6 8 9 10
MC74F657A,B
OCTAL BIDIRECTIONAL
TRANSCEIVER WITH 8-BIT PARITY
GENERATOR CHECKER
(3-STATE OUTPUTS)
FAST SCHOTTKY TTL
ORDERING INFORMATION
MC74FXXXAJ/BJ Ceramic
MC74FXXXAN/BN Plastic
MC74FXXXADW/BDW SOIC
N SUFFIX
PLASTIC
CASE 724-03
DW SUFFIX
SOIC
CASE 751E-03
24
1
24
1
J SUFFIX
CERAMIC
CASE 758-01
24
1
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FAST AND LS TTL DATA
MC74F657A, B
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 74 4.5 5.0 5.5 V
T
A
Operating Ambient
Temperature Range
74 0 25 70 °C
I
OH
Output Current — High 74 –3.0/–15 mA
I
OL
Output Current — Low 74 24/64 mA
FUNCTION TABLE
Number of
Inputs That are High
Inputs Input/Output Outputs
OE T/R Even/Odd Parity Error Outputs Mode
L H H H Z Transmit
L H L L Z Transmit
L L H H H Receive
0, 2, 4, 6, 8 L L H L L Receive
L L L H L Receive
L L L L H Receive
Number of
Inputs That are High
Inputs Input/Output Outputs
OE T/R Even/Odd Parity Error Outputs Mode
L H H L Z Transmit
L H L H Z Transmit
L L H H L Receive
1, 3, 5, 7 L L H L H Receive
L L L H H Receive
L L L L L Receive
Don’t Care H X X Z Z Z
H = HIGH Voltage Level; L = LOW Voltage Level; X = Don’t Care; Z = HIGH impedance state.
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FAST AND LS TTL DATA
MC74F657A, B
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
V
IH
Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage
V
IL
Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage
V
IK
Input Clamp Diode Voltage –0.73 –1.2 V VCC = MIN, IIN = –18 mA
All Outputs 74 2.4
VCC = 4.5 V
V
OH
2.7 3.4
V
IOH = –3.0 mA
VCC = 4.75 V
Output HIGH Voltage
B0–B7
PARITY,
ERROR
74 2.0 V IOH = –15 mA VCC = 4.5 V
A0–A7 74
0.35 0.5
V
IOL = 24 mA
V
OL
B0–B7
PARITY,
ERROR
74 0.4 0.55 V IOL = 64 mA
T/R, OE, EVEN/ODD 100
µA VCC = 0 V, VIN = 7.0 V
A0–A7 2.0
VCC = 5.5 V, VIN = 5.5 V
B0–B7, PARITY 1.0
mA
VCC = 5.5 V, VIN = 5.5 V
IH
EVEN/ODD 20
T/R, OE 40
µA
VCC = MAX, VIN = 2.7 V
EVEN/ODD –20
IILInput LOW Current
T/R, OE –40
µA
VCC = MAX, VIN = 0.5 V
I
IH
+IOZH
Off-State Current HIGH
Level Voltage Applied
70
VCC = MAX, V
OUT
= 2.7 V
I
IL
+I
OZL
Off-State Current LOW
Level Voltage Applied
B0–B7
PARITY
–70
µA
VCC = MAX, V
OUT
= 0.5 V
I
OZH
Off-State Output Current,
High-Level Voltage Applied
50
VCC = MAX, V
OUT
= 2.7 V
I
OZL
Off-State Output Current,
Low-Level Voltage Applied
–50
µA
VCC = MAX, V
OUT
= 0.5 V
An Outputs –60 –150
Output Short Circuit
Current (Note 2)
PARITY, Bn Outputs,
ERROR
–100 –225
I
CCH
90 135
I
CCL
106 150
CC
I
CCZ
98 145
CC
= MAX
NOTES:
1. For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions for the applicable device type.
2. Not more than one output should be shorted at one time, nor for more than 1 second.
I
IH
I
OS
I
CC
Output LOW Voltage
Input HIGH Current
Total Supply Current
A0–A7
ERROR
mA VCC = MAX, V
mA VCC = MAX
VCC = MIN
= 0 V
OUT
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FAST AND LS TTL DATA
MC74F657A, B
F657A
AC ELECTRICAL CHARACTERISTICS
74F 74F
TA = +25°C
VCC = +5.0 V
CL = 50 pF
TA = 0°C to +70°C
VCC = +5.0 V ± 10%
CL = 50 pF
Symbol
Parameter
Min Typ Max Min Max
Unit
Propagation Delay 2.0 7.0 2.0 7.5
PLH
t
PHL
An to Bn or Bn to A
n
2.0 7.0 2.0 7.5
ns
t
PLH
Propagation Delay 6.0 13 5.5 14
t
PHL
An to PARITY 6.5 13 6.5 14
ns
t
PLH
Propagation Delay 4.5 10.5 4.5 11
t
PHL
EVEN/ODD to PARITY, ERROR 4.5 10.5 4.5 11.5
ns
t
PLH
Propagation Delay 7.0 18 6.5 19
t
PHL
Bn to ERROR 7.0 18 6.5 19
ns
t
PLH
Propagation Delay 8.0 14 7.0 15
t
PHL
PARITY to ERROR 7.0 14 7.0 15
ns
t
PZH
Output Enable Time 3.0 8.0 3.0 9.0
t
PZL
to HIGH or LOW Level 4.0 9.0 4.0 10
ns
Output Disable Time 2.0 7.5 2.0 8.0
PHZ
t
PLZ
from HIGH or LOW Level 2.0 6.0 2.0 6.5
ns
F657B
AC ELECTRICAL CHARACTERISTICS
74F 74F
TA = +25°C
VCC = +5.0 V
CL = 50 pF
TA = 0°C to +70°C
VCC = +5.0 V ± 10%
CL = 50 pF
Symbol
Parameter
Min Typ Max Min Max
Unit
t
PLH
Propagation Delay 2.0 6.0 2.0 6.5
t
PHL
An to Bn or Bn to A
n
2.0 6.0 2.0 6.5
ns
t
PLH
Propagation Delay 4.5 11.5 4.5 13
t
PHL
An to PARITY 4.5 11.5 4.5 13
ns
t
PLH
Propagation Delay 2.0 7.5 2.0 8.5
t
PHL
EVEN/ODD to PARITY, ERROR 2.0 7.5 2.0 8.5
ns
t
PLH
Propagation Delay 4.0 15 3.5 16
t
PHL
Bn to ERROR 4.0 15 3.5 16
ns
t
PLH
Propagation Delay 5.0 11 4.0 12
t
PHL
PARITY to ERROR 5.0 11 4.0 12
ns
t
PZH
Output Enable Time 2.0 7.0 2.0 8.0
t
PZL
to HIGH or LOW Level 2.0 7.0 2.0 8.0
ns
Output Disable Time 2.0 6.0 2.0 6.5
PHZ
t
PLZ
from HIGH or LOW Level 2.0 6.0 2.0 6.5
ns
t
PLH
t
PHZ
t
PHZ
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4-251
FAST AND LS TTL DATA
MC74F657A, B
LOGIC DIAGRAM
T/R
OE
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
EVEN
/ODD
PARITY
ERROR
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