4-92
FAST AND LS TTL DATA
4-BIT ARITHMETIC LOGIC UNIT
The MC54/74F181 is a 4-bit Arithmetic Logic Unit (ALU) which can perform
all the possible 16 logic operations on two variables and a variety of arithmetic
operations. It is 40% faster than the Schottky ALU and only consumes 30%
as much power.
• Provides 16 Arithmetic Operations, ie, Add, Subtract, Compare,
Double, Plus Twelve Other Arithmetic Operations
• Provides all 16 Logic Operations of Two Variables, ie, Exclusive-OR,
Compare, AND, NAND, OR, NOR, Plus Ten Other Logic Operations
• Full Lookahead for High-Speed Arithmetic Operation on Long Words
CONNECTION DIAGRAM
22 21 20 19 18 17
1 2 3 4 5 6
7
24 23
8
V
CC
B
0
A
1B1A2B2
B
3
A
3
G
A
0S3S2S1S0Cn
M
9 10
11
12
F
0F1F2
GND
16 15 14 13
C
n+4
A = BP
F
3
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 54, 74 4.5 5.0 5.5 V
54 –55 25 125
TAOperating Ambient Temperature Range
74 0 25 70
°C
I
OH
Output Current — High 54, 74 –1.0 mA
V
OH
Output Voltage — High
A = B output
54, 74 5.5 V
I
OL
Output Current — Low 54, 74 20 mA
MC54/74F181
4-BIT ARITHMETIC LOGIC UNIT
FAST SCHOTTKY TTL
N SUFFIX
PLASTIC
CASE 724-03
24
1
ORDERING INFORMATION
MC54/74FXXXN Plastic
4-93
FAST AND LS TTL DATA
MC54/74F181
LOGIC SYMBOLS
VCC = PIN 24
GND = PIN 12
ACTIVE-HIGH OPERANDS
2 1 23 22 21 20 19 18
7
8
6
5
4
3
16
14
17
15
9 10 11 13
A0B0A1B1A2B2A3B
3
C
n
M
S
0
S
1
S
2
S
3
F0F1F2F
3
Cn +
4
A = B
G
P
2 1 23 22 21 20 19 18
7
8
6
5
4
3
16
14
17
15
9 10 11 13
A0B0A1B1A2B2A3B
3
C
n
M
S
0
S
1
S
2
S
3
F0F1F2F
3
Cn +
4
A = B
G
P
ACTIVE-LOW OPERANDS
LOGIC DIAGRAM
CnM A
0
B
0
A
1
B1A
2
B2A
3
B
3
S
0
S
1
S
2
S
3
F
0
F
1
A = B F
2
F
3
P
Cn +
4
G
4-94
FAST AND LS TTL DATA
MC54/74F181
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
V
IH
Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage
V
IL
Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage
V
IK
Input Clamp Diode Voltage –1.2 V IIN = –18 mA VCC = MIN
I
OH
Output Current — HIGH 250 µA VOH = 5.5 V VCC = MIN, A = B
54, 74 2.5 3.4 V IOH = –1.0 mA VCC = 4.5 V
VOHOutput HIGH Voltage
74 2.7 3.4 V IOH = –1.0 mA VCC = 4.75 V
V
OL
Output LOW Voltage 0.35 0.5 V IOL = 20 mA VCC = MIN
20 µA VIN = 2.7 V
IIHInput HIGH Current
100 µA VIN = 7.0 V
VCC = MAX
M Input –0.6 mA
A and B Inputs –1.8 mA
IILInput LOW Current
S
0–3
Inputs –2.4 mA
VIN = 0.5 V
VCC = MAX
Cn Input –3.0 mA
I
OS
Output Short Circuit
Current (Note 2)
–60 –150 mA V
OUT
= 0 V VCC = MAX
I
CC
Power Supply Current 43 65 mA VCC = MAX
NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.
FUNCTIONAL DESCRIPTION
The F181 is a 4-bit high-speed parallel Arithmetic Logic Unit
(ALU). Controlled by the four Function Select inputs (S0–S3)
and the Mode Control input (M), it can perform all the 16 possible logic operations or 16 different arithmetic operations on
active-HIGH or active-LOW operands. The Function Table
lists these operations.
When the Mode Control input (M) is HIGH, all internal carries
are inhibited and the device performs logic operations on the
individual bits as listed. When the Mode Control input is LOW,
the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the C
n+4
output, or for carry lookahead
between packages using the signals P
(Carry Propagate) and
G
(Carry Generate). In the Add mode, P indicates that F is 15
or more, while G
indicates that F is 16 or more. In the Subtract
mode, P
indicates that F is zero or less, while G indicates that
F
is less than zero. P and G are not affected by carry in. When
speed requirements are not stringent, it can be used in a simple Ripple Carry mode by connecting the Carry output (C
n+4
)
signal to the Carry input (Cn) of the next unit. For high-speed
operation the device is used in conjunction with a carry lookahead circuit. One carry lookahead package is required for
each group of four F181 devices. Carry lookahead can be provided at various levels and offers high-speed capability over
extremely long word lengths.
The A = B output from the device goes HIGH when all four
F
outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the Subtract mode. The
A = B output is open collector and can be wired-AND with other
A = B outputs to give a comparison for more than four bits. The
A = B signal can be used with the Cn+ 4 signal to indicate A >
B and A < B.
The Function Table lists the arithmetic operations that are
performed without a carry in. An incoming carry adds a one to
each operation. Thus, select code LHHL generates A minus
B minus 1 (2s complement notation) without a carry in and
generates A minus B when a carry is applied. Because subtraction is actually performed by complementary addition (1s
complement), a carry out means borrow
; thus a carry is generated when there is no underflow and no carry is generated
when there is underflow. As indicated, this device can be used
with either active-LOW inputs producing active-LOW outputs
or with active-HIGH inputs producing active-HIGH outputs.
For either case the table lists the operations that are performed
to the operands labeled inside the logic symbol.
4-95
FAST AND LS TTL DATA
MC54/74F181
AC CHARACTERISTICS
54/74F 54F 74F
TA = +25°C TA = –55 to +125°C TA = 0 to +70°C
VCC = +5.0 V VCC = 5.0 V ±10% VCC = 5.0 V ±10%
Parameter CL = 50 pF CL = 50 pF CL = 50 pF
Symbol Path Mode Min Max Min Max Min Max Unit
t
PLH
3.0 8.5 3.0 10.5 3.0 9.5
t
PHL
Cn to Cn +
4
3.0 8.0 3.0 10 3.0 9.0
ns
t
PLH
5.0 13 5.0 15 5.0 14
t
PHL
A or B to Cn +
4
Sum
5.0 12 5.0 14 5.0 13
ns
t
PLH
5.0 14 5.0 16 5.0 15
t
PHL
A or B to Cn +
4
Dif
5.0 13 5.0 15 5.0 14
ns
t
PLH
3.0 8.5 3.0 10.5 3.0 9.5
t
PHL
Cn to F
Any
3.0 8.5 3.0 10.5 3.0 9.5
ns
t
PLH
3.0 7.5 3.0 9.5 3.0 8.5
t
PHL
A or B to G
Sum
3.0 7.5 3.0 9.5 3.0 8.5
ns
t
PLH
3.0 8.5 3.0 10.5 3.0 9.5
t
PHL
A or B to G
Dif
3.0 9.5 3.0 11.5 3.0 10.5
ns
t
PLH
3.0 7.0 3.0 9.0 3.0 8.0
t
PHL
A or B to P
Sum
3.0 7.5 3.0 9.5 3.0 8.5
ns
t
PLH
4.0 7.5 4.0 9.5 4.0 8.5
t
PHL
A or B to P
Dif
3.5 8.5 3.5 10.5 3.5 9.5
ns
t
PLH
3.0 9.0 3.0 11 3.0 10
t
PHL
A
i
or Bi to F
i
Sum
3.0 10 3.0 11 3.0 10
ns
t
PLH
3.0 11 3.0 13 3.0 12
t
PHL
A
i
or Bi to F
i
Dif
3.0 11 3.0 13 3.0 12
ns
t
PLH
Any A or B
4.0 10.5 4.0 12.5 4.0 11.5
t
PHL
to Any F
Sum
4.0 10 4.0 12 4.0 11
ns
t
PLH
Any A or B
4.5 12 4.5 14 4.5 13
t
PHL
to Any F
Dif
4.5 12 4.5 14 4.5 13
ns
t
PLH
4.0 9.0 4.0 11 4.0 10
t
PHL
A or B to F
Logic
4.0 10 4.0 12 4.0 11
ns
t
PLH
11 27 11 31 11 29
t
PHL
A or B to A = B
Dif
7.0 12.5 7.0 14.5 7.0 13.5
ns
4-96
FAST AND LS TTL DATA
MC54/74F181
FUNCTION TABLE
Mode Select
Inputs
Active-LOW Operands
& Fn Outputs
Active-HIGH Operands
& Fn Outputs
S3S2S1S
0
Logic
(M = H)
Arithmetic**
(M = L) (Cn = L)
Logic
(M = H)
Arithmetic**
(M = L) (Cn = H)
L L L L A A minus 1 A A
L L L H AB AB minus 1 A + B A + B
L L H L A + B AB minus 1 AB A + B
L L H H Logic 1 minus 1 Logic 0 minus 1
L H L L A + B A plus (A + B) AB A plus AB
L H L H B AB plus (A + B) B (A + B) plus AB
L H H L A ⊕ B A minus B minus 1 A ⊕ B A minus B minus 1
L H H H A + B A + B AB AB minus 1
H L L L AB A plus (A + B) A + B A plus AB
H L L H A ⊕ B A plus B A ⊕ B A plus B
H L H L B AB plus (A + B) B (A + B) plus AB
H L H H A + B A + B AB AB minus 1
H H L L Logic 0 A plus A* Logic 1 A plus A*
H H L H AB AB plus A A + B (A + B) plus A
H H H L AB AB minus A A + B (A + B) plus A
H H H H A A A A minus 1
*Each bit is shifted to the next more significant position. H = HIGH Voltage Level
**Arithmetic operations expressed in 2s complement notation. L = LOW Voltage Level
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