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查询MC68HC908QL2供应商
MC68HC908QL4
MC68HC908QL3
MC68HC908QL2
Data Sheet
M68HC08
Microcontrollers
MC68HC908QL4
Rev. 4
12/2004
freescale.com
Page 2
Page 3
MC68HC908QL4
MC68HC908QL3
MC68HC908QL2
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History (Sheet 1 of 2)
Date
September,
2003
November,
2003
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Freescale Semiconductor 3
Revision
Level
N/A Initial release N/A
17.3 Functional Operating Range — Corrected operating voltage range 226
17.6 Control Timing — Corrected values for internal operating frequency
and internal clock period
1.0
17.14 5.0-Volt ADC Characteristics — Replaced ADC characteristic table
found in initial release
17.15 3.3-Volt ADC Characteristics — Added 237
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Description
Page
Number(s)
228
236
Page 4
Revision History
Revision History (Sheet 2 of 2)
Date
March,
2004
Revision
Level
2.0
Description
Figure 2-2. Control, Status, and Data Registers
Corrected reset state for the FLASH Block Protect Register.
Corrected reset value for the Internal Oscillator Time Value
Table 7-1. Instruction Set Summary — Added WAIT instruction 83
11.8.1 Oscillator Status and Control Register — Revised description of
ECGON bit for clarity
Table 13-3. Interrupt Sources — Corrected address locations for SLIC,
KBI, and ADC
14.3.5 SLIC Wait (Core Specific) — Revised description for clarity 144
14.3.7 SLIC Stop (Core Specific) — Revised description for clarity 144
14.6.6.2 Byte Transfer Mode Operation — Revised definition of Receiver
Buffer Overrun Error
14.7.1 LIN Message Frame Header — Revised third paragraph of
description
14.14 Sleep and Wakeup Operation — Revised second paragraph of
description
15.8 Input/Output Signals — Corrected reference from PTA0/TCH) to
PTB0/TCH0
Page
Number(s)
33
34
117
140
156
161
174
196
June,
2004
December,
2004
15.8.2 TIM Channel I/O Pins (PTB0/TCH0 and PTA1/TCH1) —
Corrected reference to from PTA0/TCH) to PTB0/TCH0
Figure 16-1. Block Diagram Highlighting BRK and MON Blocks — Added 206
17.5 5-V DC Electrical Characteristics — Updated table notes 227
17.8 5-V Oscillator Characteristics — Updated table notes 230
17.9 3.3-V DC Electrical Characteristics — Updated table notes 231
3.0 Modular sections reworked for clarity. Throughout
Updated to final Freescale format. Corrections per email review.
Replaced ADC chapter with latest.
Table 1-3. Function Priority in Shared Pins — Updated entry for PTA2 23
Figure 1-2. MCU Pin Assignments — Corrected pin assignments for the
4.0
TSSOP packages.
17.11 Oscillator Characteristics — Updated deviation from trimmed
internal oscillator specifications.
17.8 3.3-V DC Electrical Characteristics — Corrected capacitance values 208
17.11 Oscillator Characteristics — Corrected Note 8 211
196
Throughout
21
210
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
4 Freescale Semiconductor
Page 5
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Chapter 3 Analog-to-Digital Converter (ADC10) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chapter 4 Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Chapter 5 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Chapter 6 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Chapter 7 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Chapter 8 External Interrupt (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Chapter 9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Chapter 10 Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Chapter 11 Oscillator Module (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Chapter 12 Input/Output Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Chapter 13 System Integration Module (SIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Chapter 14 Slave LIN Interface Controller (SLIC) Module . . . . . . . . . . . . . . . . . . . . . . . . .133
Chapter 15 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Chapter 16 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
Chapter 17 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Chapter 18 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . .219
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 5
Page 6
List of Chapters
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
6 Freescale Semiconductor
Page 7
Table of Contents
Chapter 1
General Description
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5 Pin Function Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 2
Memory
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4 Direct Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.6 FLASH Memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.6.1 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.6.2 FLASH Page Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6.3 FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.6.4 FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.6.5 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.6.6 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Chapter 3
Analog-to-Digital Converter (ADC10) Module
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.1 Clock Select and Divide Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.2 Input Select and Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.3 Conversion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.3.1 Initiating Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.3.2 Completing Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.3.3 Aborting Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.3.4 Total Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.4 Sources of Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.4.1 Sampling Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.4.2 Pin Leakage Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.4.3 Noise-Induced Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.4.4 Code Width and Quantization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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Table of Contents
3.3.4.5 Linearity Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3.4.6 Code Jitter, Non-Monotonicity and Missing Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.6 ADC10 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.7.1 ADC10 Analog Power Pin (V
3.7.2 ADC10 Analog Ground Pin (V
3.7.3 ADC10 Voltage Reference High Pin (V
3.7.4 ADC10 Voltage Reference Low Pin (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DDA
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SSA
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
REFH
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
REFL
3.7.5 ADC10 Channel Pins (ADn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.8.1 ADC10 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.8.2 ADC10 Result High Register (ADRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.8.3 ADC10 Result Low Register (ADRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.8.4 ADC10 Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 4
Auto Wakeup Module (AWU)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.6.1 Port A I/O Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.6.2 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.6.3 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.6.4 Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.6.5 Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Chapter 5
Configuration Register (CONFIG)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Chapter 6
Computer Operating Properly (COP)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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6.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.1 BUSCLKX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.5 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.7 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.8 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Chapter 7
Central Processor Unit (CPU)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Chapter 8
External Interrupt (IRQ)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8.3.1 MODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
8.3.2 MODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
8.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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8.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.7.1 IRQ Input Pins (IRQ
8.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Chapter 9
Keyboard Interrupt Module (KBI)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9.3.1 Keyboard Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9.3.1.1 MODEK = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
9.3.1.2 MODEK = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.3.2 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.6 KBI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.7.1 KBI Input Pins (KBI5:KBI0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.8.1 Keyboard Status and Control Register (KBSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.8.2 Keyboard Interrupt Enable Register (KBIER). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.8.3 Keyboard Interrupt Polarity Register (KBIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Chapter 10
Low-Voltage Inhibit (LVI)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.3.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.3.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.3.3 LVI Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.3.4 LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.4 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Chapter 11
Oscillator Module (OSC)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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11.3.1 Internal Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.3.1.1 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.3.1.2 XTAL Oscillator Clock (XTALCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.3.1.3 RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.3.1.4 Internal Oscillator Clock (INTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.3.1.5 Bus Clock Times 4 (BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.3.1.6 Bus Clock Times 2 (BUSCLKX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.3.2 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.3.2.1 Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.3.2.2 Internal to External Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.3.2.3 External to Internal Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.3.3 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.3.4 XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.3.5 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.6 OSC During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.7.1 Oscillator Input Pin (OSC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.7.2 Oscillator Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.8.1 Oscillator Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.8.2 Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Chapter 12
Input/Output Ports (PORTS)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.2.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.2.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.2.3 Port A Input Pullup/Down Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.2.4 Port A Summary Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.3.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.3.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.3.3 Port B Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.3.4 Port B Summary Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Chapter 13
System Integration Module (SIM)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.2 RST
13.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.3.2 Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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13.3.3 Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.4.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.5 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.5.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.5.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.6 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.6.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.6.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.6.2.1 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.6.2.2 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
13.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.8.1 SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.8.2 Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Chapter 14
Slave LIN Interface Controller (SLIC) Module
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
14.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
14.5.1 Power Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
14.5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
14.5.3 SLIC Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
14.5.4 SLIC Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
14.5.5 SLIC Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
14.5.6 Wakeup from SLIC Wait with CPU in WAIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
14.5.7 SLIC Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
14.5.8 Normal and Emulation Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
14.5.9 Special Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
14.5.10 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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14.6 SLIC During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
14.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
14.7.1 SLCTX — SLIC Transmit Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
14.7.2 SLCRX — SLIC Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
14.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
14.8.1 SLIC Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
14.8.2 SLIC Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
14.8.3 SLIC Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
14.8.4 SLIC Prescaler Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
14.8.5 SLIC Bit Time Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
14.8.6 SLIC State Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
14.8.6.1 LIN Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
14.8.6.2 Byte Transfer Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
14.8.7 SLIC Data Length Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
14.8.8 SLIC Identifier and Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14.9 Initialization/Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
14.9.1 LIN Message Frame Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
14.9.2 LIN Data Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
14.9.3 LIN Checksum Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
14.9.4 SLIC Module Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
14.9.5 SLCSV Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
14.9.6 SLIC Module Initialization Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
14.9.6.1 LIN Mode Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
14.9.6.2 Byte Transfer Mode Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
14.9.7 Handling LIN Message Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
14.9.7.1 LIN Message Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
14.9.7.2 Possible Errors on Message Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
14.9.8 Handling Command Message Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
14.9.8.1 Standard Command Message Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
14.9.8.2 Extended Command Message Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
14.9.8.3 Possible Errors on Command Message Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
14.9.9 Handling Request LIN Message Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
14.9.9.1 Standard Request Message Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
14.9.9.2 Extended Request Message Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
14.9.9.3 Transmit Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
14.9.9.4 Possible Errors on Request Message Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
14.9.10 Handling IMSG to Minimize Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
14.9.11 Sleep and Wakeup Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
14.9.12 Polling Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
14.9.13 LIN Data Integrity Checking Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
14.9.14 High-Speed LIN Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
14.9.15 Byte Transfer Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
14.9.16 Oscillator Trimming with SLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
14.9.17 Digital Receive Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
14.9.17.1 Digital Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
14.9.17.2 Digital Filter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
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Chapter 15
Timer Interface Module (TIM)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
15.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
15.3.1 TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
15.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
15.3.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
15.3.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
15.3.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
15.3.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
15.3.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
15.3.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
15.3.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
15.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
15.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
15.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
15.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
15.6 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
15.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
15.7.1 TIM Channel I/O Pins (TCH1:TCH0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
15.7.2 TIM Clock Pin (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
15.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
15.8.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
15.8.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
15.8.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
15.8.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
15.8.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Chapter 16
Development Support
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
16.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
16.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
16.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
16.2.1.2 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
16.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
16.2.2 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
16.2.2.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
16.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
16.2.2.3 Break Auxiliary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
16.2.2.4 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
16.2.2.5 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
16.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
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16.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
16.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
16.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
16.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
16.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
16.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
16.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
16.3.1.6 Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
16.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
16.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Chapter 17
Electrical Specifications
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
17.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
17.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
17.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
17.5 5-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
17.6 Typical 5-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
17.7 5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
17.8 3.3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
17.9 Typical 3.3-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
17.10 3.3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
17.11 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
17.12 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
17.13 ADC10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
17.14 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
17.15 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Chapter 18
Ordering Information and Mechanical Specifications
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
18.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
18.3 16-Pin Small Outline Integrated Circuit Package (Case #751G) . . . . . . . . . . . . . . . . . . . . . . . 220
18.4 16-Pin Thin Shrink Small Outline Package (Case #948F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 15
Page 16
Table of Contents
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
16 Freescale Semiconductor
Page 17
Chapter 1
General Description
1.1 Introduction
The MC68HC908QL4 is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and package types.
0.4
Table 1-1. Summary of Device Variations
Device
MC68HC908QL4 4096 bytes 128 bytes 6 ch, 10 bit
MC68HC908QL3 4096 bytes 128 bytes —
MC68HC908QL2 2048 bytes 128 bytes 6 ch, 10 bit
FLASH
Memory Size
RAM
Memory Size
Analog-to-Digital
Converter
1.2 Features
Features include:
• High-performance M68HC08 CPU core
• Fully upward-compatible object code with M68HC05 Family
• 5-V and 3.3-V operating voltages (V
• 8-MHz internal bus operation at 5 V, 4-MHz at 3.3 V
• Software configurable input clock from either internal or external source
• Trimmable internal oscillator
– Selectable 1 MHz, 2 MHz, or 3.2MHz or 6.4 MHz internal bus operation
– 8-bit trim capability
– Trimmable to approximately 0.4%
– ± 25% untrimmed
• Software selectable crystal oscillator range, 32–100 kHz, 1–8 MHz, and 8–32 MHz
• Auto wakeup from STOP capability using dedicated internal 32-kHz RC or bus clock source
DD
)
(1)
• On-chip in-application programmable FLASH memory
– Internal program/erase voltage generation
– Monitor ROM containing user callable program/erase routines
– FLASH security
1. See 17.11 Oscillator Characteristics for internal oscillator specifications
2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
Freescale Semiconductor 17
(2)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Page 18
General Description
• On-chip random-access memory (RAM)
• Slave LIN interface controller (SLIC) module
– Full LIN messaging buffering of Identifier and 8 data bytes
– Automatic baud rate and LIN message frame synchronization:
No prior programming of bit rate required, 1–20 kbps LIN bus speed operation
All LIN messages will be received (no message loss due to synchronization process)
Input clock tolerance as high as ±50%, allowing internal oscillator to remain untrimmed
Incoming break symbols allowed to be 10 to 20 bit times without message loss
Supports automatic software trimming of internal oscillator using LIN synchronization data
– Automatic processing and verification of LIN SYNCH BREAK and SYNCH BYTE
– Automatic checksum calculation and verification with error reporting
– Maximum of 2 interrupts per LIN message frame
– Full LIN error checking and reporting
– High-speed LIN capability up to 83.33 kbps to 120.00 kbps
– Switchable UART-like byte transfer mode for processing bytes one at a time without LIN
message framing constraints
– Configurable digital receive filter
• 2-channel, 16-bit timer interface module (TIM) with external clock source input
• 6-channel, 10-bit analog-to-digital converter (ADC) with internal bandgap reference channel
(ADC10)
• 6-bit keyboard interrupt with wakeup feature (KBI)
– Programmable for rising/falling or high/low level detect
– Software selectable to use internal or external pullup/pulldown device
• External asynchronous interrupt pin with internal pullup (IRQ
• Master asynchronous reset pin with internal pullup (RST
)
)
• 13 bidirectional input/output (I/O) lines and one input only:
– Six shared with keyboard interrupt function
– Six shared with ADC10
– Two shared with TIM
– Two shared with SLIC
– One shared with reset
– One input only shared with external interrupt (IRQ)
– High current sink/source capability
– Selectable pullups on all ports (pullup/down on port A), selectable on an individual bit basis
– Three-state ability on all port pins
• Low-voltage inhibit (LVI) module features:
– Software selectable trip point in CONFIG register
• System protection features:
– Computer operating properly (COP) watchdog
– Low-voltage detection with reset
– Illegal opcode detection with reset
– Illegal address detection with reset
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
18 Freescale Semiconductor
Page 19
• Power-on reset
• Memory mapped I/O registers
• Power saving stop and wait modes
• Available packages:
– 16-pin small outline integrated circuit (SOIC) package
– 16-pin thin shrink small outline package (TSSOP)
Features of the CPU08 include the following:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
MCU Block Diagram
• Efficient C language support
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908QL4.
1.4 Pin Functions
Table 1-2 provides a description of the pin functions.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 19
Page 20
General Description
PTA0/AD0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ
/KBI2/TCLK
PTA3/RST
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
/KBI3
PTB0/TCH0
PTB1
PTB2/AD4
PTB3/AD5
PTB4/SLCRX
PTB5/SLCTX
PTB6
PTB7
MC68HC908QL4
128 BYTES
USER RAM
PTA
PTB
DDRA
DDRB
M68HC08 CPU
MC68HC908QL4
4096 BYTES
USER FLASH
INTERNAL OSC
INTERNAL CLOCK SOURCE
4, 8, 12.8, or 25.6 MHz
KEYBOARD INTERRUPT
MODULE
EXTERNAL INTERRUPT
MODULE
AUTO WAKEUP
MODULE
LOW-VOLTAGE
INHIBIT
2-CHANNEL 16-BIT
TIMER MODULE
COP
MODULE
6-CHANNEL
10-BIT ADC
V
DD
V
SS
RST, IRQ: Pins have internal pull up device
All port pins have programmable pull up device (pullup/down on port A)
PTA[0:5]: Higher current sink and source capability
POWER SUPPLY
Figure 1-1. Block Diagram
SLAVE LIN INTERFACE
CONTROLLER
DEVELOPMENT SUPPORT
MONITOR ROM
BREAK MODULE
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
20 Freescale Semiconductor
Page 21
Pin Functions
V
PTA1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
PTB0/TCH0
PTB3
PTB2
PTB1
V
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST
/KBI3
PTB0/TCH0
PTB3/AD5
PTB2/AD4
PTB1
1
DD
2
3
4
5
6
7
8
16-PIN ASSIGNMENT
MC68HC908QL3 SOIC
1
DD
2
3
4
5
6
7
8
V
16
SS
15
PTA0/KBI0
14
PTA5/OSC1/KBI5
PTA4/OSC2/KBI4
13
PTB4/SLCRx
12
11
PTB5/SLCTx
10
PTB6
PTB7
9
V
16
SS
15
PTA0/AD0/KBI0
14
PTA5/OSC1/AD3/KBI5
PTA4/OSC2/AD2/KBI4
13
PTB4/SLCRx
12
11
PTB5/SLCTx
10
PTB6
PTB7
9
PTA4/OSC2/KBI4
PTA5/OSC1/KBI5
PTA0/KBI0
V
SS
V
PTA1/TCH1/KBI1
PTA2/IRQ
PTA3/RST/KBI3
DD
/KBI2/TCLK
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
PTA0/AD0/KBI0
V
V
PTA1/AD1/TCH1/KBI1
PTA2/IRQ
/KBI2/TCLK
PTA3/RST/KBI3
1
2
3
4
5
6
7
8
16-PIN ASSIGNMENT
MC68HC908QL3 TSSOP
1
2
3
4
SS
DD
5
6
7
8
16
15
14
13
12
11
10
9
9
PTB4/SLCRx
PTB5/SLCTx
PTB6
PTB7
PTB1
PTB2
PTB3
PTB0/TCH0
PTB4/SLCRx
PTB5/SLCTx
PTB6
PTB7
PTB1
PTB2/AD4
PTB3/AD5
PTB0/TCH0
16
15
14
13
12
11
10
16-PIN ASSIGNMENT
MC68HC908QL4 AND MC68HC908QL2 SOIC
Figure 1-2. MCU Pin Assignments
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
16-PIN ASSIGNMENT
MC68HC908QL4 AND MC68HC908QL2 TSSOP
Freescale Semiconductor 21
Page 22
General Description
Table 1-2. Pin Functions
Pin
Name
V
DD
V
SS
Power supply Power
Power supply ground Power
Description Input/Output
PTA0 — General purpose I/O port Input/Output
PTA0
AD0 — A/D channel 0 input Input
KBI0 — Keyboard interrupt input 0 Input
PTA1 — General purpose I/O port Input/Output
PTA1
AD1 — A/D channel 1 input Input
TCH1 — Timer Channel 1 I/O Input/Output
KBI1— Keyboard interrupt input 1 Input
PTA2 — General purpose input-only port Input
IRQ
PTA2
— External interrupt with programmable pullup and Schmitt trigger input Input
KBI2 — Keyboard interrupt input 2 Input
TCLK — External clock source input for the TIM module Input
PTA3 — General purpose I/O port Input/Output
PTA3
RST
— Reset input, active low with internal pullup and Schmitt trigger input Input
KBI3 — Keyboard interrupt input 3 Input
PTA4 — General purpose I/O port Input/Output
PTA4
OSC2 — XTAL oscillator output (XTAL option only)
RC or internal oscillator output (OSC2EN = 1 in PTAPUE register)
Output
Output
AD2 — A/D channel 2 input Input
KBI4 — Keyboard interrupt input 4 Input
PTA5 — General purpose I/O port Input/Output
PTA5
OSC1 — XTAL, RC, or external oscillator input Input
AD3 — A/D channel 3 input Input
KBI5 — Keyboard interrupt input 5 Input
PTB0
PTB0 — General purpose I/O port Input/Output
TCH0 — Timer Channel 0 I/O Input/Output
PTB1 PTB1 — General purpose I/O port Input/Output
PTB2
PTB2 — General purpose I/O port Input/Output
AD4 — A/D channel 4 input Input
PTB3 — General purpose I/O port Input/Output
PTB3
PTB4
AD5 — A/D channel 5 input Input
PTB4 — General purpose I/O port Input/Output
SLCRx — SLC receive input Input
PTB5 — General purpose I/O port Input/Output
PTB5
SLCTx — SLC transmit output Output
PTB6, PTB7 General-purpose I/O port Input/Output
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
22 Freescale Semiconductor
Page 23
Pin Function Priority
1.5 Pin Function Priority
Table 1-3 defines the priority of a shared pin if multiple functions are enabled. Only the shared pins are
shown in the table.
Table 1-3. Function Priority in Shared Pins
Pin Name Highest-to-Lowest Priority Sequence
(1)
PTA0
(1)
PTA1
PTA2 TCLK → IRQ
PTA3 RST
(1)
PTA4
(1)
PTA5
PTB0 TCH0 → PTB0
PTB1 PTB1
(1)
PTB2
(1)
PTB3
PTB4 SLCRx → PTB4
AD0 → TCH1 → KBI0 → PTA0
AD1 → KBI1 → PTA1
→ KBI2 → PTA2
→ KBI3 → PTA3
OSC2 → AD2 → KBI4 → PTA4
OSC1 → AD3 → KBI5 → PTA5
AD4 → PTB2
AD5 → PTB3
(2)
PTB5 SLCTx → PTB5
1. When a pin is to be used as an ADC pin, the I/O port function should be
left as an input. The ADC does not override the port data direction
register.
2. TCLK is not included in the priority scheme. When TCLK is enabled the
other shared functions in the pin should be disabled.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 23
Page 24
General Description
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
24 Freescale Semiconductor
Page 25
Chapter 2
Memory
2.1 Introduction
The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map is shown
in Figure 2-1.
2.2 Unimplemented Memory Locations
Executing code from an unimplemented location will cause an illegal address reset. In Figure 2-1,
unimplemented locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-1, reserved
locations are marked with the word reserved or with the letter R.
2.4 Direct Page Registers
Figure 2-2 shows the memory mapped registers of the MC68HC908QL4. Registers with addresses
between $0000 and $00FF are considered direct page registers and all instructions including those with
direct page addressing modes can access them. Registers between $0100 and $FFFF require non-direct
page addressing modes. See Chapter 7 Central Processor Unit (CPU) for more information on
addressing modes.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 25
Page 26
Memory
$0000
↓
$0051
$0052
↓
$007F
$0080
↓
$00FF
$0100
↓
$2B7D
$2B7E
↓
$2E1F
$2E20
↓
$EDFF
$EE00
↓
$FDFF
$FE00
↓
$FE0F
$FE00
↓
$FE0F
$FE10
↓
$FF7D
$FF7E
↓
$FFBD
$FFBE
↓
$FFC1
$FFC2
↓
$FFCF
$FFD0
↓
$FFFF
DIRECT PAGE REGISTERS
81 BYTES
UNIMPLEMENTED
47 BYTES
RAM
128 BYTES
UNIMPLEMENTED
10,878 BYTES
AUXILIARY ROM
674 BYTES
UNIMPLEMENTED
49120 BYTES
FLASH MEMORY
4096 BYTES
MISCELLANEOUS REGISTERS
16 BYTES
UNIMPLEMENTED
16 BYTES
MONITOR ROM
350 BYTES
UNIMPLEMENTED
64 BYTES
MISCELLANEOUS REGISTERS
4 BYTES
UNIMPLEMENTED
14 BYTES
USER VECTORS
48 BYTES
RESERVED
2048 BYTES
FLASH MEMORY
2048 BYTES
$EE00
↓
$F5FF
$F600
↓
$FDFF
MC68HC908QL4, MC68HC908QL3
Memory Map
MC68HC908QL2
Memory Map
Figure 2-1. Memory Map
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
26 Freescale Semiconductor
Page 27
Direct Page Registers
Addr.Register Name Bit 7654321Bit 0
$0000
$0001
$0002
↓
$0003
Port A Data Register
(PTA)
See page 112.
Port B Data Register
(PTB)
See page 114.
Reserved
Read: 0 AWUL
Write:
Reset:U0 UUUUUU
Read:
Write:
Reset: Unaffected by reset
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
PTA5 PTA4 PTA3
PTA2
PTA1 PTA0
$0004
$0005
$0006
↓
$000A
$000B
$000C
$000D
↓
$0019
Data Direction Register A
(DDRA)
See page 112.
Data Direction Register B
(DDRB)
See page 115.
Reserved
Port A Input Pullup/Down
Enable Register (PTAPUE)
See page 113.
Port B Input Pullup Enable
Register (PTBPUE)
See page 116.
Reserved
Read: 0 0
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
OSC2EN
PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE1 PTBPUE0
0
DDRA5 DDRA4 DDRA3
PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
0
DDRA1 DDRA0
Read:0000KEYF0
Write: ACKK
Reset:00000000
Read: 0
Write:
Reset:00000000
AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
= Unimplemented R = Reserved U = Unaffected
IMASKK MODEK
$001A
$001B
Keyboard Status and
Control Register (KBSCR)
See page 94.
Keyboard Interrupt
Enable Register (KBIER)
See page 95.
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 7)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 27
Page 28
Memory
Addr.Register Name Bit 7654321Bit 0
Read: 0 0
Write:
KBIP5 KBIP4 KBIP3 KBIP2 KBIP1 KBIP0
Reset:00000000
Read:0000IRQF0
Write:
ACK
IMASK MODE
Reset:00000000
Read:
(1)
IRQPUDIRQENRRRR
Write:
Reset:00000000
OSCENIN-
STOP
RSTEN
(2)
$001C
$001D
$001E
Keyboard Interrupt
Polarity Register (KBIPR)
See page 95.
IRQ Status and Control
Register (INTSCR)
See page 87.
Configuration Register 2
(CONFIG2)
See page 63.
1. One-time writable register after each reset.
2. RSTEN reset to 0 by a power-on reset (POR) only.
$001F
$0020
$0021
$0022
$0023
$0024
$0025
Configuration Register 1
(CONFIG1)
See page 64.
TIM Status and Control
Register (TSC)
See page 180.
TIM Counter Register High
(TCNTH)
See page 182.
TIM Counter Register
Low (TCNTL)
See page 182.
TIM Counter Modulo
Register High (TMODH)
See page 182.
TIM Counter Modulo
Register Low (TMODL)
See page 182.
TIM Channel 0 Status and
Control Register (TSC0)
See page 183.
Read:
(1)
Write:
Reset:00000
COPRS LVISTOP LVIRSTD LVIPWRD LVITRIP SSREC STOP COPD
(2)
000
1. One-time writable register after each reset.
2. LVITRIP reset to 0 by a power-on reset (POR) only.
Read: TOF
Write: 0 TRST
TOIE TSTOP
00
PS2 PS1 PS0
Reset:00100000
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:00000000
Read:Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:00000000
Read:
Write:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reset:11111111
Read:
Write:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Reset:11111111
Read: CH0F
Write: 0
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Reset:00000000
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 7)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
28 Freescale Semiconductor
Page 29
Direct Page Registers
Addr.Register Name Bit 7654321Bit 0
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: CH1F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
CH1IE
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0
MS1A ELS1B ELS1A TOV1 CH1MAX
$0026
$0027
$0028
$0029
$002A
$002B
↓
$0035
TIM Channel 0
Register High (TCH0H)
See page 185.
TIM Channel 0
Register Low (TCH0L)
See page 185.
TIM Channel 1 Status and
Control Register (TSC1)
See page 183.
TIM Channel 1
Register High (TCH1H)
See page 185.
TIM Channel 1
Register Low (TCH1L)
See page 185.
Reserved
Oscillator Status and Control
$0036
$0037 Reserved
$0038
$0039
↓
$003B
$003C
$003D
Register (OSCSC)
See page 108.
Oscillator Trim Register
(OSCTRIM)
See page 109.
Reserved
ADC10 Status and Control
Register (ADSCR)
See page 52.
ADC10 Data Register High
(ADRH)
See page 54.
Read:
OSCOPT1 OSCOPT0 ICFS1 ICFS0 ECFS1 ECFS0 ECGON
Write:
Reset:00100000
Read:
Write:
Reset:10000000
Read: COCO
Write:
Reset:00011111
Read:000000AD9AD8
Write:RRRRRRRR
Reset:00000000
TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
= Unimplemented R = Reserved U = Unaffected
ECGST
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 7)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 29
Page 30
Memory
Addr.Register Name Bit 7654321Bit 0
Read:AD7AD6AD5AD4AD3AD2AD1AD0
Write:RRRRRRRR
Reset:00000000
Read:
Write:
Reset:00000000
Read: 0 0
Write:
Reset:00100000
Read:0000
Write:
Reset:00000000
Read:SLCACT0INITACK0000
Write:
Reset:00100000
Read:
Write:
Reset:10000000
Read: 0 0 0
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: 0 0 I3 I2 I1 I0 0 0
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset:00000000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset:00000000
ADLPC ADIV1 ADIV0 ADICLK MODE1 MODE0 ADLSMP ADACKEN
INITREQ
RXFP1 RXFP0
BT7 BT6 BT5 BT4 BT3 BT2 BT1
TXGO CHKMOD DLC5 DLC4 DLC3 DLC2 DLC1 DLC0
= Unimplemented R = Reserved U = Unaffected
000000
0
WAKETX TXABRT IMSG SLCIE
SLCWCM BTM
BT12 BT11 BT10 BT9 BT8
0
SLCE
SLCF
0
$003E
$003F
$0040
$0041
$0042
$0043
$0044
$0045
$0046
$0047
$0048
$0049
ADC10 Data Register Low
(ADRL)
See page 54.
ADC10 Clock Register
(ADCLK)
See page 55.
SLIC Control Register 1
(SLCC1)
See page 139.
SLIC Control Register 2
(SLCC2)
See page 140.
SLIC Status Register
(SLCS)
See page 141.
SLIC Prescale Register
(SLCP)
See page 142.
SLIC Bit Time Register High
(SLCBTH)
See page 143.
SLIC Bit Time Register Low
(SLCBTL)
See page 143.
SLIC State Vector Register
(SLCSV)
See page 144.
SLIC Data Length Code
Register (SLCDLC)
See page 148.
SLIC Identifier Register
(SLCID)
See page 149.
SLIC Data Register 7
(SLCD7)
See page 149.
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 7)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
30 Freescale Semiconductor
Page 31
Direct Page Registers
Addr.Register Name Bit 7654321Bit 0
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset:00000000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset:00000000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset:00000000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset:00000000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset:00000000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset:00000000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset:00000000
$004A
$004B
$004C
$004D
$004E
$004F
$0050
$0051
↓
$005F
SLIC Data Register 6
(SLCD6)
See page 149.
SLIC Data Register 5
(SLCD5)
See page 149.
SLIC Data Register 4
(SLCD4)
See page 149.
SLIC Data Register 3
(SLCD3)
See page 149.
SLIC Data Register 2
(SLCD2)
See page 149.
SLIC Data Register 1
(SLCD1)
See page 149.
SLIC Data Register 0
(SLCD0)
See page 149.
Reserved
$FE00
$FE01
$FE02
Break Status Register
(BSR)
See page 191.
SIM Reset Status Register
(SRSR)
See page 131.
Break Auxiliary
Register (BRKAR)
See page 191.
Read:
Write: See note 1
Reset: 0
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR:10000000
Read:0000000
Write:
Reset:00000000
RRRRRR
1. Writing a 0 clears SBSW.
= Unimplemented R = Reserved U = Unaffected
SBSW
R
BDCOP
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 7)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 31
Page 32
Memory
Addr.Register Name Bit 7654321Bit 0
Break Flag Control
$FE03
Interrupt Status Register 1
$FE04
Interrupt Status Register 2
$FE05
Interrupt Status Register 3
$FE06
$FE07 Reserved
Register (BFCR)
See page 191.
See page 127.
See page 127.
See page 128.
Read:
Write:
Reset: 0
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
(INT1)
Write:RRRRRRRR
Reset:00000000
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
(INT2)
Write:RRRRRRRR
Reset:00000000
Read: IF22 IF21 IF20 IF19 IF18 IF17 IF16 IF15
(INT3)
Write:RRRRRRRR
Reset:00000000
BCFERRRRRRR
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
↓
$FE0F
FLASH Control Register
(FLCR)
See page 35.
Break Address High
Register (BRKH)
See page 190.
Break Address Low
Register (BRKL)
See page 190.
Break Status and Control
Register (BRKSCR)
See page 191.
LVI Status Register
(LVISR)
See page 99.
Reserved
Read:0000
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:LVIOUT000000R
Write:
Reset:00000000
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
BRKE BRKA
000000
HVEN MASS ERASE PGM
$FFBE
FLASH Block Protect
Register (FLBPR)
See page 40.
Read:
Write:
Reset: Unaffected by reset
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1
= Unimplemented R = Reserved U = Unaffected
0
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 7)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
32 Freescale Semiconductor
Page 33
Direct Page Registers
Addr.Register Name Bit 7654321Bit 0
$FFBF Reserved
$FFC0
$FFC1 Reserved
$FFFF
Internal Oscillator Trim
Value (Optional)
COP Control Register
(COPCTL)
See page 69.
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 7)
Vector Priority Vector Address Vector
Lowest
Read:
Write:
Reset: Resets to factory programmed value
Read: LOW BYTE OF RESET VECTOR
Write: WRITING CLEARS COP COUNTER (ANY VALUE)
Reset: Unaffected by reset
TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0
= Unimplemented R = Reserved U = Unaffected
Table 2-1. Vector Addresses
IF22–IF16 $FFD0,1–$FFDC,D Unused vectors
IF15 $FFDE,F ADC conversion complete vector
IF14 $FFE0,1 Keyboard vector
IF13 $FFE2,3 Unused vector
IF12 $FFE4,5 Unused vector
IF11 $FFE6,7 Unused vector
IF10 $FFE8,9 Unused vector
IF9 $FFEA,B SLIC vector
IF8 $FFFC,D Unused vector
IF7 $FFEE,F Unused vector
IF6 $FFF0,1 Unused vector
IF5 $FFF2,3 TIM overflow vector
IF4 $FFF4,5 TIM channel 1 vector
IF3 $FFF6,7 TIM channel 0 vector
IF2 $FFF8,9 Unused vector
IF1 $FFFA,B IRQ
— $FFFC,D SWI vector
Highest
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
— $FFFE,F Reset vector
vector
Freescale Semiconductor 33
Page 34
Memory
2.5 Random-Access Memory (RAM)
This MCU includes static RAM. The locations in RAM below $0100 can be accessed using the more
efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation
instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program
variables in this area of RAM is preferred.
The RAM retains data when the MCU is in low-power wait or stop mode. At power-on, the contents of
RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop
below the minimum value for RAM retention.
For compatibility with older M68HC05 MCUs, the HC08 resets the stack pointer to $00FF. In the devices
that have RAM above $00FF, it is usually best to reinitialize the stack pointer to the top of the RAM so the
direct page RAM can be used for frequently accessed RAM variables and bit-addressable program
variables.
Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated
to the highest address of the RAM).
LDHX #RamLast+1 ;point one past RAM
TXS ;SP<-(H:X-1)
2.6 FLASH Memory (FLASH)
The FLASH memory is intended primarily for program storage. In-circuit programming allows the
operating program to be loaded into the FLASH memory after final assembly of the application product.
It is possible to program the entire array through the single-wire monitor mode interface. Because no
special voltages are needed for FLASH erase and programming operations, in-application programming
is also possible through other software-controlled communication paths.
This subsection describes the operation of the embedded FLASH memory. The FLASH memory can be
read, programmed, and erased from the internal V
enabled through the use of an internal charge pump.
The minimum size of FLASH memory that can be erased is 64 bytes; and the maximum size of FLASH
memory that can be programmed in a program cycle is 32 bytes (a row). Program and erase operations
are facilitated through control bits in the FLASH control register (FLCR). Details for these operations
appear later in this section.
An erased bit reads as a 1 and a programmed bit reads as a 0. A security
feature prevents viewing of the FLASH contents.
supply. The program and erase operations are
DD
NOTE
(1)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult
for unauthorized users.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
34 Freescale Semiconductor
Page 35
FLASH Memory (FLASH)
2.6.1 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operations.
Bit 7654321Bit 0
Read:0000
Write:
Reset:00000000
= Unimplemented
Figure 2-3. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the memory for either program or
erase operation. It can only be set if either PGM =1 or ERASE = 1 and the proper sequence for
program or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation.
1 = Mass erase operation selected
0 = Mass erase operation unselected
HVEN MASS ERASE PGM
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit
such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE
bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 35
Page 36
Memory
2.6.2 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes
starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 48-byte user interrupt vectors area also
forms a page. Any FLASH memory page can be erased alone.
1. Set the ERASE bit and clear the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range of the block to be erased.
4. Wait for a time, t
5. Set the HVEN bit.
6. Wait for a time, t
7. Clear the ERASE bit.
8. Wait for a time, t
9. Clear the HVEN bit.
10. After time, t
RCV,
The COP register at location $FFFF should not be written between steps
5-9, when the HVEN bit is set. Since this register is located at a valid
FLASH address, unpredictable behavior may occur if this location is written
while HVEN is set.
.
NVS
.
Erase
.
NVH
the memory can be accessed in read mode again.
NOTE
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, other unrelated operations may
occur between the steps.
CAUTION
A page erase of the vector page will erase the internal oscillator trim value at $FFC0.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
36 Freescale Semiconductor
Page 37
2.6.3 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory to read as a 1:
1. Set both the ERASE bit and the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address
4. Wait for a time, t
NVS
.
5. Set the HVEN bit.
6. Wait for a time, t
MErase
.
7. Clear the ERASE and MASS bits.
Mass erase is disabled whenever any block is protected (FLBPR does not
equal $FF).
(1)
within the FLASH memory address range.
NOTE
FLASH Memory (FLASH)
8. Wait for a time, t
NVHL
.
9. Clear the HVEN bit.
10. After time, t
the memory can be accessed in read mode again.
RCV,
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, other unrelated operations may
occur between the steps.
CAUTION
A mass erase will erase the internal oscillator trim value at $FFC0.
1. When in monitor mode, with security sequence failed (see 16.3.2 Security), write to the FLASH block protect register
instead of any FLASH address.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 37
Page 38
Memory
2.6.4 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes
starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, or $XXE0. Use the
following step-by-step procedure to program a row of FLASH memory
Figure 2-4 shows a flowchart of the programming algorithm.
NOTE
Do not program any byte in the FLASH more than once after a successful
erase operation. Reprogramming bits to a byte which is already
programmed is not allowed without first erasing the page in which the byte
resides or mass erasing the entire FLASH memory. Programming without
first erasing may disturb data stored in the FLASH.
1. Set the PGM bit. This configures the memory for program operation and enables the latching of
address and data for programming.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range desired.
4. Wait for a time, t
5. Set the HVEN bit.
6. Wait for a time, t
7. Write data to the FLASH address being programmed
8. Wait for time, t
9. Repeat step 7 and 8 until all desired bytes within the row are programmed.
10. Clear the PGM bit
11. Wait for time, t
12. Clear the HVEN bit.
13. After time, t
RCV
The COP register at location $FFFF should not be written between steps
5-12, when the HVEN bit is set. Since this register is located at a valid
FLASH address, unpredictable behavior may occur if this location is written
while HVEN is set.
.
NVS
.
PGS
PROG
NVH
(1)
.
.
.
(1)
.
, the memory can be accessed in read mode again.
NOTE
This program sequence is repeated throughout the memory until all data is programmed.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed t
maximum, see 17.15
PROG
Memory Characteristics.
1. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing
PGM bit, must not exceed the maximum programming time, t
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
38 Freescale Semiconductor
PROG
maximum.
Page 39
FLASH Memory (FLASH)
Algorithm for Programming
a Row (32 Bytes) of FLASH Memory
1
2
READ THE FLASH BLOCK PROTECT REGISTER
3
WRITE ANY DATA TO ANY FLASH ADDRESS
WITHIN THE ROW ADDRESS RANGE DESIRED
4
5
6
7
WRITE DATA TO THE FLASH ADDRESS
8
SET PGM BIT
WAIT FOR A TIME, t
SET HVEN BIT
WAIT FOR A TIME, t
TO BE PROGRAMMED
WAIT FOR A TIME, t
NVS
PGS
PROG
9
PROGRAMMING
NOTES:
The time between each FLASH address change (step 7 to step 7 loop),
,
or the time between the last FLASH address programmed
to clearing PGM bit (step 7 to step 10)
must not exceed the maximum programming
PROG
max.
time, t
This row program algorithm assumes the row/s
to be programmed is initially erased.
Figure 2-4. FLASH Programming Flowchart
COMPLETED
THIS ROW?
N
Y
10
11
12
13
CLEAR PGM BIT
WAIT FOR A TIME, t
CLEAR HVEN BIT
WAIT FOR A TIME, t
END OF PROGRAMMING
NVH
RCV
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 39
Page 40
Memory
2.6.5 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, a provision is made to protect blocks of memory from unintentional erase or program
operations due to system malfunction. This protection is done by use of a FLASH block protect register
(FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range
of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH
memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either erase or program
operations.
NOTE
In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.
When the FLBPR is programmed with all 0 s, the entire memory is protected from being programmed and
erased. When all the bits are erased (all 1’s), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of memory. The address ranges are
shown in 2.6.6 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than
$FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass
erase is disabled whenever any block is protected (FLBPR does not equal $FF). The FLBPR itself can be
erased or programmed only with an external voltage, V
allows entry from reset into monitor mode.
, present on the IRQ pin. This voltage also
TST
2.6.6 FLASH Block Protect Register
The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore can
only be written during a programming sequence of the FLASH memory. The value in this register
determines the starting address of the protected range within the FLASH memory.
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset. Initial value from factory is $FF.
Write to this register is by a programming sequence to the FLASH memory.
BPR[7:0] — FLASH Protection Register Bits [7:0]
These eight bits in FLBPR represent bits [13:6] of a 16-bit memory address. Bits [15:14] are 1s and
bits [5:0] are 0s.
The resultant 16-bit address is used for specifying the start address of the FLASH memory for block
protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF.
With this mechanism, the protect start address can be $XX00, $XX40, $XX80, or $XXC0 within the
FLASH memory. See Figure 2-6 and Table 2-2.
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Figure 2-5. FLASH Block Protect Register (FLBPR)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
40 Freescale Semiconductor
Page 41
16-BIT MEMORY ADDRESS
FLASH Memory (FLASH)
START ADDRESS OF
FLASH BLOCK PROTECT
FLBPR VALUE
Figure 2-6. FLASH Block Protect Start Address
Table 2-2. Examples of Protect Start Address
BPR[7:0]
$00–$B8 The entire FLASH memory is protected.
$B9 (1011 1001) $EE40 (1110 1110 0100 0000)
$BA (1011 1010) $EE80 (1110 1110 1000 0000)
$BB (1011 1011) $EEC0 (1110 1110 1100 0000)
$BC (1011 1100) $EF00 (1110 1111 0000 0000)
$DE (1101 1110)$F780 (1111 0111 1000 0000)
$DF (1101 1111)$F7C0 (1111 0111 1100 0000)
$FE (1111 1110)
$FF The entire FLASH memory is not protected.
1. The end address of the protected range is always $FFFF.
Start of Address of Protect Range
and so on...
$FF80 (1111 1111 1000 0000)
FLBPR, OSCTRIM, and vectors are protected
0
00011
(1)
0
0
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 41
Page 42
Memory
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
42 Freescale Semiconductor
Page 43
Chapter 3
Analog-to-Digital Converter (ADC10) Module
3.1 Introduction
This section describes the 10-bit successive approximation analog-to-digital converter (ADC10).
The ADC10 module shares its pins with general-purpose input/output (I/O) port pins. See Figure 3-1 for
port location of these shared pins. The ADC10 on this MCU uses V
pins. This MCU uses BUSCLKX4 as its alternate clock source for the ADC. This MCU does not have a
hardware conversion trigger.
3.2 Features
Features of the ADC10 module include:
• Linear successive approximation algorithm with 10-bit resolution
• Output formatted in 10- or 8-bit right-justified format
• Single or continuous conversion (automatic power-down in single conversion mode)
• Configurable sample time and conversion speed (to save power)
• Conversion complete flag and interrupt
• Input clock selectable from up to three sources
• Operation in wait and stop modes for lower noise operation
• Selectable asynchronous hardware conversion trigger
and VSS as its supply and reference
DD
3.3 Functional Description
The ADC10 uses successive approximation to convert the input sample taken from ADVIN to a digital
representation. The approximation is taken and then rounded to the nearest 10- or 8-bit value to provide
greater accuracy and to provide a more robust mechanism for achieving the ideal code-transition voltage.
Figure 3-2 shows a block diagram of the ADC10
For proper conversion, the voltage on ADVIN must fall between V
or exceeds V
a 8-bit representation. If ADVIN is equal to or less than V
Input voltages between V
Freescale Semiconductor 43
, the converter circuit converts the signal to $3FF for a 10-bit representation or $FF for
REFH
the converter circuit converts it to $000.
REFL,
and V
REFH
Input voltage must not exceed the analog supply voltages.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
are straight-line linear conversions.
REFL
NOTE
REFH
and V
. If ADVIN is equal to
REFL
Page 44
Analog-to-Digital Converter (ADC10) Module
PTA0/AD0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ
/KBI2/TCLK
PTA3/RST
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
/KBI3
PTB0/TCH0
PTB1
PTB2/AD4
PTB3/AD5
PTB4/SLCRX
PTB5/SLCTX
PTB6
PTB7
MC68HC908QL4
128 BYTES
USER RAM
PTA
PTB
DDRA
DDRB
M68HC08 CPU
MC68HC908QL4
4096 BYTES
USER FLASH
INTERNAL OSC
INTERNAL CLOCK SOURCE
4, 8, 12.8, or 25.6 MHz
KEYBOARD INTERRUPT
MODULE
EXTERNAL INTERRUPT
MODULE
AUTO WAKEUP
MODULE
LOW-VOLTAGE
INHIBIT
2-CHANNEL 16-BIT
TIMER MODULE
COP
MODULE
6-CHANNEL
10-BIT ADC
V
DD
V
SS
RST, IRQ: Pins have internal pull up device
All port pins have programmable pull up device (pullup/down on port A)
PTA[0:5]: Higher current sink and source capability
POWER SUPPLY
Figure 3-1. Block Diagram Highlighting ADC10 Block and Pins
SLAVE LIN INTERFACE
CONTROLLER
DEVELOPMENT SUPPORT
MONITOR ROM
BREAK MODULE
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
44 Freescale Semiconductor
Page 45
Functional Description
MCU STOP
ADHWT
AD0
ADn
V
REFH
V
REFL
ADLPC
ADCLK
ADCK
ADIV
CLOCK
DIVIDE
AIEN
COCO
ADICLK
ACLKEN
ACLK
1
2
ASYNC
CLOCK
GENERATOR
BUS CLOCK
ALTERNATE CLOCK SOURCE
INTERRUPT
ADCSC
AIEN
1 2
ADCH
• • •
ADVIN
ADCO
COCO
COMPLETE
CONTROL SEQUENCER
INITIALIZE
MODE
ADLSMP
SAMPLE
DATA REGISTERS ADRH:ADRL
ABORT
CONVERT
TRANSFER
SAR CONVERTER
Figure 3-2. ADC10 Block Diagram
The ADC10 can perform an analog-to-digital conversion on one of the software selectable channels. The
output of the input multiplexer (ADVIN) is converted by a successive approximation algorithm into a 10-bit
digital result. When the conversion is completed, the result is placed in the data registers (ADRH and
ADRL). In 8-bit mode, the result is rounded to 8 bits and placed in ADRL. The conversion complete flag
is then set and an interrupt is generated if the interrupt has been enabled.
3.3.1 Clock Select and Divide Circuit
The clock select and divide circuit selects one of three clock sources and divides it by a configurable value
to generate the input clock to the converter (ADCK). The clock can be selected from one of the following
sources:
• The asynchronous clock source (ACLK) — This clock source is generated from a dedicated clock
source which is enabled when the ADC10 is converting and the clock source is selected by setting
the ACLKEN bit. When the ADLPC bit is clear, this clock operates from 1–2 MHz; when ADLPC is
set it operates at 0.5–1 MHz. This clock is not disabled in STOP and allows conversions in stop
mode for lower noise operation.
• Alternate Clock Source — This clock source is equal to the external oscillator clock or a four times
the bus clock. The alternate clock source is MCU specific, see 3.1 Introduction to determine source
and availability of this clock source option. This clock is selected when ADICLK and ACLKEN are
both low.
• The bus clock — This clock source is equal to the bus frequency. This clock is selected when
ADICLK is high and ACLKEN is low.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 45
Page 46
Analog-to-Digital Converter (ADC10) Module
Whichever clock is selected, its frequency must fall within the acceptable frequency range for ADCK. If
the available clocks are too slow, the ADC10 will not perform according to specifications. If the available
clocks are too fast, then the clock must be divided to the appropriate frequency. This divider is specified
by the ADIV[1:0] bits and can be divide-by 1, 2, 4, or 8.
3.3.2 Input Select and Pin Control
Only one analog input may be used for conversion at any given time. The channel select bits in ADCSC
are used to select the input signal for conversion.
3.3.3 Conversion Control
Conversions can be performed in either 10-bit mode or 8-bit mode as determined by the MODE bits.
Conversions can be initiated by either a software or hardware trigger. In addition, the ADC10 module can
be configured for low power operation, long sample time, and continuous conversion.
3.3.3.1 Initiating Conversions
A conversion is initiated:
• Following a write to ADCSC (with ADCH bits not all 1s) if software triggered operation is selected.
• Following a hardware trigger event if hardware triggered operation is selected.
• Following the transfer of the result to the data registers when continuous conversion is enabled.
If continuous conversions are enabled a new conversion is automatically initiated after the completion of
the current conversion. In software triggered operation, continuous conversions begin after ADCSC is
written and continue until aborted. In hardware triggered operation, continuous conversions begin after a
hardware trigger event and continue until aborted.
3.3.3.2 Completing Conversions
A conversion is completed when the result of the conversion is transferred into the data result registers,
ADRH and ADRL. This is indicated by the setting of the COCO bit. An interrupt is generated if AIEN is
high at the time that COCO is set.
A blocking mechanism prevents a new result from overwriting previous data in ADRH and ADRL if the
previous data is in the process of being read while in 10-bit mode (ADRH has been read but ADRL has
not). In this case the data transfer is blocked, COCO is not set, and the new result is lost. When a data
transfer is blocked, another conversion is initiated regardless of the state of ADCO (single or continuous
conversions enabled). If single conversions are enabled, this could result in several discarded
conversions and excess power consumption. To avoid this issue, the data registers must not be read after
initiating a single conversion until the conversion completes.
3.3.3.3 Aborting Conversions
Any conversion in progress will be aborted when:
• A write to ADCSC occurs (the current conversion will be aborted and a new conversion will be
initiated, if ADCH are not all 1s).
• A write to ADCLK occurs.
• The MCU is reset.
• The MCU enters stop mode with ACLK not enabled.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
46 Freescale Semiconductor
Page 47
Functional Description
When a conversion is aborted, the contents of the data registers, ADRH and ADRL, are not altered but
continue to be the values transferred after the completion of the last successful conversion. In the case
that the conversion was aborted by a reset, ADRH and ADRL return to their reset states.
Upon reset or when a conversion is otherwise aborted, the ADC10 module will enter a low power, inactive
state. In this state, all internal clocks and references are disabled. This state is entered asynchronously
and immediately upon aborting of a conversion.
3.3.3.4 Total Conversion Time
The total conversion time depends on many factors such as sample time, bus frequency, whether
ACLKEN is set, and synchronization time. The total conversion time is summarized in Table 3-1.
Table 3-1. Total Conversion Time versus Control Conditions
Conversion Mode ACLKEN Maximum Conversion Time
8-Bit Mode (short sample — ADLSMP = 0):
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
8-Bit Mode (long sample — ADLSMP = 1):
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
10-Bit Mode (short sample — ADLSMP = 0):
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
10-Bit Mode (long sample — ADLSMP = 1):
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
Bus
Bus
Bus
Bus
≥ f
≥ f
≥ f
≥ f
ADCK
ADCK
ADCK
ADCK
)
)
)
)
0
1
X
0
1
X
0
1
X
0
1
X
18 ADCK + 3 bus clock
18 ADCK + 3 bus clock + 5 µs
16 ADCK
38 ADCK + 3 bus clock
38 ADCK + 3 bus clock + 5 µs
36 ADCK
21 ADCK + 3 bus clock
21 ADCK + 3 bus clock + 5 µs
19 ADCK
41 ADCK + 3 bus clock
41 ADCK + 3 bus clock + 5 µs
39 ADCK
The maximum total conversion time for a single conversion or the first conversion in continuous
conversion mode is determined by the clock source chosen and the divide ratio selected. The clock
source is selectable by the ADICLK and ACLKEN bits, and the divide ratio is specified by the ADIV bits.
For example, if the alternate clock source is 16 MHz and is selected as the input clock source, the input
clock divide-by-8 ratio is selected and the bus frequency is 4 MHz, then the conversion time for a single
10-bit conversion is:
Maximum Conversion time =
21 ADCK cycles
16 MHz/8
3 bus cycles
+
4 MHz
= 11.25 µs
Number of bus cycles = 11.25 µs x 4 MHz = 45 cycles
NOTE
The ADCK frequency must be between f
minimum and f
ADCK
ADCK
maximum to meet A/D specifications.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 47
Page 48
Analog-to-Digital Converter (ADC10) Module
3.3.4 Sources of Error
Several sources of error exist for ADC conversions. These are discussed in the following sections.
3.3.4.1 Sampling Error
For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given
the maximum input resistance of approximately 15 kΩ and input capacitance of approximately 10 pF,
sampling to within
LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles / 2 MHz
1/4
maximum ADCK frequency) provided the resistance of the external analog source (R
kΩ. Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase
the sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time.
3.3.4.2 Pin Leakage Error
) is kept below 10
AS
Leakage on the I/O pins can cause conversion error if the external analog source resistance (R
If this error cannot be tolerated by the application, keep R
LSB leakage error (at 10-bit resolution).
1/4
lower than V
AS
ADVIN
/ (4096*I
Leak
) is high.
AS
) for less than
3.3.4.3 Noise-Induced Errors
System noise which occurs during the sample or conversion process can affect the accuracy of the
conversion. The ADC10 accuracy numbers are guaranteed as specified only if the following conditions
are met:
• There is a 0.1µF low-ESR capacitor from V
• There is a 0.1µF low-ESR capacitor from V
REFH
DDA
to V
to V
(if available).
REFL
(if available).
SSA
• If inductive isolation is used from the primary supply, an additional 1µF capacitor is placed from
V
DDA
•V
SSA
to V
and V
(if available).
SSA
(if available) is connected to VSS at a quiet point in the ground plane.
REFL
• The MCU is placed in wait mode immediately after initiating the conversion (next instruction after
write to ADCSC).
• There is no I/O switching, input or output, on the MCU during the conversion.
There are some situations where external system activity causes radiated or conducted noise emissions
or excessive V
noise is coupled into the ADC10. In these cases, or when the MCU cannot be placed
DD
in wait or I/O activity cannot be halted, the following recommendations may reduce the effect of noise on
the accuracy:
• Place a 0.01 µF capacitor on the selected input channel to V
REFL
or V
(if available). This will
SSA
improve noise issues but will affect sample rate based on the external analog source resistance.
• Operate the ADC10 in stop mode by setting ACLKEN, selecting the channel in ADCSC, and
executing a STOP instruction. This will reduce V
noise but will increase effective conversion time
DD
due to stop recovery.
• Average the input by converting the output many times in succession and dividing the sum of the
results. Four samples are required to eliminate the effect of a 1
LSB, one-time error.
• Reduce the effect of synchronous noise by operating off the asynchronous clock (ACLKEN=1) and
averaging. Noise that is synchronous to the ADCK cannot be averaged out.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
48 Freescale Semiconductor
Page 49
Functional Description
3.3.4.4 Code Width and Quantization Error
The ADC10 quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step
ideally has the same height (1 code) and width. The width is defined as the delta between the transition
points from one code to the next. The ideal code width for an N bit converter (in this case N can be 8 or
10), defined as 1
LSB, is:
1
LSB = (V
REFH–VREFL
) / 2
N
Because of this quantization, there is an inherent quantization error. Because the converter performs a
conversion and then rounds to 8 or 10 bits, the code will transition when the voltage is at the midpoint
between the points where the straight line transfer function is exactly represented by the actual transfer
function. Therefore, the quantization error will be ± 1/2
however, the code width of the first ($000) conversion is only 1/2
or $3FF) is 1.5
LSB.
LSB in 8- or 10-bit mode. As a consequence,
LSB and the code width of the last ($FF
3.3.4.5 Linearity Errors
The ADC10 may also exhibit non-linearity of several forms. Every effort has been made to reduce these
errors but the user should be aware of them because they affect overall accuracy. These errors are:
• Zero-Scale Error (E
the actual code width of the first conversion and the ideal code width (1/2
conversion is $001, then the difference between the actual $001 code width and its ideal (1
) (sometimes called offset) — This error is defined as the difference between
ZS
LSB). Note, if the first
LSB) is
used.
• Full-Scale Error (E
the last conversion and the ideal code width (1.5
difference between the actual $3FE code width and its ideal (1
) — This error is defined as the difference between the actual code width of
FS
LSB). Note, if the last conversion is $3FE, then the
LSB) is used.
• Differential Non-Linearity (DNL) — This error is defined as the worst-case difference between the
actual code width and the ideal code width for all conversions.
• Integral Non-Linearity (INL) — This error is defined as the highest-value the (absolute value of the)
running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition
voltage to a given code and its corresponding ideal transition voltage, for all codes.
• Total Unadjusted Error (TUE) — This error is defined as the difference between the actual transfer
function and the ideal straight-line transfer function, and therefore includes all forms of error.
3.3.4.6 Code Jitter, Non-Monotonicity and Missing Codes
Analog-to-digital converters are susceptible to three special forms of error. These are code jitter,
non-monotonicity, and missing codes.
• Code jitter is when, at certain points, a given input voltage converts to one of two values when
sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition
voltage, the converter yields the lower code (and vice-versa). However, even very small amounts
of system noise can cause the converter to be indeterminate (between two codes) for a range of
input voltages around the transition voltage. This range is normally around ±1/2
LSB but will
increase with noise.
• Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code
for a higher input voltage.
• Missing codes are those which are never converted for any input value. In 8-bit or 10-bit mode, the
ADC10 is guaranteed to be monotonic and to have no missing codes.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 49
Page 50
Analog-to-Digital Converter (ADC10) Module
3.4 Interrupts
When AIEN is set, the ADC10 is capable of generating a CPU interrupt after each conversion. A CPU
interrupt is generated when the conversion completes (indicated by COCO being set). COCO will set at
the end of a conversion regardless of the state of AIEN.
3.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
3.5.1 Wait Mode
The ADC10 will continue the conversion process and will generate an interrupt following a conversion if
AIEN is set. If the ADC10 is not required to bring the MCU out of wait mode, ensure that the ADC10 is not
in continuous conversion mode by clearing ADCO in the ADC10 status and control register before
executing the WAIT instruction. In single conversion mode the ADC10 automatically enters a low-power
state when the conversion is complete. It is not necessary to set the channel select bits (ADCH[4:0]) to
all 1s to enter a low power state.
3.5.2 Stop Mode
If ACLKEN is clear, executing a STOP instruction will abort the current conversion and place the ADC10
in a low-power state. Upon return from stop mode, a write to ADCSC is required to resume conversions,
and the result stored in ADRH and ADRL will represent the last completed conversion until the new
conversion completes.
If ACLKEN is set, the ADC10 continues normal operation during stop mode. The ADC10 will continue the
conversion process and will generate an interrupt following a conversion if AIEN is set. If the ADC10 is
not required to bring the MCU out of stop mode, ensure that the ADC10 is not in continuous conversion
mode by clearing ADCO in the ADC10 status and control register before executing the STOP instruction.
In single conversion mode the ADC10 automatically enters a low-power state when the conversion is
complete. It is not necessary to set the channel select bits (ADCH[4:0]) to all 1s to enter a low-power state.
If ACLKEN is set, a conversion can be initiated while in stop using the external hardware trigger
ADEXTCO when in external convert mode. The ADC10 will operate in a low-power mode until the trigger
is asserted, at which point it will perform a conversion and assert the interrupt when complete (if AIEN is
set).
3.6 ADC10 During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. BCFE in the break flag control register (BFCR) enables software to clear status bits during
the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
50 Freescale Semiconductor
Page 51
I/O Signals
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the
second step clears the status bit.
3.7 I/O Signals
The ADC10 module shares its pins with general-purpose input/output (I/O) port pins. See Figure 3-1 for
port location of these shared pins. The ADC10 on this MCU uses V
pins. This MCU does not have an external trigger source.
and VSS as its supply and reference
DD
3.7.1 ADC10 Analog Power Pin (V
The ADC10 analog portion uses V
to V
. If externally available, connect the V
DD
may be necessary to ensure clean V
DDA
DDA
)
DDA
as its power pin. In some packages, V
pin to the same voltage potential as VDD. External filtering
DDA
for good results.
is connected internally
DDA
NOTE
If externally available, route V
carefully for maximum noise immunity
DDA
and place bypass capacitors as near as possible to the package.
3.7.2 ADC10 Analog Ground Pin (V
The ADC10 analog portion uses V
to V
. If externally available, connect the V
SS
as its ground pin. In some packages, V
SSA
SSA
)
SSA
pin to the same voltage potential as VSS.
SSA
is connected internally
In cases where separate power supplies are used for analog and digital power, the ground connection
between these supplies should be at the V
these supplies if possible. The V
pin makes a good single point ground location.
SSA
3.7.3 ADC10 Voltage Reference High Pin (V
V
V
potential as V
the V
is the power supply for setting the high-reference voltage for the converter. In some packages,
REFH
is connected internally to V
REFH
, or may be driven by an external source that is between the minimum V
DDA
potential (V
DDA
REFH
must never exceed V
. If externally available, V
DDA
pin. This should be the only ground connection between
SSA
)
REFH
may be connected to the same
REFH
spec and
DDA
).
DDA
NOTE
Route V
carefully for maximum noise immunity and place bypass
REFH
capacitors as near as possible to the package.
AC current in the form of current spikes required to supply charge to the capacitor array at each
successive approximation step is drawn through the V
REFH
and V
loop. The best external component
REFL
to meet this current demand is a 0.1 µF capacitor with good high frequency characteristics. This capacitor
is connected between V
REFH
and V
and must be placed as close as possible to the package pins.
REFL
Resistance in the path is not recommended because the current will cause a voltage drop which could
result in conversion errors. Inductance in this path must be minimum (parasitic only).
3.7.4 ADC10 Voltage Reference Low Pin (V
V
V
potential as V
Freescale Semiconductor 51
is the power supply for setting the low-reference voltage for the converter. In some packages,
REFL
is connected internally to V
REFL
. There will be a brief current associated with V
SSA
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
. If externally available, connect the V
SSA
REFL
)
pin to the same voltage
REFL
when the sampling capacitor is
REFL
Page 52
Analog-to-Digital Converter (ADC10) Module
charging. If externally available, connect the V
pin to the same potential as V
REFL
at the single point
SSA
ground location.
3.7.5 ADC10 Channel Pins (ADn)
The ADC10 has multiple input channels. Empirical data shows that capacitors on the analog inputs
improve performance in the presence of noise or when the source impedance is high. 0.01 µF capacitors
with good high-frequency characteristics are sufficient. These capacitors are not necessary in all cases,
but when used they must be placed as close as possible to the package pins and be referenced to V
SSA
3.8 Registers
These registers control and monitor operation of the ADC10:
• ADC10 status and control register, ADCSC
• ADC10 data registers, ADRH and ADRL
• ADC10 clock register, ADCLK
3.8.1 ADC10 Status and Control Register
This section describes the function of the ADC10 status and control register (ADCSC). Writing ADCSC
aborts the current conversion and initiates a new conversion (if the ADCH[4:0] bits are equal to a value
other than all 1s).
.
Bit 7654321Bit 0
Read: COCO
Write:
Reset:00011111
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
= Unimplemented
Figure 3-3. ADC10 Status and Control Register (ADCSC)
COCO — Conversion Complete Bit
COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever
the status and control register is written or whenever the data register (low) is read.
1 = Conversion completed
0 = Conversion not completed
AIEN — ADC10 Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of a conversion. The interrupt signal is cleared
when the data register is read or the status/control register is written.
1 = ADC10 interrupt enabled
0 = ADC10 interrupt disabled
ADCO — ADC10 Continuous Conversion Bit
When this bit is set, the ADC10 will begin to convert samples continuously (continuous conversion
mode) and update the result registers at the end of each conversion, provided the ADCH[4:0] bits do
not decode to all 1s. The ADC10 will continue to convert until the MCU enters reset, the MCU enters
stop mode (if ACLKEN is clear), ADCLK is written, or until ADCSC is written again. If stop is entered
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
52 Freescale Semiconductor
Page 53
Registers
(with ACLKEN low), continuous conversions will cease and can be restarted only with a write to
ADCSC. Any write to ADCSC with ADCO set and the ADCH bits not all 1s will abort the current
conversion and begin continuous conversions.
If the bus frequency is less than the ADCK frequency, precise sample time for continuous conversions
cannot be guaranteed in short-sample mode (ADLSMP = 0). If the bus frequency is less than 1/11th
of the ADCK frequency, precise sample time for continuous conversions cannot be guaranteed in
long-sample mode (ADLSMP = 1).
When clear, the ADC10 will perform a single conversion (single conversion mode) each time ADCSC
is written (assuming the ADCH[4:0] bits do not decode all 1s).
1 = Continuous conversion following a write to ADCSC
0 = One conversion following a write to ADCSC
ADCH[4:0] — Channel Select Bits
The ADCH[4:0] bits form a 5-bit field that is used to select one of the input channels. The input
channels are detailed in Table 3-2. The successive approximation converter subsystem is turned off
when the channel select bits are all set to 1. This feature allows explicit disabling of the ADC10 and
isolation of the input channel from the I/O pad. Terminating continuous conversion mode this way will
prevent an additional, single conversion from being performed. It is not necessary to set the channel
select bits to all 1s to place the ADC10 in a low-power state, however, because the module is
automatically placed in a low-power state when a conversion completes.
Table 3-2. Input Channel Select
ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
00000 AD0
00001 AD1
00010 AD2
00011 AD3
00100 AD4
00101 AD5
00110 Unused
Continuing through Unused
11001 Unused
1 1 0 1 0 BANDGAP REF
1 1 0 1 1 Reserved
11100 Reserved
11101 V
11110 V
1 1 1 1 1 Low-power state
1. If any unused or reserved channels are selected, the resulting conversion will be unknown.
2. Requires LVI to be powered (LVIPWRD = 0, in CONFIG1)
Input Select
(1)
REFH
REFL
(2)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 53
Page 54
Analog-to-Digital Converter (ADC10) Module
3.8.2 ADC10 Result High Register (ADRH)
This register holds the MSBs of the result and is updated each time a conversion completes. All other bits
read as 0s. Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the
result registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then
the intermediate conversion result will be lost. In 8-bit mode, this register contains no interlocking with
ADRL.
Bit 7654321Bit 0
Read:00000000
Write:
Reset:00000000
= Unimplemented
Figure 3-4. ADC10 Data Register High (ADRH), 8-Bit Mode
Bit 7654321Bit 0
Read:000000AD9AD8
Write:
Reset:00000000
= Unimplemented
Figure 3-5. ADC10 Data Register High (ADRH), 10-Bit Mode
3.8.3 ADC10 Result Low Register (ADRL)
This register holds the LSBs of the result. This register is updated each time a conversion completes.
Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the result
registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then the
intermediate conversion result will be lost. In 8-bit mode, there is no interlocking with ADRH.
Bit 7654321Bit 0
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:
Reset:00000000
= Unimplemented
Figure 3-6. ADC10 Data Register Low (ADRL)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
54 Freescale Semiconductor
Page 55
Registers
3.8.4 ADC10 Clock Register (ADCLK)
This register selects the clock frequency for the ADC10 and the modes of operation.
Bit 7654321Bit 0
Read:
Write:
Reset:00000000
ADLPC — ADC10 Low-Power Configuration Bit
ADLPC controls the speed and power configuration of the successive approximation converter. This
is used to optimize power consumption when higher sample rates are not required.
1 = Low-power configuration: The power is reduced at the expense of maximum clock speed.
0 = High-speed configuration
ADIV[1:0] — ADC10 Clock Divider Bits
ADIV1 and ADIV0 select the divide ratio used by the ADC10 to generate the internal clock ADCK.
Table 3-3 shows the available clock configurations.
ADLPC ADIV1 ADIV0 ADICLK MODE1 MODE0 ADLSMP ACLKEN
Figure 3-7. ADC10 Clock Register (ADCLK)
Table 3-3. ADC10 Clock Divide Ratio
ADIV1 ADIV0 Divide Ratio (ADIV) Clock Rate
0 0 1 Input clock ÷ 1
0 1 2 Input clock ÷ 2
1 0 4 Input clock ÷ 4
1 1 8 Input clock ÷ 8
ADICLK — Input Clock Select Bit
If ACLKEN is clear, ADICLK selects either the bus clock or an alternate clock source as the input clock
source to generate the internal clock ADCK. If the alternate clock source is less than the minimum
clock speed, use the internally-generated bus clock as the clock source. As long as the internal clock
ADCK, which is equal to the selected input clock divided by ADIV, is at a frequency (f
ADCK
) between
the minimum and maximum clock speeds (considering ALPC), correct operation can be guaranteed.
1 = The internal bus clock is selected as the input clock source
0 = The alternate clock source IS SELECTED
MODE[1:0] — 10- or 8-Bit or Hardware Triggered Mode Selection
These bits select 10- or 8-bit operation. The successive approximation converter generates a result
that is rounded to 8- or 10-bit value based on the mode selection. This rounding process sets the
transfer function to transition at the midpoint between the ideal code voltages, causing a quantization
error of ± 1/2
LSB.
Reset returns 8-bit mode.
00 = 8-bit, right-justified, ADCSC software triggered mode enabled
01 = 10-bit, right-justified, ADCSC software triggered mode enabled
10 = Reserved
11 = 10-bit, right-justified, hardware triggered mode enabled
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 55
Page 56
Analog-to-Digital Converter (ADC10) Module
ADLSMP — Long Sample Time Configuration
This bit configures the sample time of the ADC10 to either 3.5 or 23.5 ADCK clock cycles. This adjusts
the sample period to allow higher impedance inputs to be accurately sampled or to maximize
conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall
power consumption in continuous conversion mode if high conversion rates are not required.
1 = Long sample time (23.5 cycles)
0 = Short sample time (3.5 cycles)
ACLKEN — Asynchronous Clock Source Enable
This bit enables the asynchronous clock source as the input clock to generate the internal clock ADCK,
and allows operation in stop mode. The asynchronous clock source will operate between 1 MHz and
2 MHz if ADLPC is clear, and between 0.5 MHz and 1 MHz if ADLPC is set.
1 = The asynchronous clock is selected as the input clock source (the clock generator is only
enabled during the conversion)
0 = ADICLK specifies the input clock source and conversions will not continue in stop mode
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
56 Freescale Semiconductor
Page 57
Chapter 4
Auto Wakeup Module (AWU)
4.1 Introduction
This section describes the auto wakeup module (AWU). The AWU generates a periodic interrupt during
stop mode to wake the part up without requiring an external signal. Figure 4-1 is a block diagram of the
AWU.
COPRS (FROM CONFIG1)
OSCENINSTOP (FROM CONFIG2)
BUSCLKX4
EN 32 kHz
INT RC OSC
CLRLOGIC
(CGMXCLK)
BUSCLKX4
RESET
CLK
RST
Figure 4-1. Auto Wakeup Interrupt Request Generation Logic
CLEAR
M
U
X
RESET
AUTOW UGEN
SHORT
CLK
AWUI E
1 = DIV 2
0 = DIV 2
OVERFLOW
RST
ISTOP
V
DD
9
14
RESET
ACKK
D
Q
E
R
TO PTA READ, BIT 6
AWUL
AWUIREQ
TO KBI INTERRUPT LOGIC
(SEE Figure 9-2)
4.2 Features
Features of the auto wakeup module include:
• One internal interrupt with separate interrupt enable bit, sharing the same keyboard interrupt vector
and keyboard interrupt mask bit
• Exit from low-power stop mode without external signals
• Selectable timeout periods
• Dedicated low-power internal oscillator separate from the main system clock sources
• Option to allow bus clock source to run the AWU if enabled in STOP
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Auto Wakeup Module (AWU)
4.3 Functional Description
The function of the auto wakeup logic is to generate periodic wakeup requests to bring the microcontroller
unit (MCU) out of stop mode. The wakeup requests are treated as regular keyboard interrupt requests,
with the difference that instead of a pin, the interrupt signal is generated by an internal logic.
Writing the AWUIE bit in the keyboard interrupt enable register enables or disables the auto wakeup
interrupt input (see Figure 4-1). A 1 applied to the AWUIREQ input with auto wakeup interrupt request
enabled, latches an auto wakeup interrupt request.
There exists two clock sources for the AWU. An internal RC oscillator (exclusive for the auto wakeup
feature, AWU oscillator) drives the wakeup request generator provided the OSCENINSTOP bit in the
CONFIG2 register Figure 4-1is cleared. If the application employs a crystal, for example, by setting the
OSCENINSTOP bit the BUSCLKX4 will drive the wakeup request generator to allow a more accurate
wakeup.
Entering stop mode will enable the auto wakeup generation logic.
Once the overflow count is reached in the generator counter, a wakeup request, AWUIREQ, is latched
and sent to the KBI logic. See Figure 4-1.
Wakeup interrupt requests will only be serviced if the associated interrupt enable bit, AWUIE, in KBIER
is set. The AWU shares the keyboard interrupt vector.
The overflow count can be selected from two options defined by the COPRS bit in CONFIG1. This bit was
“borrowed” from the computer operating properly (COP) using the fact that the COP feature is idle (no
MCU clock available) in stop mode.
The auto wakeup RC oscillator is highly dependent on operating voltage and temperature. This feature is
not recommended for use as a time-keeping function.
The wakeup request is latched to allow the interrupt source identification. The latched value, AWUL, can
be read directly from the bit 6 position of PTA data register. This is a read-only bit which is occupying an
empty bit position on PTA. No PTA associated registers, such as PTA6 data, PTA6 direction, and PTA6
pullup/down exist for this bit. The latch can be cleared by writing to the ACKK bit in the KBSCR register.
Reset also clears the latch. AWUIE bit in KBI interrupt enable register (see Figure 4-1) has no effect on
AWUL reading.
The AWU oscillator and counters are inactive in normal operating mode and become active only upon
entering stop mode.
4.4 Interrupts
The AWU can generate an interrupt requests:.
AWU Latch (AWUL) — The AWUL bit is set when the AWU counter overflows. The auto wakeup interrupt
mask bit, AWUIE, is used to enable or disable AWU interrupt requests.
The AWU shares its interrupt with the KBI vector.
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Low-Power Modes
4.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
4.5.1 Wait Mode
The AWU module remains inactive in wait mode.
4.5.2 Stop Mode
When the AWU module is enabled (AWUIE = 1 in the keyboard interrupt enable register) it is activated
automatically upon entering stop mode. Clearing the IMASKK bit in the keyboard status and control
register enables keyboard interrupt requests to bring the MCU out of stop mode. The AWU counters start
from 0 each time stop mode is entered.
4.6 Registers
The AWU shares registers with the keyboard interrupt (KBI) module, the port A I/O module and
configuration register 2. The following I/O registers control and monitor operation of the AWU:
• Port A data register (PTA)
• Keyboard interrupt status and control register (KBSCR)
• Keyboard interrupt enable register (KBIER)
• Configuration register 1 (CONFIG1)
• Configuration register 2 (CONFIG2)
4.6.1 Port A I/O Register
The port A data register (PTA) contains a data latch for the state of the AWU interrupt request, in addition
to the data latches for port A.
Bit 7654321Bit 0
Read: 0 AWUL
Write:
Reset: 0 0 Unaffected by reset
= Unimplemented
PTA5 PTA4 PTA3
Figure 4-2. Port A Data Register (PTA)
AWUL — Auto Wakeup Latch
This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup
request signal is generated internally. There is no PTA6 port or any of the associated bits such as
PTA6 data direction or pullup/down bits.
1 = Auto wakeup interrupt request is pending
0 = Auto wakeup interrupt request is not pending
NOTE
PTA5–PTA0 bits are not used in conjuction with the auto wakeup feature.
To see a description of these bits, see 12.2.1 Port A Data Register.
PTA2
PTA1 PTA0
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Auto Wakeup Module (AWU)
4.6.2 Keyboard Status and Control Register
The keyboard status and control register (KBSCR):
• Flags keyboard/auto wakeup interrupt requests
• Acknowledges keyboard/auto wakeup interrupt requests
• Masks keyboard/auto wakeup interrupt requests
Bit 7654321Bit 0
Read:0000KEYF 0
Write:
Reset:00000000
= Unimplemented
ACKK
Figure 4-3. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port A or auto wakeup. Reset clears
the KEYF bit.
1 = Keyboard/auto wakeup interrupt pending
0 = No keyboard/auto wakeup interrupt pending
IMASKK MODEK
ACKK — Keyboard Acknowledge Bit
Writing a 1 to this write-only bit clears the keyboard/auto wakeup interrupt request on port A and auto
wakeup logic. ACKK always reads as 0. Reset clears ACKK.
IMASKK— Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating
interrupt requests on port A or auto wakeup. Reset clears the IMASKK bit.
1 = Keyboard/auto wakeup interrupt requests masked
0 = Keyboard/auto wakeup interrupt requests not masked
NOTE
MODEK is not used in conjuction with the auto wakeup feature. For a
description of this bit, see 9.8.1 Keyboard Status and Control Register
(KBSCR).
4.6.3 Keyboard Interrupt Enable Register
The keyboard interrupt enable register (KBIER) enables or disables the auto wakeup to operate as a
keyboard/auto wakeup interrupt input.
Bit 7654321Bit 0
Read: 0
Write:
Reset:00000000
AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
= Unimplemented
Figure 4-4. Keyboard Interrupt Enable Register (KBIER)
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Registers
AWUIE — Auto Wakeup Interrupt Enable Bit
This read/write bit enables the auto wakeup interrupt input to latch interrupt requests. Reset clears
AWUIE.
1 = Auto wakeup enabled as interrupt input
0 = Auto wakeup not enabled as interrupt input
NOTE
KBIE5–KBIE0 bits are not used in conjuction with the auto wakeup feature.
For a description of these bits, see 9.8.2 Keyboard Interrupt Enable
Register (KBIER).
4.6.4 Configuration Register 2
The configuration register 2 (CONFIG2), is used to allow the bus clock source to run in STOP. In this case,
the clock, BUSCLKX4 will be used to drive the AWU request generator.
Bit 76543 2 1 Bit 0
Read:
Reset:00000 0 0 0
IRQPUD IRQEN RRR ROSCENINSTOP RSTEN
Write:
Figure 4-5. Configuration Register 2 (CONFIG2)
OSCENINSTOP — Oscillator Enable in Stop Mode Bit
OSCENINSTOP, when set, will allow the bus clock source (BUSCLKX4) to generate clocks for the
AWU in stop mode. See 11.8.1 Oscillator Status and Control Register for information on enabling the
external clock sources.
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode
NOTE
IRQPUD, IRQEN, and RSTEN bits are not used in conjuction with the auto
wakeup feature. For a description of these bits, see Chapter 5
Configuration Register (CONFIG).
4.6.5 Configuration Register 1
The configuration register 1 (CONFIG1), is used to select the period for the AWU. The timeout will be
based on the COPRS bit along with the clock source for the AWU.
Bit 7654321Bit 0
Read:
Write:
Reset:
COPRS LVISTOP LVIRSTD LVIPWRD LVITRIP SSREC STOP COPD
POR:
0
0
U = Unaffected
0
0
0
0
0
0
U
0
0
0
0
0
0
0
Figure 4-6. Configuration Register 1 (CONFIG1)
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Auto Wakeup Module (AWU)
COPRS (In Stop Mode) — Auto Wakeup Period Selection Bit, depends on OSCSTOPEN in
CONFIG2 and bus clock source (BUSCLKX4).
9
1 = Auto wakeup short cycle = (2
0 = Auto wakeup long cycle = (2
) × (INTRCOSC or BUSCLKX4)
14
) × (INTRCOSC or BUSCLKX4)
NOTE
LVISTOP, LVIRST, LVIPWRD, LVITRIP, SSREC and COPD bits are not
used in conjuction with the auto wakeup feature. For a description of these
bits, see Chapter 5 Configuration Register (CONFIG).
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Chapter 5
Configuration Register (CONFIG)
5.1 Introduction
This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers
enable or disable the following options:
• Stop mode recovery time (32 × BUSCLKX4 cycles or 4096 × BUSCLKX4 cycles)
•STOP instruction
• Computer operating properly module (COP)
• COP reset period (COPRS): (2
• Low-voltage inhibit (LVI) enable and trip voltage selection
• Auto wakeup timeout period
• Allow clock source to remain enabled in STOP
• Enable IRQ
• Disable IRQ
• Enable RST
pin
pin pullup device
pin
5.2 Functional Description
13–24
) × BUSCLKX4 or (218–24) × BUSCLKX4
The configuration registers are used in the initialization of various options. The configuration registers can
be written once after each reset. Most of the configuration register bits are cleared during reset. Since the
various options affect the operation of the microcontroller unit (MCU) it is recommended that this register
be written immediately after reset. The configuration registers are located at $001E and $001F, and may
be read at anytime.
NOTE
The CONFIG registers are one-time writable by the user after each reset.
Upon a reset, the CONFIG registers default to predetermined settings as
shown in Figure 5-1 and Figure 5-2.
Bit 7 6 5 4 3 2 1 Bit 0
Read:
IRQPUD IRQEN R R R R OSCENINSTOP RSTEN
Write:
Reset:000 0 0 0 0 U
POR:000 0 0 0 0 0
= Reserved U = Unaffected
R
Figure 5-1. Configuration Register 2 (CONFIG2)
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Configuration Register (CONFIG)
IRQPUD — IRQ Pin Pullup Control Bit
1 = Internal pullup is disconnected
0 = Internal pullup is connected between IRQ
pin and V
DD
IRQEN — IRQ Pin Function Selection Bit
1 = Interrupt request function active in pin
0 = Interrupt request function inactive in pin
OSCENINSTOP— Oscillator Enable in Stop Mode Bit
OSCENINSTOP, when set, will allow the clock source to continue to generate clocks in stop mode.
This function can be used to keep the auto-wakeup running while the rest of the microcontroller stops.
When clear, the clock source is disabled when the microcontroller enters stop mode.
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode
RSTEN — RST
Pin Function Selection
1 = Reset function active in pin
0 = Reset function inactive in pin
NOTE
The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will
leave this bit unaffected.
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset:0000U000
COPRS LVISTOP LVIRSTD LVIPWRD LVITRIP SSREC STOP COPD
POR:00000000
U = Unaffected
Figure 5-2. Configuration Register 1 (CONFIG1)
COPRS (Out of Stop Mode) — COP Reset Period Selection Bit
1 = COP reset short cycle = (2
0 = COP reset long cycle = (2
13
– 24) × BUSCLKX4
18
– 24) × BUSCLKX4
COPRS (In Stop Mode) — Auto Wakeup Period Selection Bit, depends on OSCSTOPEN in
CONFIG2 and external clock source
1 = Auto wakeup short cycle = (2
0 = Auto wakeup long cycle = (2
9
) × (INTRCOSC or BUSCLKX4)
14
) × (INTRCOSC or BUSCLKX4)
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module.
1 = LVI module resets disabled
0 = LVI module resets enabled
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Functional Description
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module.
1 = LVI module power disabled
0 = LVI module power enabled
LVITRIP — LVI Trip Point Selection Bit
LVITRIP selects the voltage operating mode of the LVI module. The voltage mode selected for the LVI
should match the operating V
for the LVI’s voltage trip points for each of the modes.
DD
1 = LVI operates for a 5-V protection
0 = LVI operates for a 3.3-V protection
NOTE
The LVITRIP bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096
BUSCLKX4 cycle delay.
1 = Stop mode recovery after 32 BUSCLKX4 cycles
0 = Stop mode recovery after 4096 BUSCLKX4 cycles
NOTE
Exiting stop mode by an LVI reset will result in the long stop recovery.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
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Configuration Register (CONFIG)
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Chapter 6
Computer Operating Properly (COP)
6.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the
configuration 1 (CONFIG1) register.
6.2 Functional Description
SIM MODULE
BUSCLKX4
INTERNAL RESET SOURCES
STOP INSTRUCTION
COPCTL WRITE
COPEN (FROM SIM)
COPD (FROM CONFIG1)
RESET
COPCTL WRITE
COP RATE SELECT
(COPRS FROM CONFIG1)
12-BIT SIM COUNTER
(1)
CLEAR ALL STAGES
COP CLOCK
CLEAR STAGES 5–12
COP TIMEOUT
COP MODULE
6-BIT COP COUNTER
CLEAR
COP COUNTER
SIM RESET CIRCUIT
RESET STATUS REGISTER
1. See Chapter 13 System Integration Module (SIM) for more details.
Figure 6-1. COP Block Diagram
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Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM)
counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after
18–24
2
configuration register 1. With a 2
or 213–24 BUSCLKX4 cycles; depending on the state of the COP rate select bit, COPRS, in
18–24
BUSCLKX4 cycle overflow option, the internal 12.8-MHz oscillator
gives a COP timeout period of 20.48 ms. Writing any value to location $FFFF before an overflow occurs
prevents a COP reset by clearing the COP counter and stages 12–5 of the SIM counter.
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST
pin low (if the RSTEN bit is set in the CONFIG1 register) for 32 × BUSCLKX4
cycles and sets the COP bit in the reset status register (RSR). See 13.8.1 SIM Reset Status Register.
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
6.3 I/O Signals
The following paragraphs describe the signals shown in Figure 6-1.
6.3.1 BUSCLKX4
BUSCLKX4 is the oscillator output signal. BUSCLKX4 frequency is equal to the crystal frequency or the
RC-oscillator frequency.
6.3.2 STOP Instruction
The STOP instruction clears the SIM counter.
6.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see Figure 6-2) clears the COP counter and
clears stages 12–5 of the SIM counter. Reading the COP control register returns the low byte of the reset
vector.
6.3.4 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 × BUSCLKX4 cycles after power
up.
6.3.5 Internal Reset
An internal reset clears the SIM counter and the COP counter.
6.3.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG).
See Chapter 5 Configuration Register (CONFIG).
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Interrupts
6.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1
(CONFIG1). See Chapter 5 Configuration Register (CONFIG).
6.4 Interrupts
The COP does not generate CPU interrupt requests.
6.5 Monitor Mode
The COP is disabled in monitor mode when V
is present on the IRQ pin.
TST
6.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
6.6.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically
clear the COP counter.
6.6.2 Stop Mode
Stop mode turns off the BUSCLKX4 input to the COP and clears the SIM counter. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
6.7 COP Module During Break Mode
The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary
register (BRKAR).
6.8 Register
The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing
any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF
returns the low byte of the reset vector.
Address: $FFFF
Bit 7654321Bit 0
Read: LOW BYTE OF RESET VECTOR
Write: CLEAR COP COUNTER
Reset: Unaffected by reset
Figure 6-2. COP Control Register (COPCTL)
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Computer Operating Properly (COP)
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Chapter 7
Central Processor Unit (CPU)
7.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of
the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a
description of the CPU instruction set, addressing modes, and architecture.
7.2 Features
Features of the CPU include:
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with x-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for extension of addressing range
beyond 64 Kbytes
• Low-power stop and wait modes
7.3 CPU Registers
Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map.
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Central Processor Unit (CPU)
7
15
H X
15
15
70
V11H I NZC
0
ACCUMULATOR (A)
0
INDEX REGISTER (H:X)
0
STACK POINTER (SP)
0
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 7-1. CPU Registers
7.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and
the results of arithmetic/logic operations.
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
Figure 7-2. Accumulator (A)
7.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of
the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the
conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit
151413121110987654321
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Figure 7-3. Index Register (H:X)
Bit
0
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CPU Registers
7.3.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a
reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an
index register to access data on the stack. The CPU uses the contents of the stack pointer to determine
the conditional address of the operand.
Bit
151413121110987654321
Read:
Write:
Reset:0000000011111111
Bit
0
Figure 7-4. Stack Pointer (SP)
NOTE
The location of the stack is arbitrary and may be relocated anywhere in
random-access memory (RAM). Moving the SP out of page 0 ($0000 to
$00FF) frees direct address (page 0) space. For correct operation, the
stack pointer must point only to RAM locations.
7.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
Normally, the program counter automatically increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF.
The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit
151413121110987654321
Read:
Write:
Reset: Loaded with vector from $FFFE and $FFFF
Bit
0
Figure 7-5. Program Counter (PC)
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Central Processor Unit (CPU)
7.3.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the
instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code register.
Bit 7654321Bit 0
Read:
Write:
Reset:X1 1X1XXX
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch
instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an
add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and
C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
V11H I NZC
X = Indeterminate
Figure 7-6. Condition Code Register (CCR)
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the
interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the
clear interrupt mask software instruction (CLI).
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
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Arithmetic/Logic Unit (ALU)
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test
and branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
7.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set.
Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the
instructions and addressing modes and more detail about the architecture of the CPU.
7.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
7.5.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
7.5.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
7.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU
to normal operation if the break interrupt has been deasserted.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 75
Page 76
Central Processor Unit (CPU)
7.7 Instruction Set Summary
Table 7-1 provides a summary of the M68HC08 instruction set.
Table 7-1. Instruction Set Summary (Sheet 1 of 6)
Effect
Source
Form
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
AIS #
opr Add Immediate Value (Signed) to SP
AIX #opr Add Immediate Value (Signed) to H:X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3
BCLR n, opr Clear Bit n in M Mn ← 0 ––––––
BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3
BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 ––––––REL 27 rr 3
BGE opr
BGT opr
BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 ––––––REL 28 rr 3
BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 ––––––REL 29 rr 3
BHI rel Branch if Higher PC ← (PC) + 2 + rel ? (C) | (Z) = 0 ––––––REL 22 rr 3
Add with Carry A ← (A) + (M) + (C) –
Add without Carry A ← (A) + (M) –
Logical AND A ← (A) & (M) 0 – – –
Arithmetic Shift Left
(Same as LSL)
Arithmetic Shift Right ––
Branch if Greater Than or Equal To
(Signed Operands)
Branch if Greater Than (Signed
Operands)
Operation Description
SP ← (SP) + (16
H:X ← (H:X) + (16
C
b7
b7
PC ← (PC) + 2 + rel ? (N
PC ← (PC) + 2 + rel ? (Z) | (N
« M)
« M)
0
b0
C
b0
⊕ V) = 0
⊕ V) = 0
on CCR
VH I NZC
––––––IMM A7 ii 2
––––––IMM AF ii 2
––
––––––REL 90 rr 3
––––––REL 92 rr 3
Address
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
Mode
9EE9
9ED9
9EEB
9EDB
9EE4
9ED4
9E68
9E67
A9
B9
C9
D9
E9
F9
AB
BB
CB
DB
EB
FB
A4
B4
C4
D4
E4
F4
38
48
58
68
78
37
47
57
67
77
11
13
15
17
19
1B
1D
1F
Opcode
ii
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
dd
ff
ff
dd
dd
dd
dd
dd
dd
dd
dd
Operand
Cycles
2
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
1
1
4
3
5
4
4
4
4
4
4
4
4
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
76 Freescale Semiconductor
Page 77
Instruction Set Summary
Table 7-1. Instruction Set Summary (Sheet 2 of 6)
Effect
Source
Form
BHS rel
BIH rel Branch if IRQ
BIL rel Branch if IRQ
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
BLE opr
BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3
BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 ––––––REL 23 rr 3
BLT opr Branch if Less Than (Signed Operands)
BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 ––––––REL 2C rr 3
BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 ––––––REL 2B rr 3
BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? (I) = 1 ––––––REL 2D rr 3
BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 ––––––REL 26 rr 3
BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 ––––––REL 2A rr 3
BRA rel Branch Always PC ← (PC) + 2 + rel ––––––REL 20 rr 3
BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 –––––
BRN rel Branch Never PC ← (PC) + 2 ––––––REL 21 rr 3
BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 +
BSET n,opr Set Bit n in M Mn ← 1 ––––––
BSR rel Branch to Subroutine
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
CLC Clear Carry Bit C ← 0 –––––0INH 98 1
CLI Clear Interrupt Mask I ← 0 ––0–––INH 9A 2
Branch if Higher or Same
(Same as BCC)
Bit Test (A) & (M) 0 – – –
Branch if Less Than or Equal To
(Signed Operands)
Compare and Branch if Equal
Operation Description
PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3
Pin High PC ← (PC) + 2 + rel ? IRQ = 1 ––––––REL 2F rr 3
Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 ––––––REL 2E rr 3
PC ← (PC) + 2 + rel ? (Z) | (N
PC ← (PC) + 2 + rel ? (N
rel ? (Mn) = 1 –––––
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
⊕ V) = 1
⊕ V) =1
on CCR
VH I NZC
––––––REL 93 rr 3
––––––REL 91 rr 3
––––––REL AD rr 4
––––––
Address
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR
IMM
IMM
IX1+
IX+
SP1
Mode
9EE5
9ED5
9E61
A5
B5
C5
D5
E5
F5
01
03
05
07
09
0B
0D
0F
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
31
41
51
61
71
Opcode
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd
dd
dd
dd
dd
dd
dd
dd
dd rr
ii rr
ii rr
ff rr
rr
ff rr
Operand
2
3
4
4
3
2
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
5
4
4
5
4
6
Cycles
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 77
Page 78
Central Processor Unit (CPU)
Source
Form
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
COM
opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
CPHX #opr
CPHX opr
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
DAA Decimal Adjust A
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
DIV Divide
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
Clear
Compare A with M (A) – (M) ––
Complement (One’s Complement)
Compare H:X with M (H:X) – (M:M + 1) ––
Compare X with M (X) – (M) ––
Decrement and Branch if Not Zero
Decrement
Exclusive OR M with A
Increment
Operation Description
Table 7-1. Instruction Set Summary (Sheet 3 of 6)
Effect
on CCR
VH I NZC
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
M ← (M
) = $FF – (M)
A ← (A
) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M
) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(A)
10
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
M
← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
A ← (H:A)/(X)
H ← Remainder
A ← (A
⊕ M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
0––01–
0––1
U–– INH 72 2
––––––
–––
––––INH 52 7
0–––
–––
DIR
INH
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
Address
Mode
Opcode
Operand
3F
dd
4F
5F
8C
6F
ff
7F
9E6F
ff
ii
A1
dd
B1
hh ll
C1
ee ff
D1
ff
E1
F1
ff
9EE1
ee ff
9ED1
33
dd
43
53
63
ff
73
9E63
ff
6575ii ii+1dd3
A3
ii
B3
dd
C3
hh ll
D3
ee ff
E3
ff
F3
9EE3
ff
9ED3
ee ff
3B
dd rr
4B
rr
5B
rr
6B
ff rr
7B
rr
9E6B
ff rr
3A
dd
4A
5A
6A
ff
7A
9E6A
ff
A8
ii
B8
dd
C8
hh ll
D8
ee ff
E8
ff
F8
9EE8
ff
9ED8
ee ff
3C
dd
4C
5C
6C
ff
7C
9E6C
ff
Cycles
3
1
1
1
3
2
4
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
2
3
4
4
3
2
4
5
5
3
3
5
4
6
4
1
1
4
3
5
2
3
4
4
3
2
4
5
4
1
1
4
3
5
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
78 Freescale Semiconductor
Page 79
Instruction Set Summary
Table 7-1. Instruction Set Summary (Sheet 4 of 6)
Effect
Source
Form
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
LDHX #opr
LDHX opr
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
MUL Unsigned multiply X:A ← (X) × (A) –0–––0INH 42 5
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
NOP No Operation None ––––––INH 9D 1
NSA Nibble Swap A A ← (A[3:0]:A[7:4]) ––––––INH 62 3
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
PSHA Push A onto Stack Push (A); SP ← (SP) – 1 ––––––INH 87 2
PSHH Push H onto Stack Push (H); SP ← (SP) – 1 ––––––INH 8B 2
PSHX Push X onto Stack Push (X); SP ← (SP) – 1 ––––––INH 89 2
Jump PC ← Jump Address ––––––
Jump to Subroutine
Load A from M A ← (M) 0–––
Load H:X from M H:X ← (M:M + 1) 0–––
Load X from M X ← (M) 0–––
Logical Shift Left
(Same as ASL)
Logical Shift Right ––0
Move
Negate (Two’s Complement)
Inclusive OR A and M A ← (A) | (M) 0 – – –
Operation Description
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
C
b7
b7
(M)
Destination
H:X ← (H:X) + 1 (IX+D, DIX+)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
← (M)
0
b0
C0
b0
Source
on CCR
VH I NZC
––––––
––
0–––
––
DIR
EXT
IX2
IX1
IX
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
DD
DIX+
IMD
IX+D
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Address
Mode
Opcode
Operand
BC
dd
CC
hh ll
DC
ee ff
EC
ff
FC
BD
dd
CD
hh ll
DD
ee ff
ED
ff
FD
A6
ii
B6
dd
C6
hh ll
D6
ee ff
E6
ff
F6
9EE6
ff
9ED6
ee ff
4555ii jjdd3
AE
ii
BE
dd
CE
hh ll
DE
ee ff
EE
ff
FE
9EEE
ff
9EDE
ee ff
38
dd
48
58
68
ff
78
9E68
ff
34
dd
44
54
64
ff
74
9E64
ff
4E
dd dd
5E
dd
6E
ii dd
7E
dd
30
dd
40
50
60
ff
70
9E60
ff
AA
ii
BA
dd
hh ll
CA
ee ff
DA
ff
EA
FA
ff
9EEA
ee ff
9EDA
2
3
4
3
2
4
5
6
5
4
2
3
4
4
3
2
4
5
4
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
1
1
4
3
5
5
4
4
4
4
1
1
4
3
5
2
3
4
4
3
2
4
5
Cycles
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 79
Page 80
Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Sheet 5 of 6)
Effect
Source
Form
PULA Pull A from Stack SP ← (SP + 1); Pull (A) ––––––INH 86 2
PULH Pull H from Stack SP ← (SP + 1); Pull (H) ––––––INH 8A 2
PULX Pull X from Stack SP ← (SP + 1); Pull (X) ––––––INH 88 2
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
RSP Reset Stack Pointer SP ← $FF ––––––INH 9C 1
RTI Return from Interrupt
RTS Return from Subroutine
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
SEC Set Carry Bit C ← 1 –––––1INH 99 1
SEI Set Interrupt Mask I ← 1 ––1–––INH 9B 2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
STHX opr Store H:X in M (M:M + 1) ← (H:X) 0 – – – DIR 35 dd 4
STOP
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Rotate Left through Carry ––
Rotate Right through Carry ––
Subtract with Carry A ← (A) – (M) – (C) ––
Store A in M M ← (A) 0–––
Enable Interrupts, Stop Processing,
Refer to MCU Documentation
Store X in M M ← (X) 0–––
Subtract A ← (A) – (M) ––
Operation Description
C
b7
b7
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ←
(SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
I ← 0; Stop Processing ––0–––INH 8E 1
b0
b0
C
on CCR
VH I NZC
INH 80 7
––––––INH 81 4
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Address
Mode
9E69
9E66
9EE2
9ED2
9EE7
9ED7
9EEF
9EDF
9EE0
9ED0
39
49
59
69
79
36
46
56
66
76
A2
B2
C2
D2
E2
F2
B7
C7
D7
E7
F7
BF
CF
DF
EF
FF
A0
B0
C0
D0
E0
F0
Opcode
dd
ff
ff
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
hh ll
ee ff
ff
ff
ee ff
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
Operand
Cycles
4
1
1
4
3
5
4
1
1
4
3
5
2
3
4
4
3
2
4
5
3
4
4
3
2
4
5
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
80 Freescale Semiconductor
Page 81
Opcode Map
Table 7-1. Instruction Set Summary (Sheet 6 of 6)
Effect
Source
Form
SWI Software Interrupt
TAP Transfer A to CCR CCR ← (A) INH 84 2
TAX Transfer A to X X ← (A) ––––––INH 97 1
TPA Transfer CCR to A A ← (CCR) ––––––INH 85 1
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
TSX Transfer SP to H:X H:X ← (SP) + 1 ––––––INH 95 2
TXA Transfer X to A A ← (X) ––––––INH 9F 1
TXS Transfer H:X to SP (SP) ← (H:X) – 1 ––––––INH 94 2
WAIT Enable Interrupts; Wait for Interrupt
A Accumulator n Any bit
C Carry/borrow bit opr Operand (one or two bytes)
CCR Condition code register PC Program counter
dd Direct address of operand PCH Program counter high byte
dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte
DD Direct to direct addressing mode REL Relative addressing mode
DIR Direct addressing mode rel Relative program counter offset byte
DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte
ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode
EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode
ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer
H Half-carry bit U Undefined
H Index register high byte V Overflow bit
hh ll High and low bytes of operand address in extended addressing X Index register low byte
I Interrupt mask Z Zero bit
ii Immediate operand byte & Logical AND
IMD Immediate source to direct destination addressing mode | Logical OR
IMM Immediate addressing mode
INH Inherent addressing mode ( ) Contents of
IX Indexed, no offset addressing mode –( ) Negation (two’s complement)
IX+ Indexed, no offset, post increment addressing mode # Immediate value
IX+D Indexed with post increment to direct addressing mode
IX1 Indexed, 8-bit offset addressing mode ← Loaded with
IX1+ Indexed, 8-bit offset, post increment addressing mode ? If
IX2 Indexed, 16-bit offset addressing mode : Concatenated with
M Memory location Set or cleared
N Negative bit — Not affected
Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – –
Operation Description
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
I bit ← 0; Inhibit CPU clocking
until interrupted
⊕ Logical EXCLUSIVE OR
« Sign extend
on CCR
VH I NZC
––1–––INH 83 9
––0–––INH 8F 1
DIR
INH
INH
IX1
IX
SP1
Address
Mode
9E6D
3D
4D
5D
6D
7D
Opcode
dd
ff
ff
Operand
3
1
1
3
2
4
Cycles
7.8 Opcode Map
See Table 7-2.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 81
Page 82
Central Processor Unit (CPU)
2
SUB
1IX
4
SUB
3 SP1
3
SUB
2IX1
5
SUB
4 SP2
4
SUB
3IX2
4
SUB
3EXT
3
SUB
2DIR
2
SUB
2IMM
3
BGE
2REL
7
RTI
1INH
3
NEG
1IX
5
NEG
4
1
1
4
3
4
3 SP1
NEG
2IX1
NEGX
1INH
NEGA
1INH
NEG
2DIR
BRA
2REL
BSET0
2DIR
Table 7-2. Opcode Map
2
4
3
5
4
4
3
2
3
4
4
6
5
4
4
5
3
4
CMP
1IX
CMP
3 SP1
CMP
2IX1
CMP
4 SP2
CMP
3IX2
CMP
3EXT
CMP
2DIR
CMP
2IMM
BLT
2REL
RTS
1INH
CBEQ
2IX+
CBEQ
4 SP1
CBEQ
3IX1+
CBEQX
3IMM
CBEQA
3IMM
CBEQ
3DIR
BRN
2REL
BCLR0
2DIR
2
4
3
5
4
4
3
2
3
2
3
7
5
3
4
SBC
1IX
SBC
3 SP1
SBC
2IX1
SBC
4 SP2
SBC
3IX2
SBC
3EXT
SBC
2DIR
SBC
2IMM
BGT
2REL
DAA
1INH
NSA
1INH
DIV
1INH
MUL
1INH
BHI
2REL
BSET1
2DIR
2
4
3
5
4
4
3
2
3
9
3
5
4
1
1
4
3
4
CPX
1IX
CPX
3 SP1
CPX
2IX1
CPX
4 SP2
CPX
3IX2
CPX
3EXT
CPX
2DIR
CPX
2IMM
BLE
2REL
SWI
1INH
COM
1IX
COM
3 SP1
COM
2IX1
COMX
1INH
COMA
1INH
COM
2DIR
BLS
2REL
BCLR1
2DIR
2
4
3
5
4
4
3
2
2
2
3
5
4
1
1
4
3
4
AND
1IX
AND
3 SP1
AND
2IX1
AND
4 SP2
AND
3IX2
AND
3EXT
AND
2DIR
AND
2IMM
TXS
1INH
TA P
1INH
LSR
1IX
LSR
3 SP1
LSR
2IX1
LSRX
1INH
LSRA
1INH
LSR
2DIR
BCC
2REL
BSET2
2DIR
2
BIT
4
BIT
3
BIT
5
BIT
4
BIT
4
BIT
3
BIT
2
BIT
2
TSX
1
TPA
4
CPHX
3
CPHX
4
LDHX
3
LDHX
4
STHX
3
BCS
4
BCLR2
1IX
3 SP1
2IX1
4 SP2
3IX2
3EXT
2DIR
2IMM
1INH
1INH
2DIR
3IMM
2DIR
3IMM
2DIR
2REL
2DIR
2
4
3
5
4
4
3
2
2
3
5
4
1
1
4
3
4
LDA
1IX
LDA
3 SP1
LDA
2IX1
LDA
4 SP2
LDA
3IX2
LDA
3EXT
LDA
2DIR
LDA
2IMM
PULA
1INH
ROR
1IX
ROR
3 SP1
ROR
2IX1
RORX
1INH
RORA
1INH
ROR
2DIR
BNE
2REL
BSET3
2DIR
2
4
3
5
4
4
3
2
1
2
3
5
4
1
1
4
3
4
STA
1IX
STA
3 SP1
STA
2IX1
STA
4 SP2
STA
3IX2
STA
3EXT
STA
2DIR
AIS
2IMM
TA X
1INH
PSHA
1INH
ASR
1IX
ASR
3 SP1
ASR
2IX1
ASRX
1INH
ASRA
1INH
ASR
2DIR
BEQ
2REL
BCLR3
2DIR
2
4
3
5
4
4
3
2
1
2
3
5
4
1
1
4
3
4
EOR
1IX
EOR
3 SP1
EOR
2IX1
EOR
4 SP2
EOR
3IX2
EOR
3EXT
EOR
2DIR
EOR
2IMM
CLC
1INH
PULX
1INH
LSL
1IX
LSL
3 SP1
LSL
2IX1
LSLX
1INH
LSLA
1INH
LSL
2DIR
BHCC
2REL
BSET4
2DIR
2
4
3
5
4
4
3
2
1
2
3
5
4
1
1
4
3
4
ADC
1IX
ADC
3 SP1
ADC
2IX1
ADC
4 SP2
ADC
3IX2
ADC
3EXT
ADC
2DIR
ADC
2IMM
SEC
1INH
PSHX
1INH
ROL
1IX
ROL
3 SP1
ROL
2IX1
ROLX
1INH
ROLA
1INH
ROL
2DIR
BHCS
2REL
BCLR4
2DIR
2
4
3
5
4
4
3
2
2
2
3
5
4
1
1
4
3
4
ORA
1IX
ORA
3 SP1
ORA
2IX1
ORA
4 SP2
ORA
3IX2
ORA
3EXT
ORA
2DIR
ORA
2IMM
CLI
1INH
PULH
1INH
DEC
1IX
DEC
3 SP1
DEC
2IX1
DECX
1INH
DECA
1INH
DEC
2DIR
BPL
2REL
BSET5
2DIR
2
ADD
4
ADD
3
ADD
5
ADD
4
ADD
4
ADD
3
ADD
2
ADD
2
SEI
2
PSHH
4
DBNZ
6
DBNZ
5
DBNZ
3
DBNZX
3
DBNZA
5
DBNZ
3
BMI
4
BCLR5
1IX
3 SP1
2IX1
4 SP2
3IX2
3EXT
2DIR
2IMM
1INH
1INH
2IX
4 SP1
3IX1
2INH
2INH
3DIR
2REL
2DIR
2
3
4
3
2
1
1
3
5
4
1
1
4
3
4
JMP
1IX
JMP
2IX1
JMP
3IX2
JMP
3EXT
JMP
2DIR
RSP
1INH
CLRH
1INH
INC
1IX
INC
3 SP1
INC
2IX1
INCX
1INH
INCA
1INH
INC
2DIR
BMC
2REL
BSET6
2DIR
4
5
6
5
4
4
1
2
4
3
1
1
3
3
4
JSR
1IX
JSR
2IX1
JSR
3IX2
JSR
3EXT
JSR
2DIR
BSR
2REL
NOP
1INH
TST
1IX
TST
3 SP1
TST
2IX1
TSTX
1INH
TSTA
1INH
TST
2DIR
BMS
2REL
BCLR6
2DIR
2
2
STX
LDX
4
LDX
3
LDX
5
LDX
4
LDX
4
LDX
3
LDX
2
LDX
1
STOP
4
MOV
4
MOV
4
MOV
5
MOV
3
BIL
4
BSET7
1IX
3 SP1
2IX1
4 SP2
3IX2
3EXT
2DIR
2IMM
*
1INH
2IX+D
3IMD
2DIX+
3DD
2REL
2DIR
4
STX
3
STX
5
STX
4
STX
4
STX
3
STX
2
AIX
1
TXA
1
WAIT
2
CLR
4
CLR
3
CLR
1
CLRX
1
CLRA
3
CLR
3
BIH
4
BCLR7
1IX
3 SP1
2IX1
4 SP2
3IX2
3EXT
2DIR
2IMM
1INH
1INH
1IX
3 SP1
2IX1
1INH
1INH
2DIR
2REL
2DIR
MSB
0 High Byte of Opcode in Hexadecimal
LSB
Cycles
Opcode Mnemonic
Number of Bytes / Addressing Mode
5
BRSET0
3DIR
Low Byte of Opcode in Hexadecimal 0
5
BRCLR0
1
3DIR
5
BRSET1
3DIR
2
5
0 1 2 3 4 5 6 9E6 7 8 9 A B C D 9ED E 9EE F
DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX
Bit Manipulation Branch Read-Modify-Write Control Register/Memory
MSB
BRSET0
3DIR
0
LSB
5
5
BRSET2
3DIR
BRCLR1
3DIR
4
3
5
5
BRSET3
3DIR
BRCLR2
3DIR
6
5
5
5
BRSET4
3DIR
BRCLR3
3DIR
8
7
5
BRSET5
A
3DIR
5
5
5
BRSET6
BRCLR5
3DIR
3DIR
BRCLR6
3DIR
B
C
D
5
BRCLR4
3DIR
9
5
5
BRSET7
BRCLR7
3DIR
3DIR
F
E
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset
IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment
DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with
IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment
*Pre-byte for stack pointer indexed instructions
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
82 Freescale Semiconductor
Page 83
Chapter 8
External Interrupt (IRQ)
8.1 Introduction
The IRQ (external interrupt) module provides a maskable interrupt input.
IRQ functionality is enabled by setting configuration register 2 (CONFIG2) IRQEN bit accordingly. A zero
disables the IRQ function and IRQ
function. See Chapter 5 Configuration Register (CONFIG) for more information on enabling the IRQ
will assume the other shared functionalities. A one enables the IRQ
pin.
The IRQ
location of this shared pin.
pin shares its pin with general-purpose input/output (I/O) port pins. See Figure 8-1 for port
8.2 Features
Features of the IRQ module include:
• A dedicated external interrupt pin IRQ
• IRQ interrupt control bits
• Programmable edge-only or edge and level interrupt sensitivity
• Automatic interrupt acknowledge
• Internal pullup device
8.3 Functional Description
A low level applied to the external interrupt request (IRQ) pin can latch a CPU interrupt request. Figure 8-2
shows the structure of the IRQ module.
Interrupt signals on the IRQ
following actions occurs:
• IRQ vector fetch. An IRQ vector fetch automatically generates an interrupt acknowledge signal that
clears the latch that caused the vector fetch.
• Software clear. Software can clear the IRQ latch by writing a 1 to the ACK bit in the interrupt status
and control register (INTSCR).
• Reset. A reset automatically clears the IRQ latch.
pin are latched into the IRQ latch. The IRQ latch remains set until one of the
The external IRQ
edge or falling edge and low level sensitive. The MODE bit in INTSCR controls the triggering sensitivity
of the IRQ
Freescale Semiconductor 83
pin.
pin is falling edge sensitive out of reset and is software-configurable to be either falling
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Page 84
External Interrupt (IRQ)
PTA0/AD0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
/KBI2/TCLK
PTA3/RST
PTB0/TCH0
PTB2/AD4
PTB3/AD5
PTB4/SLCRX
PTB5/SLCTX
/KBI3
PTB1
PTB6
PTB7
MC68HC908QL4
128 BYTES
USER RAM
INTERNAL OSC
INTERNAL CLOCK SOURCE
PTA
DDRA
M68HC08 CPU
PTB
DDRB
MC68HC908QL4
4096 BYTES
USER FLASH
4, 8, 12.8, or 25.6 MHz
KEYBOARD INTERRUPT
MODULE
EXTERNAL INTERRUPT
MODULE
AUTO WAKEUP
MODULE
LOW-VOLTAGE
INHIBIT
2-CHANNEL 16-BIT
TIMER MODULE
COP
MODULE
6-CHANNEL
10-BIT ADC
V
DD
V
SS
RST, IRQ: Pins have internal pull up device
All port pins have programmable pull up device (pullup/down on port A)
PTA[0:5]: Higher current sink and source capability
POWER SUPPLY
Figure 8-1. Block Diagram Highlighting IRQ Block and Pin
SLAVE LIN INTERFACE
CONTROLLER
DEVELOPMENT SUPPORT
MONITOR ROM
BREAK MODULE
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
84 Freescale Semiconductor
Page 85
RESET
ACK
Functional Description
IRQ VECTOR
FETCH
DECODER
INTERNAL ADDRESS BUS
IRQ
V
DD
INTERNAL
PULLUP
DEVICE
V
DD
DQ
IRQ LATCH
MODE
CK
CLR
SYNCHRONIZER
IMASK
HIGH
VOLTAGE
DETECT
IRQF
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQ
INTERRUPT
REQUEST
TO MODE
SELECT
LOGIC
Figure 8-2. IRQ Module Block Diagram
8.3.1 MODE = 1
If the MODE bit is set, the IRQ pin is both falling edge sensitive and low level sensitive. With MODE set,
both of the following actions must occur to clear the IRQ
• Return of the IRQ
pin to a high level. As long as the IRQ pin is low, the IRQ request remains active.
• IRQ vector fetch or software clear. An IRQ vector fetch generates an interrupt acknowledge signal
to clear the IRQ latch. Software generates the interrupt acknowledge signal by writing a 1 to ACK
in INTSCR. The ACK bit is useful in applications that poll the IRQ
the IRQ latch. Writing to ACK prior to leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ
edge that occurs after writing to ACK latches another interrupt request. If the IRQ mask bit, IMASK,
is clear, the CPU loads the program counter with the IRQ vector address.
interrupt request:
pin and require software to clear
pin. A falling
The IRQ vector fetch or software clear and the return of the IRQ
The interrupt request remains pending as long as the IRQ
pin to a high level may occur in any order.
pin is low. A reset will clear the IRQ latch and
the MODE control bit, thereby clearing the interrupt even if the pin stays low.
Use the BIH or BIL instruction to read the logic level on the IRQ
pin.
8.3.2 MODE = 0
If the MODE bit is clear, the IRQ pin is falling edge sensitive only. With MODE clear, an IRQ vector fetch
or software clear immediately clears the IRQ latch.
The IRQF bit in INTSCR can be read to check for pending interrupts. The IRQF bit is not affected by
IMASK, which makes it useful in applications where polling is preferred.
NOTE
When using the level-sensitive interrupt trigger, avoid false IRQ interrupts
by masking interrupt requests in the interrupt routine.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 85
Page 86
External Interrupt (IRQ)
8.4 Interrupts
The following IRQ source can generate interrupt requests:
• Interrupt flag (IRQF) — The IRQF bit is set when the IRQ
The IRQ interrupt mask bit, IMASK, is used to enable or disable IRQ interrupt requests.
pin is asserted based on the IRQ mode..
8.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
8.5.1 Wait Mode
The IRQ module remains active in wait mode. Clearing IMASK in INTSCR enables IRQ interrupt requests
to bring the MCU out of wait mode.
8.5.2 Stop Mode
The IRQ module remains active in stop mode. Clearing IMASK in INTSCR enables IRQ interrupt requests
to bring the MCU out of stop mode.
8.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the
second step clears the status bit.
8.7 I/O Signals
The IRQ module does not share its pin with any module on this MCU.
8.7.1 IRQ Input Pins (IRQ)
The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup
device.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
86 Freescale Semiconductor
Page 87
Registers
8.8 Registers
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks the IRQ interrupt request
• Controls triggering sensitivity of the IRQ
Bit 7654321Bit 0
Read:0000IRQF0
Write:
Reset:00000000
= Unimplemented
Figure 8-3. IRQ Status and Control Register (INTSCR)
IRQF — IRQ Flag Bit
This read-only status bit is set when the IRQ interrupt is pending.
1 = IRQ
0 = IRQ
interrupt pending
interrupt not pending
interrupt pin
ACK
IMASK MODE
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads 0.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables the IRQ interrupt request.
1 = IRQ interrupt request disabled
0 = IRQ interrupt request enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ
1 = IRQ
0 = IRQ
interrupt request on falling edges and low levels
interrupt request on falling edges only
pin.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 87
Page 88
External Interrupt (IRQ)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
88 Freescale Semiconductor
Page 89
Chapter 9
Keyboard Interrupt Module (KBI)
9.1 Introduction
The keyboard interrupt module (KBI) provides independently maskable external interrupts.
The KBI shares its pins with general-purpose input/output (I/O) port pins. See Figure 9-1 for port location
of these shared pins.
9.2 Features
Features of the keyboard interrupt module include:
• Keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt
mask
• Programmable edge-only or edge and level interrupt sensitivity
• Edge sensitivity programmable for rising or falling edge
• Level sensitivity programmable for high or low level
• KBI can be configured to use either internal or external pullup/pulldown devices using PTAPUE,
see 12.2.3 Port A Input Pullup/Down Enable Register
– When in internal device is enabled, pullup or pulldown device automatically configured based
on the polarity of edge or level detect
• Exit from low-power modes
9.3 Functional Description
The keyboard interrupt module controls the enabling/disabling of interrupt functions on the KBI pins.
These pins can be enabled/disabled independently of each other. See Figure 9-2.
9.3.1 Keyboard Operation
Writing to the KBIEx bits in the keyboard interrupt enable register (KBIER) independently enables or
disables each KBI pin. The polarity of the keyboard interrupt is controlled using the KBIPx bits in the
keyboard interrupt polarity register (KBIPR). Edge-only or edge and level sensitivity is controlled using the
MODEK bit in the keyboard status and control register (KBISCR).
Enabling a keyboard interrupt pin also enables its internal pullup or pulldown device based on the polarity
enabled and the corresponding port pullup/down enable bit, PTAPUEx see 12.2.3 Port A Input
Pullup/Down Enable Register. On falling edge or low level detection, a pullup device is configured. On
rising edge or high level detection, a pulldown device is configured.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 89
Page 90
Keyboard Interrupt Module (KBI)
PTA0/AD0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
/KBI2/TCLK
PTA3/RST
PTB0/TCH0
PTB2/AD4
PTB3/AD5
PTB4/SLCRX
PTB5/SLCTX
/KBI3
PTB1
PTB6
PTB7
MC68HC908QL4
128 BYTES
USER RAM
PTA
PTB
DDRA
DDRB
M68HC08 CPU
MC68HC908QL4
4096 BYTES
USER FLASH
INTERNAL OSC
INTERNAL CLOCK SOURCE
4, 8, 12.8, or 25.6 MHz
KEYBOARD INTERRUPT
MODULE
EXTERNAL INTERRUPT
MODULE
AUTO WAKEUP
MODULE
LOW-VOLTAGE
INHIBIT
2-CHANNEL 16-BIT
TIMER MODULE
COP
MODULE
6-CHANNEL
10-BIT ADC
V
DD
V
SS
RST, IRQ: Pins have internal pull up device
All port pins have programmable pull up device (pullup/down on port A)
PTA[0:5]: Higher current sink and source capability
POWER SUPPLY
Figure 9-1. Block Diagram Highlighting KBI Block and Pins
SLAVE LIN INTERFACE
CONTROLLER
DEVELOPMENT SUPPORT
MONITOR ROM
BREAK MODULE
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
90 Freescale Semiconductor
Page 91
Functional Description
The keyboard interrupt latch is set when one or more enabled keyboard interrupt inputs are asserted.
• If the keyboard interrupt sensitivity is edge-only, for KBIPx = 0, a falling (for KBIPx = 1, a rising)
edge on a keyboard interrupt input does not latch an interrupt request if another enabled keyboard
pin is already asserted. To prevent losing an interrupt request on one input because another input
remains asserted, software can disable the latter input while it is asserted.
• If the keyboard interrupt is edge and level sensitive, an interrupt request is present as long as any
enabled keyboard interrupt input is asserted.
INTERNAL BUS
VECTOR FETCH
DECODER
1
ACKK
RESET
AWUIREQ
0
S
KBIE0
TO PULLUP/
PULLDOWN ENABLE
(see Note)
1
0
S
KBIEx
TO PULLUP/
PULLDOWN ENABLE
(see Note)
MODEK
V
DD
DQ
KBI LATCH
CK
CLR
SYNCHRONIZER
IMASKK
KEYF
KEYBOARD
INTERRUPT
REQUEST
KBI0
KBIP0
KBIx
KBIPx
(SEE Figure 4-1)
NOTE:
To enable internal pullup/pulldown, requires both the KBIPx and the corresponding PTAPUEN to both be set.
Figure 9-2. Keyboard Interrupt Block Diagram
9.3.1.1 MODEK = 1
If the MODEK bit is set, the keyboard interrupt inputs are both edge and level sensitive. The KBIPx bit will
determine whether a edge sensitive pin detects rising or falling edges and on level sensitive pins whether
the pin detects low or high levels. With MODEK set, both of the following actions must occur to clear a
keyboard interrupt request:
• Return of all enabled keyboard interrupt inputs to a deasserted level. As long as any enabled
keyboard interrupt pin is asserted, the keyboard interrupt remains active.
• Vector fetch or software clear. A KBI vector fetch generates an interrupt acknowledge signal to
clear the KBI latch. Software generates the interrupt acknowledge signal by writing a 1 to ACKK in
KBSCR. The ACKK bit is useful in applications that poll the keyboard interrupt inputs and require
software to clear the KBI latch. Writing to ACKK prior to leaving an interrupt service routine can
also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 91
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Keyboard Interrupt Module (KBI)
on the keyboard interrupt inputs. An edge detect that occurs after writing to ACKK latches another
interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program
counter with the KBI vector address.
The KBI vector fetch or software clear and the return of all enabled keyboard interrupt pins to a deasserted
level may occur in any order.
Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a
keyboard interrupt input stays asserted.
9.3.1.2 MODEK = 0
If the MODEK bit is clear, the keyboard interrupt inputs are edge sensitive. The KBIPx bit will determine
whether an edge sensitive pin detects rising or falling edges. A KBI vector fetch or software clear
immediately clears the KBI latch.
The keyboard flag bit (KEYF) in KBSCR can be read to check for pending interrupts. The KEYF bit is not
affected by IMASKK, which makes it useful in applications where polling is preferred.
NOTE
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction register.
However, the data direction register bit must be a 0 for software to read the
pin.
9.3.2 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pullup or pulldown device if selected
to pull the pin to its deasserted level. Therefore a false interrupt can occur as soon as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting IMASKK in KBSCR.
2. Enable the KBI polarity by setting the appropriate KBIPx bits in KBIPR.
3. Enable the KBI pins by setting the appropriate KBIEx bits in KBIER.
4. Write to ACKK in KBSCR to clear any false interrupts.
5. Clear IMASKK.
An interrupt signal on an edge sensitive pin can be acknowledged immediately after enabling the pin. An
interrupt signal on an edge and level sensitive pin must be acknowledged after a delay that depends on
the external load.
9.4 Interrupts
The following KBI source can generate interrupt requests:
• Keyboard flag (KEYF) — The KEYF bit is set when any enabled KBI pin is asserted based on the
KBI mode and pin polarity. The keyboard interrupt mask bit, IMASKK, is used to enable or disable
KBI interrupt requests.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
92 Freescale Semiconductor
Page 93
Low-Power Modes
9.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
9.5.1 Wait Mode
The KBI module remains active in wait mode. Clearing IMASKK in KBSCR enables keyboard interrupt
requests to bring the MCU out of wait mode.
9.5.2 Stop Mode
The KBI module remains active in stop mode. Clearing IMASKK in KBSCR enables keyboard interrupt
requests to bring the MCU out of stop mode.
9.6 KBI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the
second step clears the status bit.
9.7 I/O Signals
The KBI module can share its pins with the general-purpose I/O pins. See Figure 9-1 for the port pins that
are shared.
9.7.1 KBI Input Pins (KBI5:KBI0)
Each KBI pin is independently programmable as an external interrupt source. KBI pin polarity can be
controlled independently. Each KBI pin when enabled can be configured to use an internal pullup/pulldown
device using the corresponding PTAPUEx bit see 12.2.3 Port A Input Pullup/Down Enable Register. The
selection of pullup or pulldown is automatically configured to match the polarity selected in KBIPR.
9.8 Registers
The following registers control and monitor operation of the KBI module:
• KBSCR (keyboard interrupt status and control register)
• KBIER (keyboard interrupt enable register)
• KBIPR (keyboard interrupt polarity register)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 93
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Keyboard Interrupt Module (KBI)
9.8.1 Keyboard Status and Control Register (KBSCR)
Features of the KBSCR:
• Flags keyboard interrupt requests
• Acknowledges keyboard interrupt requests
• Masks keyboard interrupt requests
• Controls keyboard interrupt triggering sensitivity
Bit 7654321Bit 0
Read:0000KEYF 0
Write:
Reset:00000000
= Unimplemented
Figure 9-3. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK
IMASKK MODEK
ACKK — Keyboard Acknowledge Bit
Writing a 1 to this write-only bit clears the KBI request. ACKK always reads 0.
IMASKK— Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the KBI latch from generating interrupt requests.
1 = Keyboard interrupt requests disabled
0 = Keyboard interrupt requests enabled
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard interrupt pins.
1 = Keyboard interrupt requests on edge and level
0 = Keyboard interrupt requests on edge only
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
94 Freescale Semiconductor
Page 95
Registers
9.8.2 Keyboard Interrupt Enable Register (KBIER)
KBIER enables or disables each keyboard interrupt pin.
Bit 7654321Bit 0
Read: 0
Write:
Reset:00000000
Figure 9-4. Keyboard Interrupt Enable Register (KBIER)
KBIE5–KBIE0 — Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard interrupt pin to latch KBI interrupt
requests.
1 = KBIx pin enabled as keyboard interrupt pin
0 = KBIx pin not enabled as keyboard interrupt pin
KBIEx bit does not automatically enable the internal pullup/pulldown
device. Internal pullup/pulldown device is selected using the corresponding
PTAPUEx bit. Refer to PTAPUE bit description, see 12.2.3 Port A Input
Pullup/Down Enable Register.
AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
= Unimplemented
NOTE
AWUIE bit is not used in conjunction with the keyboard interrupt feature. To
see a description of this bit, see Chapter 4 Auto Wakeup Module (AWU)
9.8.3 Keyboard Interrupt Polarity Register (KBIPR)
KBIPR determines the polarity of the enabled keyboard interrupt pin and enables the appropriate pullup
or pulldown device.
Bit 7654321Bit 0
Read: 0 0
Write:
Reset:00000000
= Unimplemented
Figure 9-5. Keyboard Interrupt Polarity Register (KBIPR)
KBIP5–KBIP0 — Keyboard Interrupt Polarity Bits
Each of these read/write bits enables the polarity of the keyboard interrupt detection.
1 = Keyboard polarity is high level and/or rising edge. Port pulldown is enabled if the corresponding
PTAPUE bit is set.
0 = Keyboard polarity is low level and/or falling edge. Port pullup is enabled if the corresponding
PTAPUE bit is set.
KBIP5 KBIP4 KBIP3 KBIP2 KBIP1 KBIP0
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 95
Page 96
Keyboard Interrupt Module (KBI)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
96 Freescale Semiconductor
Page 97
Chapter 10
Low-Voltage Inhibit (LVI)
10.1 Introduction
The low-voltage inhibit (LVI) module is provided as a system protection mechanism to prevent the MCU
from operating below a certain operating supply voltage level. The module has several configuration
options to allow functionality to be tailored to different system level demands.
The configuration registers (see Chapter 5 Configuration Register (CONFIG)) contain control bits for this
module.
10.2 Features
Features of the LVI module include:
• Programmable LVI reset
• Selectable LVI trip voltage
• Programmable stop mode operation
10.3 Functional Description
Figure 10-1 shows the structure of the LVI module. LVISTOP, LVIPWRD, LVITRIP, and LVIRSTD are
user selectable options found in the configuration register.
V
DD
STOP INSTRUCTION
LVISTOP
FROM CONFIGURATION REGISTER
FROM CONFIGURATION REGISTER
LVIRSTD
LVIPWRD
FROM CONFIGURATION REGISTER
0 IF V
> V
1 IF V
DD
≤ V
DD
LOW V
DD
DETECTOR
LVITRIP
FROM CONFIGURATION REGISTER
TRIPR
TRIPF
LVIOUT
LVI RESET
Figure 10-1. LVI Module Block Diagram
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor 97
Page 98
Low-Voltage Inhibit (LVI)
The LVI module contains a bandgap reference circuit and comparator. When the LVITRIP bit is cleared,
the default state at power-on reset, V
is configured for the lower VDD operating range. The actual
TRIPF
trip points are specified in 17.5 5-V DC Electrical Characteristics and 17.8 3.3-V DC Electrical
Characteristics.
Because the default LVI trip point after power-on reset is configured for low voltage operation, a system
requiring high voltage LVI operation must set the LVITRIP bit during system initialization. V
above the LVI trip rising voltage, V
, for the high voltage operating range or the MCU will immediately
TRIPR
must be
DD
go into LVI reset.
After an LVI reset occurs, the MCU remains in reset until V
rises above V
DD
. See Chapter 13 System
TRIPR
Integration Module (SIM) for the reset recovery sequence.
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and
can be used for polling LVI operation when the LVI reset is disabled.
The LVI is enabled out of reset. The following bits located in the configuration register can alter the default
conditions.
• Setting the LVI power disable bit, LVIPWRD, disables the LVI.
• Setting the LVI reset disable bit, LVIRSTD, prevents the LVI module from generating a reset.
• Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode.
• Setting the LVI trip point bit, LVITRIP, configures the trip point voltage (V
) for the higher VDD
TRIPF
operating range.
10.3.1 Polled LVI Operation
In applications that can operate at VDD levels below the V
the LVIOUT bit. In the configuration register, LVIPWRD must be cleared to enable the LVI module, and
LVIRSTD must be set to disable LVI resets.
level, software can monitor VDD by polling
TRIPF
10.3.2 Forced Reset Operation
In applications that require VDD to remain above the V
module to reset the MCU when V
falls below the V
DD
TRIPF
and LVIRSTD must be cleared to enable the LVI module and to enable LVI resets.
level, enabling LVI resets allows the LVI
TRIPF
level. In the configuration register, LVIPWRD
10.3.3 LVI Hysteresis
The LVI has hysteresis to maintain a stable operating condition. After the LVI has triggered (by having
V
fall below V
DD
V
. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is
TRIPR
approximately equal to V
), the MCU will remain in reset until VDD rises above the rising trip point voltage,
TRIPF
TRIPF
. V
is greater than V
TRIPR
by the typical hysteresis voltage, V
TRIPF
HYS
.
10.3.4 LVI Trip Selection
LVITRIP in the configuration register selects the LVI protection range. The default setting out of reset is
for the low voltage range. Because LVITRIP is in a write-once configuration register, the protection range
cannot be changed after initialization.
NOTE
The MCU is guaranteed to operate at a minimum supply voltage. The trip
point (V
Specifications for the actual trip point voltages.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
98 Freescale Semiconductor
) may be lower than this. See Chapter 17 Electrical
TRIPF
Page 99
LVI Interrupts
10.4 LVI Interrupts
The LVI module does not generate interrupt requests.
10.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
10.5.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
10.5.2 Stop Mode
If the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration
register is set, the LVI module remains active. If enabled to generate resets, the LVI module can generate
a reset and bring the MCU out of stop mode.
10.6 Registers
The LVI status register (LVISR) contains a status bit that is useful when the LVI is enabled and LVI reset
is disabled.
Bit 76 5 4 3 2 1Bit 0
Read:LVIOUT000000R
Write:
Reset:00000000
= Unimplemented R = Reserved
Figure 10-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V
when V
voltage rises above V
DD
TRIPR
Table 10-1. LVIOUT Bit Indication
VDD > V
V
< V
DD
V
< VDD < V
TRIPF
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
voltage falls below the V
DD
. (See Table 10-1).
V
DD
TRIPR
TRIPF
TRIPR
LVIOUT
0
1
Previous value
trip voltage and is cleared
TRIPF
Freescale Semiconductor 99
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Low-Voltage Inhibit (LVI)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
100 Freescale Semiconductor
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