Page 1
查询MC68HC908GZ32供应商
nc...
I
Freescale Semiconductor, Inc.
MC68HC908GZ60
MC68HC908GZ48
MC68HC908GZ32
Data Sheet
cale Semiconductor,
Frees
M68HC08
Microcontrollers
MOTOROLA.COM/SEMICONDUCTORS
MC68HC908GZ60/D
Rev. 1.0
5/2004
For More Information On This Product,
Go to: www.freescale.com
Page 2
Freescale Semiconductor, Inc.
nc...
I
cale Semiconductor,
Frees
For More Information On This Product,
Go to: www.freescale.com
Page 3
Freescale Semiconductor, Inc.
MC68HC908GZ60
MC68HC908GZ48
MC68HC908GZ32
Data Sheet
nc...
I
To provide the most up-to-date information, the revision of our documents on the
World Wide Web will be the most current. Your printed copy may be an earlier
revision. To verify you have the latest information available, refer to:
http://motorola.com/semiconductors
cale Semiconductor,
Frees
The following revision history table summarizes changes contained in this
document. For your convenience, the page number designators have been linked
to the appropriate location.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA 3
For More Information On This Product,
Go to: www.freescale.com
Page 4
Revision History
Freescale Semiconductor, Inc.
Revision History
Date
April,
2004
May,
2004
nc...
I
Revision
Level
N/A Initial release N/A
9.7.3 Keyboard Interrupt Polarity Register — Corrected the bit description
of the KBIP7–KBIP0 bits.
14.8.8 ESCI Prescaler Register — Reworked note under PDS2–PDS0
description for clarity.
Table 22-1. MC Order Numbers — Corrected order numbers. 367
Figure 22-1. Device Numbering System — Reworked diagram to reflect
1.0
correct order numbers.
Table A-1. MC Order Numbers — Corrected order numbers. 374
Figure A-3. Device Numbering System — Reworked diagr am to reflect
correct order numbers.
B.4 Ordering Information — Corrected order numbers. 378
Figure B-3. Device Numbering System — Reworked diagr am to reflect
correct order numbers.
Description
cale Semiconductor,
Page
Number(s)
132
234
367
374
378
Frees
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
4 Revision History MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 5
Freescale Semiconductor, Inc.
Data Sheet — MC68HC908GZ60
Section 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Section 3. Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . .65
Section 4. Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . .79
List of Sections
nc...
I
cale Semiconductor,
Frees
Section 5. Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . .99
Section 6. Computer Operating Properly (COP) Module. . . . . . . . . .103
Section 7. Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . .107
Section 8. External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Section 9. Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . .125
Section 10. Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Section 11. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . . . . . .141
Section 12. MSCAN08 Controller (MSCAN08) . . . . . . . . . . . . . . . . . .145
Section 13. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . . . . . . . . . .183
Section 14. Enhanced Serial Communications
Interface (ESCI) Module . . . . . . . . . . . . . . . . . . . . . . . . .205
Section 15. System Integration Module (SIM) . . . . . . . . . . . . . . . . . .241
Section 16. Serial Peripheral Interface (SPI) Module. . . . . . . . . . . . .261
Section 17. Timebase Module (TBM). . . . . . . . . . . . . . . . . . . . . . . . . .285
Section 18. Timer Interface Module (TIM1). . . . . . . . . . . . . . . . . . . . .291
Section 19. Timer Interface Module (TIM2). . . . . . . . . . . . . . . . . . . . .309
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA List of Sections 5
For More Information On This Product,
Go to: www.freescale.com
Page 6
List of Sections
nc...
I
Freescale Semiconductor, Inc.
Section 20. Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . . .333
Section 21. Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . .351
Section 22. Ordering Information
Appendix A. MC68HC908GZ48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
Appendix B. MC68HC908GZ32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
and Mechanical Specifications . . . . . . . . . . . . . . . . . . .367
cale Semiconductor,
Frees
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
6 List of Sections MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 7
Data Sheet — MC68HC908GZ60
1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2.1 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2.2 Features of the CPU08. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.3 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
nc...
I
cale Semiconductor,
Frees
1.5 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5.1 Power Supply Pins (V
1.5.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.5.3 External Reset Pin (RST
1.5.4 External Interrupt Pin (IRQ
1.5.5 CGM Power Supply Pins (V
1.5.6 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . 30
1.5.7 ADC Power Supply/Reference Pins
1.5.8 Port A Input/Output (I/O) Pins
1.5.9 Port B I/O Pins (PTB7/AD7–PTB0/AD0). . . . . . . . . . . . . . . . . . . . . . 30
1.5.10 Port C I/O Pins (PTC6–PTC0/CANTX). . . . . . . . . . . . . . . . . . . . . . . 30
1.5.11 Port D I/O Pins (PTD7/T2CH1–PTD0/SS
1.5.12 Port E I/O Pins (PTE5–PTE2, PTE1/RxD, and PTE0/TxD) . . . . . . . 31
1.5.13 Port F I/O Pins (PTF7/T2CH5–PTF0). . . . . . . . . . . . . . . . . . . . . . . . 31
1.5.14 Port G I/O Pins (PTG7/AD23–PTBG0/AD16). . . . . . . . . . . . . . . . . . 31
2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.4 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.5 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.6 FLASH-1 Memory (FLASH-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.6.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.6.2 FLASH-1 Control and Block Protect Registers. . . . . . . . . . . . . . . . . 49
2.6.2.1 FLASH-1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.6.2.2 FLASH-1 Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.6.3 FLASH-1 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Freescale Semiconductor, Inc.
Section 1. General Description
and VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
and V
DDA
(V
DDAD/VREFH
(PTA7/KBD7/AD15–PTA0/KBD0/AD8) . . . . . . . . . . . . . . . . . . . . 30
and V
SSAD/VREFL
) . . . . . . . . . . . . . . . . . . . 29
SSA
) . . . . . . . . . . . . . . . . . . . . . . . . 30
) . . . . . . . . . . . . . . . . . . . . 31
Section 2. Memory
Table of Contents
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Table of Contents 7
For More Information On This Product,
Go to: www.freescale.com
Page 8
Table of Contents
nc...
I
Freescale Semiconductor, Inc.
2.6.4 FLASH-1 Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.6.5 FLASH-1 Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.6.6 FLASH-1 Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.6.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.6.7.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.7 FLASH-2 Memory (FLASH-2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.7.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.7.2 FLASH-2 Control and Block Protect Registers. . . . . . . . . . . . . . . . . 57
2.7.2.1 FLASH-2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.7.2.2 FLASH-2 Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.7.3 FLASH-2 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.7.4 FLASH-2 Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.7.5 FLASH-2 Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.7.6 FLASH-2 Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.7.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.7.7.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
cale Semiconductor,
Frees
Section 3. Analog-to-Digital Converter (ADC)
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3.1 ADC Port I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.3.3 Conversion Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.3.4 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.3.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.3.6 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.4 Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.7.1 ADC Analog Power Pin (V
3.7.2 ADC Analog Ground Pin (V
3.7.3 ADC Voltage Reference High Pin (V
3.7.4 ADC Voltage Reference Low Pin (V
3.7.5 ADC Voltage In (V
3.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 72
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ADIN
). . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DDAD
). . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SSAD
). . . . . . . . . . . . . . . . . . . . 71
REFH
) . . . . . . . . . . . . . . . . . . . . 71
REFL
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
8 Table of Contents MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 9
nc...
I
cale Semiconductor,
Frees
Freescale Semiconductor, Inc.
3.8.2 ADC Data Register High and Data Register Low. . . . . . . . . . . . . . . 74
3.8.2.1 Left Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.8.2.2 Right Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.8.2.3 Left Justified Signed Data Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.8.2.4 Eight Bit Truncation Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.8.3 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table of Contents
Section 4. Clock Generator Module (CGM)
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.3.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.3.2 Phase-Locked Loop Circuit (PLL). . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.3.3 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.3.4 Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.3.5 Manual and Automatic PLL Bandwidth Modes. . . . . . . . . . . . . . . . . 82
4.3.6 Programming the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.3.7 Special Programming Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.3.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.3.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.4.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . 88
4.4.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . 88
4.4.4 PLL Analog Power Pin (V
4.4.5 PLL Analog Ground Pin (V
4.4.6 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . . . . . . . 88
4.4.7 Oscillator Enable in Stop Mode Bit (OSCENINSTOP) . . . . . . . . . . . 88
4.4.8 Crystal Output Frequency Signal (CGMXCLK). . . . . . . . . . . . . . . . . 89
4.4.9 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . . . . . . . . . 89
4.4.10 CGM CPU Interrupt (CGMINT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.5 CGM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.5.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.5.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.5.3 PLL Multiplier Select Register High . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.5.4 PLL Multiplier Select Register Low. . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.5.5 PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.7 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.7.3 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.8 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.8.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.8.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . . . . . . . . . 97
4.8.3 Choosing a Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
DDA
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SSA
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Table of Contents 9
For More Information On This Product,
Go to: www.freescale.com
Page 10
Table of Contents
nc...
I
cale Semiconductor,
Frees
Freescale Semiconductor, Inc.
Section 5. Configuration Register (CONFIG)
5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Section 6. Computer Operating Properly (COP) Module
6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.4 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.8 COP Module During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Section 7. Central Processor Unit (CPU)
7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.3.2 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.3.5 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.8 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
10 Table of Contents MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 11
nc...
I
cale Semiconductor,
Frees
Freescale Semiconductor, Inc.
Table of Contents
Section 8. External Interrupt (IRQ)
8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.4 IRQ
8.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8.6 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Section 9. Keyboard Interrupt Module (KBI)
9.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.4 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.6 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . 130
9.7 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.7.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . 130
9.7.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 131
9.7.3 Keyboard Interrupt Polarity Register. . . . . . . . . . . . . . . . . . . . . . . . 132
Section 10. Low-Power Modes
10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.1.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.1.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.2 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.2.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.2.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.3 Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.3.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.3.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.4 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.4.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.4.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.5 Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.6 Computer Operating Properly Module (COP). . . . . . . . . . . . . . . . . . . . 135
10.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Table of Contents 11
For More Information On This Product,
Go to: www.freescale.com
Page 12
Table of Contents
nc...
I
cale Semiconductor,
Frees
Freescale Semiconductor, Inc.
10.7 External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.8 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.8.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.9 Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.9.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.10 Enhanced Serial Communications Interface Module (ESCI) . . . . . . . . 136
10.10.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.11 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . 137
10.11.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.12 Timer Interface Module (TIM1 and TIM2). . . . . . . . . . . . . . . . . . . . . . . 137
10.12.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.12.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.13 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.13.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.13.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.14 Motorola Scalable Controller Area Network Module (MSCAN) . . . . . . 138
10.14.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.14.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.15 Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.16 Exiting Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Section 11. Low-Voltage Inhibit (LVI)
11.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
11.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
11.3.1 Polled LVI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
11.3.2 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
11.3.3 Voltage Hysteresis Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
11.3.4 LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
11.4 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
11.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
12 Table of Contents MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 13
nc...
I
cale Semiconductor,
Frees
Freescale Semiconductor, Inc.
Table of Contents
Section 12. MSCAN08 Controller (MSCAN08)
12.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.3 External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.4 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.4.1 Background. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.4.2 Receive Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.4.3 Transmit Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.5 Identifier Acceptance Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.6.1 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.6.2 Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.7 Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.8.1 MSCAN08 Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.8.2 MSCAN08 Soft Reset Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.8.3 MSCAN08 Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.8.4 CPU Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.8.5 Programmable Wakeup Function. . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.9 Timer Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.10 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.11 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.12 Programmer’s Model of Message Storage. . . . . . . . . . . . . . . . . . . . . . 164
12.12.1 Message Buffer Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.12.2 Identifier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.12.3 Data Length Register (DLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.12.4 Data Segment Registers (DSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.12.5 Transmit Buffer Priority Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.13 Programmer’s Model of Control Registers . . . . . . . . . . . . . . . . . . . . . . 168
12.13.1 MSCAN08 Module Control Register 0 . . . . . . . . . . . . . . . . . . . . . . 169
12.13.2 MSCAN08 Module Control Register 1 . . . . . . . . . . . . . . . . . . . . . . 171
12.13.3 MSCAN08 Bus Timing Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.13.4 MSCAN08 Bus Timing Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.13.5 MSCAN08 Receiver Flag Register (CRFLG) . . . . . . . . . . . . . . . . . 174
12.13.6 MSCAN08 Receiver Interrupt Enable Register . . . . . . . . . . . . . . . 176
12.13.7 MSCAN08 Transmitter Flag Register. . . . . . . . . . . . . . . . . . . . . . . 177
12.13.8 MSCAN08 Transmitter Control Register. . . . . . . . . . . . . . . . . . . . . 178
12.13.9 MSCAN08 Identifier Acceptance Control Register. . . . . . . . . . . . . 179
12.13.10 MSCAN08 Receive Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . 180
12.13.11 MSCAN08 Transmit Error Counter. . . . . . . . . . . . . . . . . . . . . . . . . 180
12.13.12 MSCAN08 Identifier Acceptance Registers . . . . . . . . . . . . . . . . . . 181
12.13.13 MSCAN08 Identifier Mask Registers (CIDMR0–CIDMR3). . . . . . . 182
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Table of Contents 13
For More Information On This Product,
Go to: www.freescale.com
Page 14
Table of Contents
nc...
I
cale Semiconductor,
Frees
Freescale Semiconductor, Inc.
Section 13. Input/Output (I/O) Ports
13.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
13.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
13.2.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
13.2.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
13.2.3 Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . 189
13.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
13.3.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
13.3.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
13.4 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
13.4.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
13.4.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
13.4.3 Port C Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . 194
13.5 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
13.5.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
13.5.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
13.5.3 Port D Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . 197
13.6 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
13.6.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
13.6.2 Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
13.7 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
13.7.1 Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
13.7.2 Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
13.8 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
13.8.1 Port G Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
13.8.2 Data Direction Register G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Section 14. Enhanced Serial Communications
Interface (ESCI) Module
14.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
14.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
14.3 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
14.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
14.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
14.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
14.4.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
14.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
14.4.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
14.4.2.5 Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . 213
14.4.2.6 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
14.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
14.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
14.4.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
14 Table of Contents MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 15
nc...
I
cale Semiconductor,
Frees
Freescale Semiconductor, Inc.
14.4.3.3 Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
14.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
14.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
14.4.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
14.4.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
14.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
14.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
14.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
14.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
14.6 ESCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 221
14.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
14.7.1 PTE0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
14.7.2 PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
14.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
14.8.1 ESCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
14.8.2 ESCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
14.8.3 ESCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
14.8.4 ESCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
14.8.5 ESCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
14.8.6 ESCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
14.8.7 ESCI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
14.8.8 ESCI Prescaler Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
14.9 ESCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
14.9.1 ESCI Arbiter Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
14.9.2 ESCI Arbiter Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
14.9.3 Bit Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
14.9.4 Arbitration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table of Contents
Section 15. System Integration Module (SIM)
15.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
15.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . 244
15.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
15.2.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . 244
15.2.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . 244
15.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
15.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
15.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . 246
15.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
15.3.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . 248
15.3.2.3 Illegal Opcode Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
15.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
15.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 248
15.3.2.6 Monitor Mode Entry Module Reset (MODRST). . . . . . . . . . . . . . 248
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Table of Contents 15
For More Information On This Product,
Go to: www.freescale.com
Page 16
Table of Contents
nc...
I
Freescale Semiconductor, Inc.
15.4 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
15.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . 249
15.4.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . . . . . . . 249
15.4.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
15.5 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
15.5.1 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
15.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
15.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
15.5.1.3 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
15.5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
15.5.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
15.5.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . 255
15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
15.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
15.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
15.7 SIM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
15.7.1 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
15.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
15.7.3 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
cale Semiconductor,
Frees
Section 16. Serial Peripheral Interface (SPI) Module
16.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
16.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
16.3.1 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
16.3.2 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
16.4 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
16.4.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . 266
16.4.2 Transmission Format When CPHA = 0. . . . . . . . . . . . . . . . . . . . . . 266
16.4.3 Transmission Format When CPHA = 1. . . . . . . . . . . . . . . . . . . . . . 267
16.4.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
16.5 Queuing Transmission Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
16.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
16.6.1 Overflow Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
16.6.2 Mode Fault Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
16.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
16.8 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
16.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
16.9.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
16.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
16.10 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
16.11 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
16.11.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
16.11.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
16 Table of Contents MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 17
Freescale Semiconductor, Inc.
16.11.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
16.11.4 SS
16.12 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
16.12.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
16.12.2 SPI Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 280
16.12.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table of Contents
(Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Section 17. Timebase Module (TBM)
17.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
17.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
17.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
17.5 TBM Interrupt Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
nc...
I
17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
17.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
17.7 Timebase Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
cale Semiconductor,
Frees
Section 18. Timer Interface Module (TIM1)
18.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
18.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
18.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
18.3.1 TIM1 Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
18.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
18.3.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
18.3.3.1 Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
18.3.3.2 Buffered Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
18.3.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
18.3.4.1 Unbuffered PWM Signal Generation. . . . . . . . . . . . . . . . . . . . . . 297
18.3.4.2 Buffered PWM Signal Generation. . . . . . . . . . . . . . . . . . . . . . . . 298
18.3.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
18.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
18.5 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
18.6 TIM1 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
18.7 Input/Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
18.8 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
18.8.1 TIM1 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 300
18.8.2 TIM1 Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
18.8.3 TIM1 Counter Modulo Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 303
18.8.4 TIM1 Channel Status and Control Registers . . . . . . . . . . . . . . . . . 303
18.8.5 TIM1 Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Table of Contents 17
For More Information On This Product,
Go to: www.freescale.com
Page 18
Table of Contents
nc...
I
cale Semiconductor,
Frees
Freescale Semiconductor, Inc.
Section 19. Timer Interface Module (TIM2)
19.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
19.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
19.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
19.3.1 TIM2 Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
19.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
19.3.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
19.3.3.1 Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
19.3.3.2 Buffered Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
19.3.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
19.3.4.1 Unbuffered PWM Signal Generation. . . . . . . . . . . . . . . . . . . . . . 318
19.3.4.2 Buffered PWM Signal Generation. . . . . . . . . . . . . . . . . . . . . . . . 318
19.3.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
19.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
19.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
19.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
19.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
19.6 TIM2 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
19.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
19.7.1 TIM2 Clock Pin (T2CH0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
19.7.2 TIM2 Channel I/O Pins (T2CH5:T2CH2 and T2CH1:T2CH0) . . . . 322
19.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
19.8.1 TIM2 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 323
19.8.2 TIM2 Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
19.8.3 TIM2 Counter Modulo Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 325
19.8.4 TIM2 Channel Status and Control Registers . . . . . . . . . . . . . . . . . 326
19.8.5 TIM2 Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Section 20. Development Support
20.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
20.2 Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
20.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
20.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . 336
20.2.1.2 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
20.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
20.2.2 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
20.2.2.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . 337
20.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
20.2.2.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
20.2.2.4 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
20.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
20.3 Monitor Module (MON). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
20.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
20.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
18 Table of Contents MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 19
nc...
I
cale Semiconductor,
Frees
Freescale Semiconductor, Inc.
20.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
20.3.1.3 Monitor Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
20.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
20.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
20.3.1.6 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
20.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
20.3.2 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Table of Contents
Section 21. Electrical Specifications
21.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
21.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
21.3 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
21.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
21.5 5.0-Vdc Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
21.6 3.3-Vdc Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
21.7 5.0-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
21.8 3.3-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
21.9 Clock Generation Module (CGM) Characteristics. . . . . . . . . . . . . . . . . 358
21.9.1 CGM Component Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 358
21.9.2 CGM Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
21.10 5.0-Volt ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
21.11 3.3-Volt ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
21.12 5.0-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
21.13 3.3-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
21.14 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 365
21.15 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Section 22. Ordering Information
and Mechanical Specifications
22.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
22.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
22.3 32-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . . . . . . . . 368
22.4 48-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . . . . . . . . 369
22.5 64-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Appendix A. MC68HC908GZ48
A.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
A.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
A.3 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
A.4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Table of Contents 19
For More Information On This Product,
Go to: www.freescale.com
Page 20
Table of Contents
nc...
I
Freescale Semiconductor, Inc.
B.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
B.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
B.3 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
B.4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Appendix B. MC68HC908GZ32
cale Semiconductor,
Frees
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
20 Table of Contents MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 21
Freescale Semiconductor, Inc.
Data Sheet — MC68HC908GZ60
1.1 Introduction
The MC68HC908GZ60, MC68HC908GZ48, and MC68HC908GZ32 are members
of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units
(MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and
package types.
Section 1. General Description
nc...
I
1.2 Features
1.2.1 Standard Features
cale Semiconductor,
Frees
The information contained in this document pertains to all three devices with the
exceptions noted in Appendix A. MC68HC908GZ48 and Appendix B.
MC68HC908GZ32.
For convenience, features have been organized to reflect:
• Standard features
• Features of the CPU08
Features of the MC68HC908GZ60 include:
• High-performance M68HC08 architecture optimized for C-compilers
• Fully upward-compatible object code with M6 805, M146805, and M68HC05
Families
• 8-MHz internal bus frequency
• Clock generation module supporting 1-MHz to 8-MHz crystals
• MSCAN08 (Motorola scalable controller area network) controller
(implementing 2.0b protocol as defined in BOSCH specification dated
September 1991)
• FLASH program memory security
• On-chip programming firmware for use with host personal computer which
does not require high voltage for entry
• In-system programming (ISP)
(1)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA General Description 21
For More Information On This Product,
Go to: www.freescale.com
Page 22
General Description
nc...
I
cale Semiconductor,
Frees
Freescale Semiconductor, Inc.
• System protection features:
– Optional computer operating properly (COP) reset
– Low-voltage detection with optional reset and selectable trip points for
– Illegal opcode detection with reset
– Illegal address detection with reset
• Low-power design; fully static with stop and wait modes
• Standard low-power modes of operation:
– Wait mode
– Stop mode
• Master reset pin and power-on reset (POR)
• On-chip FLASH memory:
– MC68HC908GZ60 — 60 Kbytes
– MC68HC908GZ48 — 48 Kbytes
– MC68HC908GZ32 — 32 Kbytes
• Random-access memory (RAM):
– MC68HC908GZ60 — 2048 bytes
– MC68HC908GZ48 — 1536 bytes
– MC68HC908GZ32 — 1536 bytes
• Serial peripheral interface (SPI) module
• Enhanced serial communications interface (ESCI) module
• One 16-bit, 2-channel timer interface module (TIM1) with selectable input
capture, output compare, and pulse-width modulation (PWM) capability on
each channel
• One 16-bit, 6-channel timer interface module (TIM2) with selectable input
capture, output compare, and pulse-width modulation (PWM) capability on
each channel
• Timebase module with clock prescaler circuitry for eight user selectable
periodic real-time interrupts with optional active clock source during stop
mode for periodic wakeup from stop using an external crystal
• 24-channel, 10-bit successive approximation analog-to-digital converter
(ADC)
• 8-bit keyboard wakeup port with software selectable rising or falling edge
detect, as well as high or low level detection
• Up to 53 general-purpose input/output (I/O) pins, including:
– 40 shared-function I/O pins, depending on package choice
– Up to 13 dedicated I/O pins, depending on package choice
• Selectable pullups on inputs only on ports A, C, and D. Selection is on an
individual port bit basis. During output mode, pullups are disengaged.
• Internal pullups on IRQ
• High current 10-mA sink/source capability on all port pins
3.3-V and 5.0-V operation
and RST to reduce customer system cost
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
22 General Description MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 23
nc...
I
cale Semiconductor,
Frees
Freescale Semiconductor, Inc.
• Higher current 20-mA sink/source capability on PTC0–PTC4 and
PTF0–PTF3
• User selectable clockout feature with divide by 1, 2, and 4 of the bus or
crystal frequency
• User selection of having the o scillator enabled or disabled during stop mode
• BREAK module (BRK) to allow single breakpoint setting during
in-circuit debugging
• Available packages:
– 32-pin low-profile quad flat pack (LQFP)
– 48-pin low-profile quad flat pack (LQFP)
– 64-pin quad flat pack (QFP)
• Specific features in 32-pin LQFP are:
– Port A is only 4 bits: PTA0–PTA3; shared with ADC and KBI modules
– Port B is only 6 bits: PTB0–PTB5; shared with ADC module
– Port C is only 2 bits: PTC0–PTC1; shared with MSCAN module
– Port D is only 7 bits: PTD0–PTD6; shared with SPI, TIM1 and TIM2
– Port E is only 2 bits: PTE0–PTE1; shared with ESCI module
• Specific features in 48-pin LQFP are:
– Port A is 8 bits: PTA0–PTA7; shared with ADC and KBI modules
– Port B is 8 bits: PTB0–PTB7; shared with ADC module
– Port C is only 7 bits: PTC0–PTC6; shared with MSCAN module
– Port D is 8 bits: PTD0–PTD7; shared with SPI, TIM1, and TIM2 modules
– Port E is only 6 bits: PTE0–PTE5; shared with ESCI module
• Specific features in 64-pin QFP are:
– Port A is 8 bits: PTA0–PTA7; shared with ADC and KBI modules
– Port B is 8 bits: PTB0–PTB7; shared with ADC module
– Port C is only 7 bits: PTC0–PTC6; shared with MSCAN module
– Port D is 8 bits: PTD0–PTD7; shared with SPI, TIM1, andTIM2 modules
– Port E is only 6 bits: PTE0–PTE5; shared with ESCI module
– Port F is 8 bits: PTF0–PTF7; shared with TIM2 module
– Port G is 8 bits; PTG0–PTG7; shared with ADC module
General Description
Features
modules
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA General Description 23
For More Information On This Product,
Go to: www.freescale.com
Page 24
General Description
1.2.2 Features of the CPU08
nc...
I
1.3 MCU Block Diagram
Freescale Semiconductor, Inc.
Features of the CPU08 include:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
cale Semiconductor,
Frees
Figure 1-1 shows the structure of the MC68HC908GZ60. Refer to Appendix A.
MC68HC908GZ48 and Appendix B. MC68HC908GZ32.
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
24 General Description MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 25
Freescale Semiconductor, Inc.
General Description
MCU Block Diagram
(2)
(2)
PTD3/SPSCK
PTD2/MOSI
PORTD
DDRD
COMPUTER OPERATING
(2)
(2)
PTD1/MISO
PTD0/SS/MCLK
PROPERLY MODULE
SERIAL PERIPHERAL
INTERFACE MODULE
PTE5–PTE2
PTE1/RxD
DDRE
MONITOR MODE ENTRY
PTE0/TxD
PORTE
MODULE
PTF6/T2CH4
PTF7/T2CH5
MODULE
SECURITY
PTF5/T2CH3
PTF4/T2CH2
PORTF
DDRF
MODULE
MEMORY MAP
(3)
PTF3–PFT0
MODULE
CONFIGURATION REGISTER 1–2
PTG7/AD23–PTG0/AD16
PORTG
DDRG
MSCAN
MODULE
Figure 1-1. MC68HC908GZ60 Block Diagram
(2)
TX
PTD7/T2CH1
PTC0/CAN
MODULE
6-CHANNEL TIMER INTERFACE
(2)
(2, 3)
(2, 3)
(2, 3)
PTC3
(2, 3)
PTC2
PORTC
DDRC
2-CHANNEL TIMER INTERFACE
RX
PTC1/CAN
MODULE
(2)
(2)
(2, 3)
PTC6
PTC5
PTA7/KBD7/AD15–PTA0/KBD0/AD8
PORTA
nc...
I
INTERNAL BUS
DDRA
MODULE
PROGRAMMABLE TIMEBASE
PTB7/AD7–PTB0/AD0
PORTB
DDRB
MODULE
DUAL VOLTAGE
SINGLE BREAKPOINT BREAK
PTC4
8-BIT KEYBOARD
INTERRUPT MODULE
LOW-VOLTAGE INHIBIT MODULE
(2)
(2)
(2)
PTD6/T2CH0
PTD5/T1CH1
PTD4/T1CH0
COMMUNICATIONS
ENHANCED SERIAL
INTERFACE MODULE
cale Semiconductor,
Frees
UNIT (ALU)
ARITHMETIC/LOGIC
M68HC08 CPU
CPU
REGISTERS
CONTROL AND STATUS REGISTERS — 64 BYTES
USER FLASH — 62,078 BYTES
USER RAM — 2048 BYTES
MONITOR ROM
USER FLASH VECTOR SPACE — 52 BYTES
1–8 MHz OSCILLATOR
CLOCK GENERATOR MODULE
OSC1
OSC2
PHASE LOCKED LOOP
CGMXFC
SYSTEM INTEGRATION
(1)
MODULE
RST
SINGLE EXTERNAL
INTERRUPT MODULE
(1)
IRQ
CONVERTER MODULE
10-BIT ANALOG-TO-DIGITAL
REFL
REFH
/V
/V
SSAD
DDAD
V
V
MODULE
POWER-ON RESET
V
DD
POWER
SS
DDA
V
V
V
SSA
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA General Description 25
For More Information On This Product,
Go to: www.freescale.com
1. Pin contains integrated pullup device.
2. Ports are software configurable with pullup device if input port or pullup/pulldown device for keyboard input.
3. Higher current drive port pins
Page 26
General Description
1.4 Pin Assignments
Figure 1-2, Figure 1-3, and Figure 1-4 illustrate the pin assignments for the 32-pin
LQFP, 48-pin LQFP, and 64-pin QFP respectively.
Freescale Semiconductor, Inc.
TX
OSC1
OSC2
32
RST
1
PTE0/TxD
nc...
I
PTE1/RxD
IRQ
PTD0/SS/MCLK
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
31
2
3
4
5
6
7
8
9
10
SS
DD
V
V
SSAVDDA
CGMXFC
V
29
30
11
12
PTD4/T1CH0
PTD5/T1CH1
PTC1/CANRXPTC0/CAN
27
28
13
14
PTB0/AD0
PTD6/T2CH0
Figure 1-2. 32-Pin LQFP Pin Assignments
cale Semiconductor,
26
15
PTB1/AD1
PTA3/KBD3/AD11
25
24
23
22
21
20
19
18
17
16
PTB2/AD2
PTA2/KBD2/AD10
PTA1/KBD1/AD9
PTA0/KBD0/AD8
V
SSAD/VREFL
V
DDAD/VREFH
PTB5/AD5
PTB4/AD4
PTB3/AD3
Frees
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
26 General Description MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 27
Freescale Semiconductor, Inc.
RX
TX
General Description
Pin Assignments
PTD4/T1CH0
SSAVDDA
CGMXFC
V
46
45
15
16
PTD5/T1CH1
PTD6/T2CH0
PTC1/CAN
44
43
17
18
PTD7/T2CH1
PTC0/CAN
42
19
PTC2
PTA7/KBD7/AD15
41
20
PTC3
PTA5/KBD5/AD13
PTA6/KBD6/AD14
40
39
21
22
PTC4
PTB0/AD0
PTA3/KBD3/AD11
PTA4/KBD4/AD12
37
38
36
35
34
33
32
31
30
29
28
27
26
23
PTB1/AD1
25
24
PTB2/AD2
PTA2/KBD2/AD10
PTA1/KBD1/AD9
PTA0/KBD0/AD8
PTC6
PTC5
V
SSAD/VREFL
V
DDAD/VREFH
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
OSC1
OSC2
48
RST
1
PTE0/TxD
PTE1/RxD
PTE2
PTE3
PTE4
nc...
I
PTE5
PTD0/SS/MCLK
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
IRQ
2
3
4
5
6
7
8
9
10
12
47
11
14
13
SS
DD
V
V
Figure 1-3. 48-Pin LQFP Pin Assignments
cale Semiconductor,
Frees
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA General Description 27
For More Information On This Product,
Go to: www.freescale.com
Page 28
General Description
nc...
I
RST
PTE0/TxD
PTE1/RxD
PTE2
PTE3
PTE4
PTE5
PTF0
PTF1
Freescale Semiconductor, Inc.
OSC1
OSC2
CGMXFC
64
63 62 61 60
1
2
3
4
5
6
7
8
9
V
SSA
V
DDA
PTC1/CAN
TX
RX
PTC0/CAN
PTG6/AD22
PTG7/AD23
56575859
PTG4/AD20
PTG5/AD21
PTA5/KBD5/AD13
PTA4/KBD4/AD12
PTA6/KBD6/AD14
PTA7/KBD7/AD15
PTA3/KBD3/AD11
49
505152535455
PTA2/KBD2/AD10
48
PTA1/KBD1/AD9
47
46
PTA0/KBD0/AD8
45
PTC6
44
PTC5
43
PTG3/AD19
42
PTG2/AD18
41
PTG1/AD17
40
PTG0/AD16
PTF2
PTF3
IRQ
PTD0/SS/MCLK
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
cale Semiconductor,
Frees
1.5 Pin Functions
1.5.1 Power Supply Pins (V
10
11
12
13
14
15
16
27
PTC2
PTF7/T2CH5
28 29 30 31
PTC4
PTC3
23
PTD7/T2CH1
24 25 26
PTF5/T2CH3
PTF4/T2CH2
PTF6/T2CH4
18
19
20 21 22
17 32
SS
DD
V
V
PTD5/T1CH1
PTD4/T1CH0
PTD6/T2CH0
Figure 1-4. 64-Pin QFP Pin Assignments
Descriptions of the pin functions are provided here.
and VSS)
DD
PTB0/AD0
PTB1/AD1
39
38
37
36
35
34
PTB2/AD2
33
V
SSAD/VREFL
V
DDAD/VREFH
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
and VSS are the power supply and ground pins. The MCU operates from a
V
DD
single power supply.
Fast signal transitions on MCU pins place high, short-duration current demands on
the power supply. To prevent noise problems, take special care to provide power
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
28 General Description MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 29
Freescale Semiconductor, Inc.
supply bypassing at the MCU as Figure 1-5 shows. Place the C1 bypass capacitor
as close to the MCU as possible. Use a high-frequency-response ceramic
capacitor for C1. C2 is an optional bulk current bypass capacitor for use in
applications that require the port pins to source high current levels.
General Description
Pin Functions
MCU
nc...
I
1.5.2 Oscillator Pins (OSC1 and OSC2)
OSC1 and OSC2 are the connections for an external crystal, resonator, or clock
circuit. See Section 4. Clock Generator Module (CGM).
1.5.3 External Reset Pin (RST
cale Semiconductor,
A low on the RST
allowing a reset of the entire system. It is driven low when any internal reset source
is asserted. This pin contains an internal pullup resistor. See Section 15. System
Integration Module (SIM).
V
DD
C1
0.1 µF
+
C2
V
DD
Note: Component values shown represent typical applications.
Figure 1-5. Power Supply Bypassing
)
pin forces the MCU to a known startup state. RST is bidirectional,
V
SS
Frees
1.5.4 External Interrupt Pin (IRQ
is an asynchronous external interrupt pin. This pin contains an internal pullup
IRQ
resistor. See Section 8. External Interrupt (IRQ).
1.5.5 CGM Power Supply Pins (V
and V
V
DDA
generator module (CGM). Decoupling of these pins should be as per the digital
supply. See Section 4. Clock Generator Module (CGM).
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA General Description 29
)
and V
DDA
are the power supply pins for the analog portion of the clock
SSA
SSA
)
For More Information On This Product,
Go to: www.freescale.com
Page 30
Freescale Semiconductor, Inc.
General Description
1.5.6 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. See Section 4.
Clock Generator Module (CGM).
1.5.7 ADC Power Supply/Reference Pins (V
DDAD
and V
REFH
SSAD
and V
V
(ADC). V
high reference supply for the ADC, and by default the V
externally filtered and connected to the same voltage potential as V
low reference supply for the ADC, and by default the V
connected to the same voltage potential as V
Converter (ADC).
nc...
1.5.8 Port A Input/Output (I/O) Pins (PTA7/KBD7/AD15–PTA0/KBD0/AD8)
I
PTA7–PTA0 are general-purpose, bidirectional I/O port pins. Any or all of the port
A pins can be programmed to serve as keyboard interrupt pins or used as
analog-to-digital inputs. PTA7–PTA4 are only available on the 48-pin LQFP and
64-pin QFP packages. See Section 13. Input/Output (I/O) Ports, Section 9.
Keyboard Interrupt Module (KBI), and Section 3. Analog-to-Digital Converter
(ADC).
These port pins also have selectable pullups when configured for input mode. The
pullups are disengaged when configured for output mode. The pullups are
selectable on an individual port bit basis.
1.5.9 Port B I/O Pins (PTB7/AD7–PTB0/AD0)
PTB7–PTB0 are general-purpose, bidirectional I/O port pins that can also be used
for analog-to-digital converter (ADC) inputs. PTB7–PTB6 are only available on the
cale Semiconductor,
1.5.10 Port C I/O Pins (PTC6–PTC0/CAN
Frees
48-pin LQFP and 64-pin QFP packages. See Section 13. Input/Output (I/O)
Ports and Section 3. Analog-to-Digital Converter (ADC).
PTC6 and PTC5 are general-purpose, bidirectional I/O port pins.
DDAD/VREFH
are the power supply pins to the analog-to-digital converter
are the reference voltage pins for the ADC. V
REFL
)
TX
and V
SSAD/VREFL
. See Section 3. Analog-to-Digital
SS
)
DDAD/VREFH
DD
SSAD/VREFL
REFH
pin should be
. V
REFL
pin should be
is the
is the
PTC4–PTC0 are general-purpose, bidirectional I/O port pins that contain higher
current sink/source capability. PTC6–PTC2 are only available on the 48-pin LQFP
and 64-pin QFP packages. See Section 13. Input/Output (I/O) Ports.
PTC1 and PTC0 can be programmed to be MSCAN08 pins.
These port pins also have selectable pullups when configured for input mode. The
pullups are disengaged when configured for output mode. The pullups are
selectable on an individual port bit basis.
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
30 General Description MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 31
Freescale Semiconductor, Inc.
1.5.11 Port D I/O Pins (PTD7/T2CH1–PTD0/SS)
PTD7–PTD0 are special-function, bidirectional I/O port pins. PTD3–PTD0 can be
programmed to be serial peripheral interface (SPI) pins, while PTD7–PTD4 can be
individually programmed to be timer interface module (TIM1 and TIM2) pins. PTD0
can be used to output a clock, MCLK. PTD7 is only available on the 48-pin LQFP
and 64-pin QFP packages. See Section 18. Timer Interface Module (TIM1),
Section 19. Timer Interface Module (TIM2), Section 16. Serial Peripheral
Interface (SPI) Module, Section 13. Input/Output (I/O) Ports. and Section 5.
Configuration Register (CONFIG).
These port pins also have selectable pullups when configured for input mode. The
pullups are disengaged when configured for output mode. The pullups are
selectable on an individual port bit basis.
nc...
1.5.12 Port E I/O Pins (PTE5–PTE2, PTE1/RxD, and PTE0/TxD)
I
PTE5–PTE0 are general-purpose, bidirectional I/O port pins. PTE1 and PTE0 can
also be programmed to be enhanced serial communications interface (ESCI) pins.
PTE5–PTE2 are only available on the 48-pin LQFP and 64-pin QFP packages. See
Section 14. Enhanced Serial Communications Interface (ESCI) Module and
Section 13. Input/Output (I/O) Ports.
General Description
Pin Functions
1.5.13 Port F I/O Pins (PTF7/T2CH5–PTF0)
PTF7–PTF4 are special-function, bidirectional I/O port pins that can be individually
programmed to be timer interface module (TIM2) pins.
PTF3–PTF0 are general-purpose, bidirectional I/O port pins that contain higher
current sink/source capability.
PTF7–PTF0 are only available on the 64-pin QFP package. See Section 18.
cale Semiconductor,
1.5.14 Port G I/O Pins (PTG7/AD23–PTBG0/AD16)
Frees
NOTE: Any unused inputs and I/O ports should be tied to an appropriate logic level (either
Timer Interface Module (TIM1), Section 19. Timer Interface Module (TIM2), and
Section 13. Input/Output (I/O) Ports.
PTG7–PTG0 are general-purpose, bidirectional I/O port pins that can also be used
for analog-to-digital converter (ADC) inputs. PTG7–PTG0 are only available on the
64-pin QFP package. See Section 13. Input/Output (I/O) Ports and Section 3.
Analog-to-Digital Converter (ADC).
or VSS). Although the I/O ports do not require termination, termination is
V
DD
recommended to reduce the possibility of static damage.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA General Description 31
For More Information On This Product,
Go to: www.freescale.com
Page 32
General Description
nc...
I
Freescale Semiconductor, Inc.
cale Semiconductor,
Frees
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
32 General Description MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 33
Freescale Semiconductor, Inc.
Data Sheet — MC68HC908GZ60
2.1 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory map, shown in
Figure 2-1, includes:
• 62,078 bytes of user FLASH memory
• 2048 bytes of random-access memory (RAM)
• 52 bytes of user-defined vectors
nc...
I
2.2 Unimplemented Memory Locations
Section 2. Memory
Accessing an unimplemented location can cause an illegal address reset. In the
memory map (Figure 2-1) and in register figures in this document, unimplemented
locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on microcontroller
(MCU) operation. In the Figure 2-1 and in register figures in this document,
reserved locations are marked with the word Reserved or with the letter R.
cale Semiconductor,
Frees
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 33
For More Information On This Product,
Go to: www.freescale.com
Page 34
Memory
Freescale Semiconductor, Inc.
$0000
↓
$003F
$0040
↓
$043F
$0440
↓
$0461
$0462
↓
$04FF
nc...
I
cale Semiconductor,
$0500
↓
$057F
$0580
↓
$097F
$0980
↓
$1B7F
$1B80
↓
$1DFF
$1E00
↓
$1E0F
$1E10
↓
$1E1F
MSCAN CONTROL AND MESSAGE BUFFER
I/O REGISTERS
64 BYTES
RAM-1
1024 BYTES
I/O REGISTERS
34 BYTES
FLASH-2
158 BYTES
128 BYTES
RAM-2
1024 BYTES
FLASH-2
4608 BYTES $FE20
RESERVED
640 BYTES
MONITOR ROM
16 BYTES
RESERVED
16 BYTES
$FE00 SIM BREAK STATUS REGISTER (BSR)
$FE01 SIM RESET STATUS REGISTER (SRSR)
$FE02 RESERVED
$FE03 SIM BREAK FLAG CONTROL REGISTER (BFCR)
$FE04 INTERRUPT STATUS REGISTER 1 (INT1)
$FE05 INTERRUPT STATUS REGISTER 2 (INT2)
$FE06 INTERRUPT STATUS REGISTER 3 (INT3)
$FE07 INTERRUPT STATUS REGISTER 4 (INT4)
$FE08 FLASH-2 CONTROL REGISTER (FL2CR)
$FE09 BREAK ADDRESS REGISTER HIGH (BRKH)
$FE0A BREAK ADDRESS REGISTER LOW (BRKL)
$FE0B BREAK STATUS AND CONTROL REGISTER (BRKSCR)
$FE0C LVI STATUS REGISTER (LVISR)
$FE0D FLASH-2 TEST CONTROL REGISTER (FLTCR2)
$FE0E FLASH-1 TEST CONTROL REGISTER (FLTCR1)
$FE0F
$FE10
↓
$FE1F
$FF7F
$FF80 FLASH-1 BLOCK PROTECT REGISTER (FL1BPR)
$FF81 FLASH-2 BLOCK PROTECT REGISTER (FL2BPR)
$FF82
$FF87
$FF88 FLASH-1 CONTROL REGISTER (FL1CR)
RESERVED FOR COMPATIBILITY WITH MONITOR CODE
↓
↓
UNIMPLEMENTED
UNIMPLEMENTED
16 BYTES
FOR A-FAMILY PART
MONITOR ROM
352 BYTES
RESERVED
6 BYTES
Frees
$1E20
↓
$7FFF
$8000
↓
$FDFF
FLASH-2
25,056 BYTES
FLASH-1
32,256 BYTES
$FF89
↓
$FFCB
$FFCC
↓
$FFFF
RESERVED
67 BYTES
FLASH-1 VECTORS
(1)
1. $FFF6–$FFFD used for eight security bytes
52 BYTES
Figure 2-1. MC68HC908GZ60 Memory Map
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
34 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 35
Freescale Semiconductor, Inc.
2.4 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page area of
$0000–$003F, or at $0440–$0461. Additional I/O registers have these addresses:
• $FE00; SIM break status register, BSR
• $FE01; SIM reset status register, SRSR
• $FE02; reserved
• $FE03; SIM break flag control register, BFCR
• $FE04; interrupt status register 1, INT1
• $FE05; interrupt status register 2, INT2
• $FE06; interrupt status register 3, INT3
Memory
Input/Output (I/O) Section
nc...
I
cale Semiconductor,
Frees
• $FE07; interrupt status register 4, INT4
• $FE08; FLASH-2 control register, FL2CR
• $FE09; break address register high, BRKH
• $FE0A; break address register low, BRKL
• $FE0B; break status and control register, BRKSCR
• $FE0C; LVI status register, LVISR
• $FE0D; FLASH-2 test control register, FLTCR2
• $FE0E; FLASH-1 test control register, FLTCR1
• $FF80; FLASH-1 block protect register, FL1BPR
• $FF81; FLASH-2 block protect register, FL2BPR
• $FF88; FLASH-1 control register, FL1CR
Data registers are shown in Figure 2-2. Table 2-1 is a list of vector locations.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 35
For More Information On This Product,
Go to: www.freescale.com
Page 36
Freescale Semiconductor, Inc.
Memory
Addr.Register Name Bit 7654321Bit 0
nc...
I
cale Semiconductor,
Frees
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
Port A Data Register
(PTA)
See page 187.
Port B Data Register
(PTB)
See page 190.
Port C Data Register
(PTC)
See page 192.
Port D Data Register
(PTD)
See page 194.
Data Direction Register A
(DDRA)
See page 188.
Data Direction Register B
(DDRB)
See page 190.
Data Direction Register C
(DDRC)
See page 192.
Data Direction Register D
(DDRD)
See page 196.
Port E Data Register
(PTE)
See page 198.
ESCI Prescaler Register
(SCPSC)
See page 234.
Read:
PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
Write:
Reset: Unaffected by reset
Read:
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
Reset: Unaffected by reset
Read: 1
PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
Write:
Reset: Unaffected by reset
Read:
PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
Write:
Reset: Unaffected by reset
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:00000000
Read:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset:00000000
Read: 0
DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write:
Reset:00000000
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Write:
Reset:00000000
Read: 0 0
PTE5 PTE4 PTE3 PTE2 PTE1 PTE0
Write:
Reset: Unaffected by reset
Read:
PDS2 PDS1 PDS0 PSSB4 PSSB3 PSSB2 PSSB1 PSSB0
Write:
Reset:00000000
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 10)
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
36 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 37
Freescale Semiconductor, Inc.
Addr.Register Name Bit 7654321Bit 0
Read:
Write:
Reset:00000000
$000A
ESCI Arbiter Control
Register (SCIACTL)
See page 237.
AM1
ALOST
Memory
Input/Output (I/O) Section
AFIN ARUN AROVFL ARD8
AM0 ACLK
nc...
I
cale Semiconductor,
Frees
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
ESCI Arbiter Data
Register (SCIADAT)
See page 238.
Data Direction Register E
(DDRE)
See page 199.
Port A Input Pullup Enable
Register (PTAPUE)
See page 189.
Port C Input Pullup Enable
Register (PTCPUE)
See page 194.
Port D Input Pullup Enable
Register (PTDPUE)
See page 197.
SPI Control Register
(SPCR)
See page 279.
SPI Status and Control
Register (SPSCR)
See page 281.
SPI Data Register
(SPDR)
See page 283.
Read: ARD7 ARD6 ARD5 ARD4 ARD3 ARD2 ARD1 ARD0
Write:
Reset:00000000
Read: 0 0
Write:
Reset:00000000
Read:
PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset:00000000
Read: 0
PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0
Write:
Reset:00000000
Read:
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
Write:
Reset:00000000
Read:
SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE
Write:
Reset:00101000
Read: SPRF
ERRIE
Write:
Reset:00001000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
OVRF MODF SPTE
MODFEN SPR1 SPR0
Read:
LOOPS ENSCI TXINV M WAKE ILTY PEN PTY
Write:
Reset:00000000
= Unimplemented R = Reserved U = Unaffected
$0013
ESCI Control Register 1
(SCC1)
See page 223.
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 10)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 37
For More Information On This Product,
Go to: www.freescale.com
Page 38
Freescale Semiconductor, Inc.
Memory
Addr.Register Name Bit 7654321Bit 0
Read:
SCTIE TCIE SCRIE ILIE TE RE RWU SBK
Write:
Reset:00000000
$0014
ESCI Control Register 2
(SCC2)
See page 225.
nc...
I
cale Semiconductor,
Frees
ESCI Control Register 3
$0015
ESCI Status Register 1
$0016
ESCI Status Register 2
$0017
$0018
ESCI Baud Rate Register
$0019
Keyboard Status and Control
$001A
$001B
$001C
Register (INTKBSCR)
Keyboard Interrupt Enable
Register (INTKBIER)
Timebase Module Control
(SCC3)
See page 227.
(SCS1)
See page 228.
(SCS2)
See page 231.
ESCI Data Register
(SCDR)
See page 231.
(SCBR)
See page 232.
See page 130.
See page 131.
Register (TBCR)
See page 288.
Read: R8
Write:
Reset:U0000000
Read: SCTE TC SCRF IDLE OR NF FE PE
Write:
Reset:11000000
Read: 000000BKFRPF
Write:
Reset:00000000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
Read:
LINT LINR SCP1 SCP0 R SCR2 SCR1 SCR0
Write:
Reset:00000000
Read: 0000KEYF 0
Write:
Reset:00000000
Read:
KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
Write:
Reset:00000000
Read: TBIF
Write:
Reset:00000000
T8 R R ORIE NEIE FEIE PEIE
IMASKK MODEK
TBR2 TBR1 TBR0
ACKK
0
TBIE TBON R
TACK
Read: 0000IRQF0
Write:
Reset:00000000
= Unimplemented R = Reserved U = Unaffected
ACK
IMASK MODE
$001D
IRQ Status and Control
Register (INTSCR)
See page 124.
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 10)
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
38 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 39
Freescale Semiconductor, Inc.
Addr.Register Name Bit 7654321Bit 0
Read: 0
(1)
Write:
Reset:00000001
$001E
Configuration Register 2
(CONFIG2)
See page 100.
MCLKSEL MCLK1 MCLK0
MSCAN-
(1)
EN
Memory
Input/Output (I/O) Section
TBMCLK-
SEL
OSCENIN-
STOP
SCIBDSRC
nc...
I
cale Semiconductor,
Frees
Configuration Register 1
$001F
1. One-time writable register after each reset, except MSCANEN and LVI5OR3 bits. MSCANEN andLVI5OR3 bits are only
reset via POR (power-on reset).
TIM1 Status and Control
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
Register High (T1CNTH)
Register Low (T1CNTL)
Register High (T1MODH)
Register Low (T1MODL)
TIM1 Channel 0 Status and
Control Register (T1SC0)
Register High (T1CH0H)
Register Low (T1CH0L)
(CONFIG1)
See page 101.
Register (T1SC)
See page 301.
TIM1 Counter
See page 302.
TIM1 Counter
See page 302.
TIM1 Counter Modulo
See page 303.
TIM1 Counter Modulo
See page 303.
See page 304.
TIM1 Channel 0
See page 307.
TIM1 Channel 0
See page 307.
Read:
(1)
Write:
Reset:00000000
Read: TOF
Write: 0 TRST
Reset:00100000
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Read: Bit 7 654321Bit 0
Write:
Reset:00000000
Read:
Write:
Reset:11111111
Read:
Write:
Reset:11111111
Read: CH0F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3
00
TOIE TSTOP
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
(1)
SSREC STOP COPD
PS2 PS1 PS0
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 10)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 39
For More Information On This Product,
Go to: www.freescale.com
Page 40
Freescale Semiconductor, Inc.
Memory
Addr.Register Name Bit 7654321Bit 0
TIM1 Channel 1 Status and
$0028
Control Register (T1SC1)
See page 304.
Read: CH1F
CH1IE
Write: 0
Reset:00000000
0
MS1A ELS1B ELS1A TOV1 CH1MAX
nc...
I
cale Semiconductor,
Frees
$0029
$002A
$002B
$002C
$002D
$002E
$002F
$0030
TIM1 Channel 1
Register High (T1CH1H)
See page 307.
TIM1 Channel 1
Register Low (T1CH1L)
See page 307.
TIM2 Status and Control
Register (T2SC)
See page 323.
TIM2 Counter
Register High (T2CNTH)
See page 325.
TIM2 Counter
Register Low (T2CNTL)
See page 325.
TIM2 Counter Modulo
Register High (T2MODH)
See page 325.
TIM2 Counter Modulo
Register Low (T2MODL)
See page 325.
TIM2 Channel 0 Status and
Control Register (T2SC0)
See page 326.
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: TOF
Write: 0 TRST
Reset:00100000
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Read: Bit 7 654321Bit 0
Write:
Reset:00000000
Read:
Write:
Reset:11111111
Read:
Write:
Reset:11111111
Read: CH0F
Write: 0
Reset:00000000
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
TOIE TSTOP
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
00
PS2 PS1 PS0
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
= Unimplemented R = Reserved U = Unaffected
$0031
TIM2 Channel 0
Register High (T2CH0H)
See page 330.
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 10)
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
40 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 41
Freescale Semiconductor, Inc.
Addr.Register Name Bit 7654321Bit 0
Read:
Write:
Reset: Indeterminate after reset
$0032
TIM2 Channel 0
Register Low (T2CH0L)
See page 330.
Memory
Input/Output (I/O) Section
Bit 7654321Bit 0
nc...
I
cale Semiconductor,
Frees
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
TIM2 Channel 1 Status and
Control Register (T2SC1)
See page 326.
TIM2 Channel 1
Register High (T2CH1H)
See page 330.
TIM2 Channel 1
Register Low (T2CH1L)
See page 330.
PLL Control Register
(PCTL)
See page 90.
PLL Bandwidth Control
Register (PBWC)
See page 92.
PLL Multiplier Select High
Register (PMSH)
See page 93.
PLL Multiplier Select Low
Register (PMSL)
See page 94.
PLL VCO Select Range
Register (PMRS)
See page 94.
Read: CH1F
Write: 0
Reset:00000000
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
Read:
PLLIE
Write:
Reset:00100000
Read:
AUTO
Write:
Reset:00000000
Read: 0000
Write:
Reset:00000000
Read:
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Write:
Reset:01000000
Read:
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Write:
Reset:01000000
CH1IE
PLLF
LOCK
0
PLLON BCS R R VPR1 VPR0
ACQ
MS1A ELS1B ELS1A TOV1 CH1MAX
0000
R
MUL11 MUL10 MUL9 MUL8
$003B Reserved
Read: 0000
Write:
Reset:00000001
= Unimplemented R = Reserved U = Unaffected
RRRR
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 10)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 41
For More Information On This Product,
Go to: www.freescale.com
Page 42
Freescale Semiconductor, Inc.
Memory
Addr.Register Name Bit 7654321Bit 0
Read: COCO
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write: R
Reset:00011111
$003C
ADC Status and Control
Register (ADSCR)
See page 72.
nc...
I
cale Semiconductor,
Frees
$003D
$003E
$003F
$0440
$0441
$0444
$0445
$0448
ADC Data High Register
(ADRH)
See page 74.
ADC Data Low Register
(ADRL)
See page 74.
ADC Clock Register
(ADCLK)
See page 76.
Port F Data Register
(PTF)
See page 200.
Port G Data Register
(PTG)
See page 202.
Data Direction Register F
(DDRF)
See page 200.
Data Direction Register G
(DDRG)
See page 202.
Keyboard Interrupt
Polarity Register
(INTKBIPR)
See page 132.
Read: 000000AD9AD8
Write:
Reset: Unaffected by reset
Read: AD7 AD6 AD5 AD4 A3 AD2 AD1 AD0
Write:
Reset: Unaffected by reset
Read:
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 R
Write:
Reset:00000100
Read:
PTF7 PTF6 PTF5 PTF4 PTAF3 PTF2 PTF1 PTF0
Write:
Reset: Unaffected by reset
Read:
PTG7 PTG6 PTG5 PTG4 PTG3 PTG2 PTG1 PTG0
Write:
Reset: Unaffected by reset
Read:
DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
Write:
Reset:00000000
Read:
DDRG7 DDRG6 DDRG5 DDRG4 DDRG3 DDRG2 DDRG1 DDRG0
Write:
Reset:00000000
Read:
KBIP7 KBIP6 KBIP5 KBIP4 KBIP3 KBIP2 KBIP1 KBIP0
Write:
Reset:00000000
0
TIM2 Channel 2 Status and
$0456
Control Register (T2SC2)
See page 330.
Read: CH2F
CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX
Write: 0
Reset:00000000
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 10)
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
42 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 43
Freescale Semiconductor, Inc.
Addr.Register Name Bit 7654321Bit 0
Read:
Write:
Reset: Indeterminate after reset
$0457
TIM2 Channel 2
Register High (T2CH2H)
See page 330.
Memory
Input/Output (I/O) Section
Bit 15 14 13 12 11 10 9 Bit 8
nc...
I
cale Semiconductor,
Frees
$0458
$0459
$045A
$045B
$045C
$045D
$045E
$045F
TIM2 Channel 2
Register Low (T2CH2L)
See page 330.
TIM2 Channel 3 Status and
Control Register (T2SC3)
See page 326.
TIM2 Channel 3
Register High (T2CH3H)
See page 330.
TIM2 Channel 3
Register Low (T2CH3L)
See page 330.
TIM2 Channel 4 Status and
Control Register (T2SC4)
See page 326.
TIM2 Channel 4
Register High (T2CH4H)
See page 330.
TIM2 Channel 4
Register Low (T2CH4L)
See page 330.
TIM2 Channel 5 Status and
Control Register (T2SC5)
See page 326.
Read:
Write:
Reset: Indeterminate after reset
Read: CH3F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: CH4F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: CH5F
Write: 0
Reset:00000000
Bit 7654321Bit 0
CH3IE
Bit 15 14 13 12 11 10 9 Bit 8
Bit 765432 1Bit 0
CH4IE MS4B MS4A ELS4B ELS4A TOV4 CH4MAX
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321 Bit 0
CH5IE
0
MS3A ELS3B ELS3A TOV3 CH3MAX
0
MS5A ELS5B ELS5A TOV 5 CH5MAX
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
= Unimplemented R = Reserved U = Unaffected
$0460
TIM2 Channel 5
Register High (T2CH5H)
See page 330.
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 10)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 43
For More Information On This Product,
Go to: www.freescale.com
Page 44
Freescale Semiconductor, Inc.
Memory
Addr.Register Name Bit 7654321Bit 0
Read:
Bit 7654321 Bit 0
Write:
Reset: Indeterminate after reset
$0461
TIM2 Channel 5
Register Low (T2CH5L)
See page 330.
Break Status Register
$FE00
See page 258.
1. Writing a 0 clears SBSW.
SIM Reset Status Register
$FE01
nc...
I
$FE02 Reserved
Break Flag Control Register
$FE03
Interrupt Status Register 1
$FE04
Interrupt Status Register 2
$FE05
(SRSR)
See page 259.
(BFCR)
See page 260.
See page 254.
See page 254.
cale Semiconductor,
Interrupt Status Register 3
$FE06
See page 254.
Read:
(BSR)
Write: NOTE 1
Reset:00000000
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR:10000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
(INT1)
Write:RRRRRRRR
Reset:00000000
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
(INT2)
Write:RRRRRRRR
Reset:00000000
Read: IF22 IF21 IF20 IF19 IF18 IF17 IF16 IF15
(INT3)
Write:RRRRRRRR
Reset:00000000
RRRRRR
RRRRRRRR
BCFERRRRRRR
SBSW
R
Frees
$FE07
$FE08
Interrupt Status Register 4
See page 255.
FLASH-2 Control Register
(FL2CR)
See page 57.
Read: 000000IF24IF23
(INT4)
Write:RRRRRRRR
Reset:00000000
Read: 0000
Write:
Reset:00000000
= Unimplemented R = Reserved U = Unaffected
HVEN MASS ERASE PGM
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 10)
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
44 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 45
Freescale Semiconductor, Inc.
Addr.Register Name Bit 7654321Bit 0
Break Address Register High
$FE09
(BRKH)
See page 338.
Read:
Write:
Reset:00000000
Memory
Input/Output (I/O) Section
Bit 15 14 13 12 11 10 9 Bit 8
nc...
I
cale Semiconductor,
Frees
Break Address Register Low
$FE0A
Break Status and Control
$FE0B
$FE0C
$FE0D
$FE0E
$FF80
$FF81
1. Non-volatile FLASH register
$FF88
Register (BRKSCR)
LVI Status Register
FLASH-2 Test Control
Register (FLTCR2)
FLASH-1 Test Control
Register (FLTCR1)
FLASH-1 Block Protect
Register (FL1BPR)
FLASH-2 Block Protect
Register (FL2BPR)
FLASH-1 Control Register
(BRKL)
See page 338.
See page 337.
(LVISR)
See page 143.
See page 50.
See page 58.
(FL1CR)
See page 49.
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: LVIOUT 0000000
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
(1)
Write:
Reset: Unaffected by reset
Read:
(1)
Write:
Reset: Unaffected by reset
Read: 0000
Write:
Reset:00000000
Bit 7654321Bit 0
000000
BRKE BRKA
RRRRRRRR
RRRRRRRR
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
HVEN MASS ERASE PGM
Read: Low byte of reset vector
Write: Writing clears COP counter (any value)
Reset: Unaffected by reset
= Unimplemented R = Reserved U = Unaffected
$FFFF
COP Control Register
(COPCTL)
See page 105.
Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 10)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 45
For More Information On This Product,
Go to: www.freescale.com
Page 46
Memory
Freescale Semiconductor, Inc.
nc...
I
cale Semiconductor,
Frees
Table 2-1. Vector Addresses
Vector Priority Vector Address Vector
Lowest
IF24
IF23
IF22
IF21
IF20
IF19
IF18
IF17
IF16
IF15
IF14
IF13
IF12
IF11
IF10
IF9
IF8
$FFCC TIM2 Channel 5 Vector (High)
$FFCD TIM2 Channel 5 Vector (Low)
$FFCE TIM2 Channel 4 Vector (High)
$FFCF TIM2 Channel 4 Vector (Low)
$FFD0 TIM2 Channel 3 Vector (High)
$FFD1 TIM2 Channel 3 Vector (Low)
$FFD2 TIM2 Channel 2 Vector (High)
$FFD3 TIM2 Channel 2 Vector (Low)
$FFD4 MSCAN08 Transmit Vector (High)
$FFD5 MSCAN08 Transmit Vector (Low)
$FFD6 MSCAN08 Receive Vector (High)
$FFD7 MSCAN08 Receive Vector (Low)
$FFD8 MSCAN08 Error Vector (High)
$FFD9 MSCAN08 Error Vector (Low)
$FFDA MSCAN08 Wakeup Vector (High)
$FFDB MSCAN08 Wakeup Vector (Low)
$FFDC Timebase Vector (High)
$FFDD Timebase Vector (Low)
$FFDE ADC Conversion Complete Vector (High)
$FFDF ADC Conversion Complete Vector (Low)
$FFE0 Keyboard Vector (High)
$FFE1 Keyboard Vector (Low)
$FFE2 ESCI Transmit Vector (High)
$FFE3 ESCI Transmit Vector (Low)
$FFE4 ESCI Receive Vector (High)
$FFE5 ESCI Receive Vector (Low)
$FFE6 ESCI Error Vector (High)
$FFE7 ESCI Error Vector (Low)
$FFE8 SPI Transmit Vector (High)
$FFE9 SPI Transmit Vector (Low)
$FFEA SPI Receive Vector (High)
$FFEB SPI Receive Vector (Low)
$FFEC TIM2 Overflow Vector (High)
$FFED TIM2 Overflow Vector (Low)
.
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
46 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 47
Vector Priority Vector Address Vector
nc...
I
Highest $FFFF Reset Vector (Low)
2.5 Random-Access Memory (RAM)
The RAM locations are broken into two non-continuous memory blocks. The RAM
cale Semiconductor,
NOTE: For correct operation, the stack pointer must point only to RAM locations.
addresses locations are $0040–$043F and $0580–$097F. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to be
anywhere in the 64-Kbyte memory space.
Freescale Semiconductor, Inc.
Random-Access Memory (RAM)
Table 2-1. Vector Addresses (Continued)
IF7
IF6
IF5
IF4
IF3
IF2
IF1
—
—
$FFEE TIM2 Channel 1 Vector (High)
$FFEF TIM2 Channel 1 Vector (Low)
$FFF0 TIM2 Channel 0 Vector (High)
$FFF1 TIM2 Channel 0 Vector (Low)
$FFF2 TIM1 Overflow Vector (High)
$FFF3 TIM1 Overflow Vector (Low)
$FFF4 TIM1 Channel 1 Vector (High)
$FFF5 TIM1 Channel 1 Vector (Low)
$FFF6 TIM1 Channel 0 Vector (High)
$FFF7 TIM1 Channel 0 Vector (Low)
$FFF8 PLL Vector (High)
$FFF9 PLL Vector (Low)
$FFFA IRQ
$FFFB IRQ Vector (Low)
$FFFC SWI Vector (High)
$FFFD SWI Vector (Low)
$FFFE Reset Vector (High)
Vector (High)
Memory
Frees
NOTE: For M6805 compatibility, the H register is not stacked.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 47
Within page zero are 192 bytes of RAM. Because the location of the stack RAM is
programmable, all page zero RAM locations can be used for I/O control and user
data or code. When the stack pointer is moved from its reset location at $00FF out
of page zero, direct addressing mode instructions can efficiently access all page
zero RAM locations. Page zero RAM, therefore, provides ideal locations for
frequently accessed global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to save the
contents of the CPU registers.
For More Information On This Product,
Go to: www.freescale.com
Page 48
Freescale Semiconductor, Inc.
Memory
During a subroutine call, the CPU uses two bytes of the stack to store the return
address. The stack pointer decrements during pushes and increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the
RAM during a subroutine or during the interrupt stacking operation.
2.6 FLASH-1 Memory (FLASH-1)
This subsection describes the operation of the embedded FLASH-1 memory. This
memory can be read, programmed, and erased from a single external supply. The
program and erase operations are enabled through the use of an internal charge
pump.
2.6.1 Functional Description
nc...
I
cale Semiconductor,
Frees
The FLASH-1 memory is an array of 32,256 bytes with two bytes of block protection
(one byte for protecting areas within FLASH-1 array and one byte for protecting
areas within FLASH-2 array) and an additional 52 bytes of user vectors. An erased
bit reads as a 1 and a programmed bit reads as a 0.
Memory in the FLASH-1 array is organized into rows within pages. There are two
rows of memory per page with 64 bytes per row. The minimum erase block size is
a single page,128 bytes. Programming is performed on a per-row basis, 64 bytes
at a time. Program and erase operations are facilitated through control bits in the
FLASH-1 control register (FL1CR). Details for these operations appear later in this
subsection.
The FLASH-1 memory map consists of:
• $8000–$FDFF: user memory (32,256 bytes)
• $FF80: FLASH-1 block protect register (FL1BPR)
• $FF81: FLASH-2 block protect register (FL2BPR)
• $FF88: FLASH-1 control register (FL1CR)
• $FFCC–$FFFF: these locations are reserved for user-defined interrupt and
reset vectors (see Table 2-1 for details)
Programming tools are available from Motorola. Contact your local Motorola
representative for more information.
NOTE: A security feature prevents viewing of the FLASH contents.
(1)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
48 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 49
Freescale Semiconductor, Inc.
2.6.2 FLASH-1 Control and Block Protect Registers
The FLASH-1 array has two registers that control its operation, the FLASH-1
control register (FL1CR) and the FLASH-1 block protect register (FL1BPR).
2.6.2.1 FLASH-1 Control Register
The FLASH-1 control register (FL1CR) controls FLASH program and erase
operations.
Address: $FF88
Read:0000
Write:
nc...
I
Reset:00000000
Bit 7654321Bit 0
= Unimplemented
Memory
FLASH-1 Memory (FLASH-1)
HVEN MASS ERASE PGM
cale Semiconductor,
Frees
Figure 2-3. FLASH-1 Control Register (FL1CR)
HVEN — High-Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for program
and erase operations in the array. HVEN can only be set if either PGM = 1 or
ERASE = 1 and the proper sequence for program or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
Setting this read/write bit configures the FLASH-1 array for mass erase
operation.
1 = MASS erase operation selected
0 = MASS erase operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is
interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1
at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is
interlocked with the ERASE bit such that both bits cannot be equal to 1 or set
to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 49
For More Information On This Product,
Go to: www.freescale.com
Page 50
Freescale Semiconductor, Inc.
Memory
2.6.2.2 FLASH-1 Block Protect Register
The FLASH-1 block protect register (FL1BPR) is implemented as a byte within the
FLASH-1 memory; therefore, it can only be written during a FLASH programming
sequence. The value in this register determines the starting location of the
protected range within the FLASH-1 memory.
Address: $FF80
Bit 7654321Bit 0
Read:
Write:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Figure 2-4. FLASH-1 Block Protect Register (FL1BPR)
Unaffected by reset
nc...
I
cale Semiconductor,
Frees
FL1BPR[7:0] — Block Protect Register Bits 7 to 0
These eight bits represent bits [14:7] of a 16-bit memory address. Bit 15 is a 1
and bits [6:0] are 0s.
The resultant 16-bit address is used for specifying the start address of the
FLASH-1 memory for block protection. FLASH-1 is protected from this start
address to the end of FLASH-1 memory at $FFFF. With this mechanism, the
protect start address can be $XX00 and $XX80 (128 byte page boundaries)
within the FLASH-1 array.
16-BIT MEMORY ADDRESS
START ADDRESS OF FLASH
BLOCK PROTECT
Figure 2-5. FLASH-1 Block Protect Start Address
Table 2-2. FLASH-1 Protected Ranges
FL1BPR[7:0] Protected Range
$FF No protection
$FE $FF00–$FFFF
$FD
↓
$0B
$0A $8500–$FFFF
$09 $8480–$FFFF
$08
↓
$04
$03 $8180–$FFFF
$02 $8100–$FFFF
$01 $8080–$FFFF
$00 $8000–$FFFF
1
FLBPR VALUE
$FE80–$FFFF
0000000
↓
$8580–$FFFF
$8400–$FFFF
↓
$8200–$FFFF
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
50 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 51
2.6.3 FLASH-1 Block Protection
nc...
I
Freescale Semiconductor, Inc.
Decreasing the value in FL1BPR by one increases the protected range by one
page (128 bytes). However, programming the block protect register with $FE
protects a range twice that size, 256 bytes, in the corresponding array. $FE means
that locations $FF00–$FFFF are protected in FLASH-1.
The FLASH memory does not exist at some locations. The block protection range
configuration is unaffected if FLASH memory does not exist in that range. Refer to
Figure 2-1 and make sure that the desired locations are protected.
Due to the ability of the on-board charge pump to erase and program the FLASH
memory in the target application, provision is made for protecting blocks of memory
from unintentional erase or program operations due to system malfunction. This
protection is done by using the FLASH-1 block protection register (FL1BPR).
FL1BPR determines the range of the FLASH-1 memory which is to be protected.
The range of the protected area starts from a location defined by FL1BPR and ends
at the bottom of the FLASH-1 memory ($FFFF). When the memory is protected,
the HVEN bit can not be set in either ERASE or PROGRAM operations.
Memory
FLASH-1 Memory (FLASH-1)
cale Semiconductor,
Frees
NOTE: In performing a program or erase operation, the FLASH-1 block protect register
must be read after setting the PGM or ERASE bit and before asserting the
HVEN bit.
When the FLASH-1 block protect register is programmed with all 0’s, the entire
memory is protected from being programmed and erased. When all the bits are
erased (all 1’s), the entire memory is accessible for program and erase.
When bits within FL1BPR are programmed (0), they lock a block of memory
address ranges as shown in Figure 2-4. If FL1BPR is programmed with any value
other than $FF, the protected block of FLASH memory can not be erased or
programmed.
NOTE: The vector locations and the FLASH block protect registers are located in the same
page. FL1BPR and FL2BPR are not protected with special hardware or software.
Therefore, if this page is not protected by FL1BPR and the vector locations are
erased by either a page or a mass erase operation, then both FL1BPR and
FL2BPR will also get erased.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 51
For More Information On This Product,
Go to: www.freescale.com
Page 52
Memory
2.6.4 FLASH-1 Mass Erase Operation
Use this step-by-step procedure to erase the entire FLASH-1 memory:
1. Set both the ERASE bit and the MASS bit in the FLASH-1 control register
2. Read the FLASH-1 block protect register (FL1BPR).
NOTE: Mass erase is disabled whenever any block is protected (FL1BPR does not equal
$FF).
3. Write to any FLASH-1 address within the FLASH-1 array with any data.
4. Wait for a time, t
5. Set the HVEN bit.
6. Wait for a time, t
nc...
I
7. Clear the ERASE and MASS bits.
8. Wait for a time, t
9. Clear the HVEN bit.
10. Wait for a time, t
Freescale Semiconductor, Inc.
(FL1CR).
accessed in normal read mode.
(minimum 10 µs).
NVS
MERASE
NVHL
RCV
(minimum 4 ms).
(minimum 100 µs).
, (typically 1 µs) after which the memory can be
NOTES: A. Programming and erasing of FLASH locations can not be performed by code
being executed from the same FLASH array.
B. While the se operations must be performed in the order shown, other unrelated
operations may occur between the steps. However, care must be taken to
ensure that these operations do not access any address within the FLASH
array memory space such as the COP control register (COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during program/erase
operations.
cale Semiconductor,
2.6.5 FLASH-1 Page Erase Operation
Use this step-by-step procedure to erase a page (128 bytes) of FLASH-1 memory:
Frees
1. Set the ERASE bit and clear the MASS bit in the FLASH-1 control register
2. Read the FLASH-1 block protect register (FL1BPR).
3. Write any data to any FLASH-1 address within the address range of the
4. Wait for time, t
5. Set the HVEN bit.
6. Wait for time, t
7. Clear the ERASE bit.
8. Wait for time, t
(FL1CR).
page (128 byte block) to be erased.
(minimum 10 µs).
NVS
(minimum 1 ms or 4 ms).
ERASE
(minimum 5 µs).
NVH
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
52 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 53
Freescale Semiconductor, Inc.
9. Clear the HVEN bit.
10. Wait for a time, t
accessed in normal read mode.
NOTES: A. Programming and erasing of FLASH locations can not be performed by code
being executed from the same FLASH array.
B. While the se operations must be performed in the order shown, other unrelated
operations may occur between the steps. However, care must be taken to
ensure that these operations do not access any address within the FLASH
array memory space such as the COP control register (COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during program/erase
operations.
FLASH-1 Memory (FLASH-1)
, (typically 1 µs) after which the memory can be
RCV
Memory
nc...
I
2.6.6 FLASH-1 Program Operation
cale Semiconductor,
Frees
NOTE: Only bytes which are currently $FF may be programmed.
In applications that require more than 1000 program/erase cycles, use the 4 ms
page erase specification to get improved long-term reliability. Any application can
use this 4 ms page erase specification. However, in applications where a FLASH
location will be erased and reprogrammed less than 1000 times, and speed is
important, use the 1 ms page erase specification to get a shorter cycle time.
Programming of the FLASH-1 memory is done on a row basis. A row consists of
64 consecutive bytes with address ranges as follows:
During the programming cycle, make sure that all addresses being written to fit
within one of the ranges specified above. Attempts to program addresses in
different row ranges in one programming cycle will fail.
Use this step-by-step procedure to program a row of FLASH-1 memory.
• $XX00 to $XX3F
• $XX40 to $XX7F
• $XX80 to $XXBF
• $XXC0 to $XXFF
1. Set the PGM bit in the FLASH-1 control register (FL1CR). This configures
the memory for program operation and enables the latching of address and
data programming.
2. Read the FLASH-1 block protect register (FL1BPR).
3. Write to any FLASH-1 address within the row address range desired with
any data.
4. Wait for time, t
5. Set the HVEN bit.
6. Wait for time, t
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 53
For More Information On This Product,
Go to: www.freescale.com
(minimum 10 µs).
NVS
(minimum 5 µs).
PGS
Page 54
Memory
Freescale Semiconductor, Inc.
7. Write data byte to the FLASH-1 address to be programmed.
8. Wait for time, t
9. Repeat steps 7 and 8 until all the bytes within the row are programmed.
10. Clear the PGM bit.
11. Wait for time, t
12. Clear the HVEN bit.
13. Wait for a time, t
accessed in normal read mode.
The FLASH programming algorithm flowchart is shown in Figure 2-6.
NOTES: A. Programming and erasing of FLASH locations can not be performed by code
being executed from the same FLASH array.
(minimum 30 µs).
PROG
(minimum 5 µs)
NVH
, (typically 1 µs) after which the memory can be
RCV
nc...
I
cale Semiconductor,
Frees
B. While the se operations must be performed in the order shown, other unrelated
operations may occur between the steps. However, care must be taken to
ensure that these operations do not access any address within the FLASH
array memory space such as the COP control register (COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during program/erase
operations.
D. Do not exceed t
cumulative high voltage programming time to the same row before next erase.
t
must satisfy this condition:
HV
t
+ t
NVS
E. The time between each FLASH address change (step 7 to step 7), or the time
between the last FLASH address programmed to clearing the PGM bit (step 7
to step 10) must not exceed the maximum programming time, t
F. Be cautious when programming the FLASH-1 array to ensure that non-FLASH
locations are not used as the address that is written to when selecting either the
desired row address range in step 3 of the algorithm or the byte to be
programmed in step 7 of the algorithm.
NVH
+ t
maximum or t
PROG
+ (t
PGS
PROG
X
HV
64) ≤ t
maximum. t
maximum
HV
is defined as the
HV
PROG
maximum.
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
54 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 55
Freescale Semiconductor, Inc.
Memory
FLASH-1 Memory (FLASH-1)
nc...
I
cale Semiconductor,
Frees
Algorithm for programming
a row (64 bytes) of FLASH memory
1
2
3
WRITE ANY DATA TO ANY FLASH
4
5
6
7
ADDRESS TO BE PROGRAMMED
8
SET PGM BIT
READ THE FLASH BLOCK
PROTECT REGISTER
ADDRESS WITHIN THE ROW
ADDRESS RANGE DESIRED
WAIT FOR A TIME, t
SET HVEN BIT
WAIT FOR A TIME, t
WRITE DATA TO THE FLASH
WAIT FOR A TIME, t
COMPLETED
PROGRAMMING
THIS ROW?
NO
NVS
PGS
PROG
10
11
YES
CLEAR PGM BIT
WAIT FOR A TIME, t
NVH
NOTES:
The time between each FLASH address change (step 7 to step 7) or
the time between the last FLASH address programmed to clearing
PGM bit (step 7 to step10) must not exceed the maximum
programming time, t
This row program algorithm assumes the row/s to be
programmed are initially erased.
PROG
, maximum.
12
13
CLEAR HVEN BIT
WAIT FOR A TIME, t
END OF PROGRAMMING
RCV
Figure 2-6. FLASH-1 Programming Algorithm Flowchart
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 55
For More Information On This Product,
Go to: www.freescale.com
Page 56
Memory
2.6.7 Low-Power Modes
2.6.7.1 Wait Mode
nc...
2.6.7.2 Stop Mode
I
Freescale Semiconductor, Inc.
The WAIT and STOP instructions will place the MCU in low power-consumption
standby modes.
Putting the MCU into wait mode while the FLASH is in read mode does not affect
the operation of the FLASH memory directly; however, no memory activity will take
place since the CPU is inactive.
The WAIT instruction should not be executed while performing a program or erase
operation on the FLASH. Wait mode will suspend any FLASH program/erase
operations and leave the memory in a standby mode.
Putting the MCU into stop mode while the FLASH is in read mode does not affect
the operation of the FLASH memory directly; however, no memory activity will take
place since the CPU is inactive.
The STOP instruction should not be executed while performing a program or erase
operation on the FLASH. Stop mode will suspend any FLASH program/erase
operations and leave the memory in a standby mode.
NOTE: Standby mode is the power saving mode of the FLASH module, in which all internal
control signals to the FLASH are inactive and the current consumption of the
FLASH is minimum.
2.7 FLASH-2 Memory (FLASH-2)
This subsection describes the operation of the embedded FLASH-2 memory. This
cale Semiconductor,
2.7.1 Functional Description
Frees
memory can be read, programmed, and erased from a single external supply. The
program and erase operations are enabled through the use of an internal charge
pump.
The FLASH-2 memory is a non-continuous array consisting of a total of 29,822
bytes. An erased bit reads as a 1 and a programmed bit reads as a 0.
Memory in the FLASH-2 array is organized into rows within pages. There are two
rows of memory per page with 64 bytes per row. The minimum erase block size is
a single page,128 bytes. Programming is performed on a per-row basis, 64 bytes
at a time. Program and erase operations are facilitated through control bits in the
FLASH-2 control register (FL2CR). Details for these operations appear later in this
subsection.
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
56 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 57
Freescale Semiconductor, Inc.
The FLASH-2 memory map consists of:
• $0462–$04FF: user memory (158 bytes)
• $0980–$1B7F: user memory (4608 bytes)
• $1E20–$7FFF: user memory (25056 bytes)
• $FF81: FLASH-2 block protect register (FL2BPR)
NOTE: FL2BPR physically resides within FLASH-1 memory addressing space
• $FE08: FLASH-2 control register (FL2CR)
Programming tools are available from Motorola. Contact your local Motorola
representative for more information.
NOTE: A security feature prevents viewing of the FLASH contents.
nc...
I
2.7.2 FLASH-2 Control and Block Protect Registers
Memory
FLASH-2 Memory (FLASH-2)
(1)
2.7.2.1 FLASH-2 Control Register
cale Semiconductor,
Frees
The FLASH-2 array has two registers that control its operation, the FLASH-2
control register (FL2CR) and the FLASH-2 block protect register (FL2BPR).
The FLASH-2 control register (FL2CR) controls FLASH-2 program and erase
operations.
Address: $FE08
Bit 7654321Bit 0
Read:0000
Write:
Reset:00000000
Figure 2-7. FLASH-2 Control Register (FL2CR)
HVEN — High-Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for program
and erase operations in the array. HVEN can only be set if either PGM = 1 or
ERASE = 1 and the proper sequence for program or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
HVEN MASS ERASE PGM
MASS — Mass Erase Control Bit
Setting this read/write bit configures the FLASH-2 array for mass or page erase
operation.
1 = Mass erase operation selected
0 = Page erase operation selected
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 57
For More Information On This Product,
Go to: www.freescale.com
Page 58
Freescale Semiconductor, Inc.
Memory
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is
interlocked with the PGM bit such that both bits cannot be set at t he same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is
interlocked with the ERASE bit such that both bits cannot be equal to 1 or set
to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
2.7.2.2 FLASH-2 Block Protect Register
nc...
I
cale Semiconductor,
Frees
The FLASH-2 block protect register (FL2BPR) is implemented as a byte within the
FLASH-1 memory; therefore, can only be written during a FLASH-1 programming
sequence. The value in this register determines the starting location of the
protected range within the FLASH-2 memory.
Address: $FF81
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
NOTE: The FLASH-2 block protect register (FL2BPR) controls the block protection for the
FLASH-2 array. However, FL2BPR is implemented within the FLASH-1 memory
array and therefore, the FLASH-1 control register (FL1CR) must be used to
program/erase FL2BPR.
FL2BPR[7:0] — Block Protect Register Bits 7 to 0
These eight bits represent bits [14:7] of a 16-bit memory address. Bit 15 is a 0
and bits [6:0] are 0s.
The resultant 16-bit address is used for specifying the start address of the
FLASH-2 memory for block protection. FLASH-2 is protected from this start
address to the end of FLASH-2 memory at $7FFF. With this mechanism, the
protect start address can be $XX00 and $XX80 (128 byte page boundaries)
within the FLASH-2 array.
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Figure 2-8. FLASH-2 Block Protect Register (FL2BPR)
16-BIT MEMORY ADDRESS
START ADDRESS OF FLASH
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
58 Memory MOTOROLA
BLOCK PROTECT
Figure 2-9. FLASH-2 Block Protect Start Address
For More Information On This Product,
Go to: www.freescale.com
0
FLBPR VALUE
0000000
Page 59
Freescale Semiconductor, Inc.
nc...
I
FLASH-2 Memory (FLASH-2)
Table 2-3. FLASH-2 Protected Ranges
FL2BPR[7:0] Protected Range
$FF No Protection
$FE $7F00–$7FFF
$FD
↓
$0B
$0A $0500–$7FFF
$09 $0480–$7FFF
$08
↓
$04
$03 $0462–$7FFF
$02 $0462–$7FFF
$01 $0462–$7FFF
$00 $0462–$7FFF
$7E80–$7FFF
↓
$0580–$7FFF
$0462–$7FFF
↓
$0462–$7FFF
Memory
2.7.3 FLASH-2 Block Protection
cale Semiconductor,
Frees
NOTE: In performing a program or erase operation, the FLASH-2 block protect register
Decreasing the value in FL2BPR by one increases the protected range by one
page (128 bytes). However, programming the block protect register with $FE
protects a range twice that size, 256 bytes, in the corresponding array. $FE means
that locations $7F00–$7FFF are protected in FLASH-2.
The FLASH memory does not exist at some locations. The block protection range
configuration is unaffected if FLASH memory does not exist in that range. Refer to
Figure 2-1 and make sure that the desired locations are protected.
Due to the ability of the on-board charge pump to erase and program the FLASH
memory in the target application, provision is made for protecting blocks of memory
from unintentional erase or program operations due to system malfunction. This
protection is done by using the FLASH-2 block protection register (FL2BPR).
FL2BPR determines the range of the FLASH-2 memory which is to be protected.
The range of the protected area starts from a location defined by FL2BPR and ends
at the bottom of the FLASH-2 memory ($7FFF). When the memory is protected,
the HVEN bit can not be set in either ERASE or PROGRAM operations.
must be read after setting the PGM or ERASE bit and before asserting the
HVEN bit.
When the FLASH-2 block protect register is programmed with all 0’s, the entire
memory is protected from being programmed and erased. When all the bits are
erased (all 1’s), the entire memory is accessible for program and erase.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 59
For More Information On This Product,
Go to: www.freescale.com
Page 60
Memory
When bits within FL2BPR are programmed (0), they lock a block of memory
address ranges as shown in 2.7.2.2 FLASH-2 Block Protect Register. If FL2BPR
is programmed with any value other than $FF, the protected block of FLASH
memory can not be erased or programmed.
NOTE: The vector locations and the FLASH block protect registers are located in the same
page. FL1BPR and FL2BPR are not protected with special hardware or software.
Therefore, if this page is not protected by FL1BPR and the vector locations are
erased by either a page or a mass erase operation, both FL1BPR and FL2BPR will
also get erased.
2.7.4 FLASH-2 Mass Erase Operation
Use this step-by-step procedure to erase the entire FLASH-2 memory:
nc...
I
1. Set both the ERASE bit and the MASS bit in the FLASH-2 control register
2. Read the FLASH-2 block protect register (FL2BPR).
Freescale Semiconductor, Inc.
(FL2CR).
cale Semiconductor,
Frees
NOTE: Mass erase is disabled whenever any block is protected (FL2BPR does not equal
$FF).
3. Write to any FLASH-2 address within the FLASH-2 array with any data.
4. Wait for a time, t
5. Set the HVEN bit.
6. Wait for a time, t
7. Clear the ERASE and MASS bits.
8. Wait for a time, t
9. Clear the HVEN bit.
10. Wait for a time, t
accessed in normal read mode.
NOTES: A. Programming and erasing of FLASH locations can not be performed by code
being executed from the same FLASH array.
B. While the se operations must be performed in the order shown, other unrelated
operations may occur between the steps. However, care must be taken to
ensure that these operations do not access any address within the FLASH
array memory space such as the COP control register (COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during program/erase
operations.
(minimum 10 µs).
NVS
MERASE
NVHL
RCV
(minimum 4 ms).
(minimum 100 µs).
, (typically 1 µs) after which the memory can be
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
60 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 61
2.7.5 FLASH-2 Page Erase Operation
Use this step-by-step procedure to erase a page (128 bytes) of FLASH-2 memory:
1. Set the ERASE bit and clear the MASS bit in the FLASH-2 control register
2. Read the FLASH-2 block protect register (FL2BPR).
3. Write any data to any FLASH-2 address within the address range of the
4. Wait for time, t
5. Set the HVEN bit.
6. Wait for time, t
7. Clear the ERASE bit.
8. Wait for time, t
nc...
I
9. Clear the HVEN bit.
10. Wait for a time, t
Freescale Semiconductor, Inc.
(FL2CR).
page (128 byte block) to be erased.
accessed in normal read mode.
(minimum 10 µs).
NVS
(minimum 1 ms or 4 ms).
ERASE
(minimum 5 µs).
NVH
, (typically 1 µs) after which the memory can be
RCV
Memory
FLASH-2 Memory (FLASH-2)
NOTES: A. Programming and erasing of FLASH locations can not be performed by code
B. While the se operations must be performed in the order shown, other unrelated
C. It is highly recommended that interrupts be disabled during program/erase
In applications that require more than 1000 program/erase cycles, use the 4 ms
page erase specification to get improved long-term reliability. Any application can
use this 4 ms page erase specification. However, in applications where a FLASH
cale Semiconductor,
2.7.6 FLASH-2 Program Operation
Frees
location will be erased and reprogrammed less than 1000 times, and speed is
important, use the 1 ms page erase specification to get a shorter cycle time.
Programming of the FLASH memory is done on a row basis. A row consists of 64
consecutive bytes with address ranges as follows:
being executed from the same FLASH array.
operations may occur between the steps. However, care must be taken to
ensure that these operations do not access any address within the FLASH
array memory space such as the COP control register (COPCTL) at $FFFF.
operations.
• $XX00 to $XX3F
• $XX40 to $XX7F
• $XX80 to $XXBF
• $XXC0 to $XXFF
During the programming cycle, make sure that all addresses being written to fit
within one of the ranges specified above. Attempts to program addresses in
different row ranges in one programming cycle will fail.
NOTE: Only bytes which are currently $FF may be programmed.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 61
For More Information On This Product,
Go to: www.freescale.com
Page 62
nc...
I
Memory
Freescale Semiconductor, Inc.
Use this step-by-step procedure to program a row of FLASH-2 memory:
1. Set the PGM bit in the FLASH-2 control register (FL2CR). This configures
the memory for program operation and enables the latching of address and
data programming.
2. Read the FLASH-2 block protect register (FL2BPR).
3. Write to any FLASH-2 address within the row address range desired with
any data.
4. Wait for time, t
5. Set the HVEN bit.
6. Wait for time, t
7. Write data byte to the FLASH-2 address to be programmed.
8. Wait for time, t
9. Repeat step 7 and 8 until all the bytes within the row are programmed.
10. Clear the PGM bit.
11. Wait for time, t
12. Clear the HVEN bit.
13. Wait for a time, t
accessed in normal read mode.
(minimum 10 µs).
NVS
(minimum 5 µs).
PGS
(minimum 30 µs).
PROG
(minimum 5 µs).
NVH
, (typically 1 µs) after which the memory can be
RCV
cale Semiconductor,
Frees
The FLASH programming algorithm flowchart is shown in Figure 2-10.
NOTES: A. Programming and erasing of FLASH locations can not be performed by code
being executed from the same FLASH array.
B. While the se operations must be performed in the order shown, other unrelated
operations may occur between the steps. However, care must be taken to
ensure that these operations do not access any address within the FLASH
array memory space such as the COP control register (COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during program/erase
operations.
D. Do not exceed t
cumulative high voltage programming time to the same row before next erase.
t
must satisfy this condition:
HV
t
+ t
NVS
E. The time between each FLASH address change (step 7 to step 7), or the time
between the last FLASH address programmed to clearing the PGM bit (step 7
to step 10) must not exceed the maximum programming time, t
F. Be cautious when programming the FLASH-2 array to ensure that non-FLASH
locations are not used as the address that is written to when selecting either the
desired row address range in step 3 of the algorithm or the byte to be
programmed in step 7 of the algorithm.
NVH
PROG
+ t
maximum or t
+ (t
PGS
PROG
X
64) ≤ t
maximum. t
HV
maximum
HV
is defined as the
HV
PROG
maximum.
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
62 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 63
Freescale Semiconductor, Inc.
Memory
FLASH-2 Memory (FLASH-2)
nc...
I
cale Semiconductor,
Frees
Algorithm for programming
a row (64 bytes) of FLASH memory
1
2
3
WRITE ANY DATA TO ANY FLASH
4
5
6
7
8
SET PGM BIT
READ THE FLASH BLOCK
PROTECT REGISTER
ADDRESS WITHIN THE ROW
ADDRESS RANGE DESIRED
WAIT FOR A TIME, t
SET HVEN BIT
WAIT FOR A TIME, t
WRITE DATA TO THE FLASH
ADDRESS TO BE PROGRAMMED
WAIT FOR A TIME, t
COMPLETED
PROGRAMMING
THIS ROW?
NO
NVS
PGS
PROG
10
11
YES
CLEAR PGM BIT
WAIT FOR A TIME, t
NVH
NOTES:
The time between each FLASH address change (step 7 to step 7) or
the time between the last FLASH address programmed to clearing
PGM bit (step 7 to step10) must not exceed the maximum
programming time, t
This row program algorithm assumes the row/s to be
programmed are initially erased.
PROG
, maximum.
12
13
CLEAR HVEN BIT
WAIT FOR A TIME, t
END OF PROGRAMMING
RCV
Figure 2-10. FLASH-2 Programming Algorithm Flowchart
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Memory 63
For More Information On This Product,
Go to: www.freescale.com
Page 64
Memory
2.7.7 Low-Power Modes
2.7.7.1 Wait Mode
nc...
2.7.7.2 Stop Mode
I
Freescale Semiconductor, Inc.
The WAIT and STOP instructions will place the MCU in low power-consumption
standby modes.
Putting the MCU into wait mode while the FLASH is in read mode does not affect
the operation of the FLASH memory directly; however, no memory activity will take
place since the CPU is inactive.
The WAIT instruction should not be executed while performing a program or erase
operation on the FLASH. Wait mode will suspend any FLASH program/erase
operations and leave the memory in a standby mode.
Putting the MCU into stop mode while the FLASH is in read mode does not affect
the operation of the FLASH memory directly; however, no memory activity will take
place since the CPU is inactive.
cale Semiconductor,
Frees
The STOP instruction should not be executed while performing a program or erase
operation on the FLASH. Stop mode will suspend any FLASH program/erase
operations and leave the memory in a standby mode.
NOTE: Standby mode is the power saving mode of the FLASH module, in which all internal
control signals to the FLASH are inactive and the current consumption of the
FLASH is minimum.
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
64 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 65
Data Sheet — MC68HC908GZ60
3.1 Introduction
This section describes the 10-bit analog-to-digital converter (ADC).
3.2 Features
Features of the ADC module include:
nc...
I
Freescale Semiconductor, Inc.
Section 3. Analog-to-Digital Converter (ADC)
• 24 channels with multiplexed input
• Linear successive approximation with monotonicity
• 10-bit resolution
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
3.3 Functional Description
cale Semiconductor,
3.3.1 ADC Port I/O Pins
Frees
• Selectable ADC clock
• Left or right justified result
• Left justified sign data mode
The ADC provides 24 pins for sampling external sources at pins
PTG7/AD23–PTG0/AD16, PTA7/KBD7/AD15–PTA0/KBD0/AD8, and
PTB7/AD7–PTB0/AD0. An analog multiplexer allows the single ADC converter to
select one of 24 ADC channels as ADC voltage in (V
the successive approximation register-based analog-to-digital converter. When the
conversion is completed, ADC places the result in the ADC data register and sets
a flag or generates an interrupt. See Figure 3-2.
PTG7/AD23–PTG0/AD16, PTA7/KBD7/AD15–PTA0/KBD0/AD8, and
PTB7/AD7–PTB0/AD0 are general-purpose I/O (input/output) pins that share with
the ADC channels. The channel select bits define which ADC channel/port pin will
be used as the input signal. The ADC overrides the port I/O logic by forcing that pin
as input to the ADC. The remaining ADC channels/port pins are controlled by the
port I/O logic and can be used as general-purpose I/O. Writes to the port register
or data direction register (DDR) will not have any affect on the port pin that is
selected by the ADC. A read of a port pin in use by the ADC will return a 0.
ADIN
). V
is converted by
ADIN
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Analog-to-Digital Converter (ADC) 65
For More Information On This Product,
Go to: www.freescale.com
Page 66
Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
(2)
(2)
(2)
PTD3/SPSCK
PTD2/MOSI
PTD1/MISO
PORTD
DDRD
PROPERLY MODULE
COMPUTER OPERATING
(2)
PTD0/SS/MCLK
PTE1/RxD
PTE5–PTE2
DDRE
SERIAL PERIPHERAL
INTERFACE MODULE
MONITOR MODE ENTRY
PTE0/TxD
PORTE
MODULE
PTF6/T2CH4
PTF5/T2CH3
PTF7/T2CH5
MODULE
SECURITY
(3)
PTF4/T2CH2
PTF3–PFT0
PORTF
DDRF
MODULE
MEMORY MAP
CONFIGURATION REGISTER 1–2
PTG7/AD23–PTG0/AD16
MODULE
PORTG
DDRG
MSCAN
MODULE
(2)
TX
PTD7/T2CH1
PTC0/CAN
MODULE
6-CHANNEL TIMER INTERFACE
(2)
(2, 3)
(2, 3)
(2, 3)
PTC3
(2, 3)
PTC2
PORTC
DDRC
2-CHANNEL TIMER INTERFACE
RX
PTC1/CAN
MODULE
(2)
(2)
(2, 3)
PTC6
PTC5
PTA7/KBD7/AD15–PTA0/KBD0/AD8
PORTA
nc...
I
INTERNAL BUS
DDRA
MODULE
PROGRAMMABLE TIMEBASE
PTB7/AD7–PTB0/AD0
PORTB
DDRB
MODULE
DUAL VOLTAGE
SINGLE BREAKPOINT BREAK
PTC4
8-BIT KEYBOARD
INTERRUPT MODULE
LOW-VOLTAGE INHIBIT MODULE
(2)
(2)
(2)
PTD6/T2CH0
PTD5/T1CH1
PTD4/T1CH0
COMMUNICATIONS
ENHANCED SERIAL
INTERFACE MODULE
cale Semiconductor,
Frees
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
66 Analog-to-Digital Converter (ADC) MOTOROLA
UNIT (ALU)
ARITHMETIC/LOGIC
M68HC08 CPU
CPU
REGISTERS
USER FLASH — 62,078 BYTES
CONTROL AND STATUS REGISTERS — 64 BYTES
USER RAM — 2048 BYTES
MONITOR ROM
1–8 MHz OSCILLATOR
CLOCK GENERATOR MODULE
OSC1
USER FLASH VECTOR SPACE — 52 BYTES
OSC2
PHASE LOCKED LOOP
CGMXFC
MODULE
SYSTEM INTEGRATION
(1)
RST
SINGLE EXTERNAL
INTERRUPT MODULE
10-BIT ANALOG-TO-DIGITAL
(1)
REFH
IRQ
/V
DDAD
V
MODULE
POWER-ON RESET
CONVERTER MODULE
REFL
/V
SSAD
V
V
DD
POWER
SS
DDA
V
V
SSA
V
For More Information On This Product,
Go to: www.freescale.com
1. Pin contains integrated pullup device.
2. Ports are software configurable with pullup device if input port or pullup/pulldown device for keyboard input.
3. Higher current drive port pins
Figure 3-1. Block Diagram Highlighting ADC Block and Pins
Page 67
Freescale Semiconductor, Inc.
INTERNAL
DATA BUS
READ DDRx
Analog-to-Digital Converter (ADC)
Functional Description
nc...
I
cale Semiconductor,
3.3.2 Voltage Conversion
Frees
WRITE DDRx
DDRx
PTx
ADC DATA REGISTER
ADC
ADC CLOCK
CLOCK
GENERATOR
WRITE PTx
READ PTx
INTERRUPT
LOGIC
AIEN COCO
RESET
CONVERSION
COMPLETE
CGMXCLK
BUS CLOCK
ADIV2–ADIV0 ADICLK
Figure 3-2. ADC Block Diagram
When the input voltage to the ADC equals V
$3FF (full scale). If the input voltage equals V
Input voltages between V
REFH
and V
are a straight-line linear conversion.
REFL
DISABLE
PTx
ADC CHANNEL x
DISABLE
ADC
VOLTAGE IN
)
(V
ADIN
, the ADC converts the signal to
REFH
, the ADC converts it to $000.
REFL
CHANNEL
SELECT
ADCH4–ADCH0
NOTE: The ADC input voltage must always be greater than V
Connect the V
the V
The V
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Analog-to-Digital Converter (ADC) 67
pin to the same voltage potential as the VSS pin.
SSAD
pin should be routed carefully for maximum noise immunity.
DDAD
For More Information On This Product,
pin to the same voltage potential as the VDD pin, and connect
DDAD
Go to: www.freescale.com
and less than V
SSAD
DDAD
.
Page 68
Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
3.3.3 Conversion Time
Conversion starts after a write to the ADC status and control register (ADSCR).
One conversion will take between 16 and 17 ADC clock cycles. The ADIVx and
ADICLK bits should be set to provide a 1-MHz ADC clock frequency.
3.3.4 Conversion
nc...
I
3.3.5 Accuracy and Precision
3.3.6 Result Justification
cale Semiconductor,
Frees
Conversion time =
Number of bus cycles = conversion time × bus frequency
In continuous conversion mode, the ADC data register will be filled with new data
after each conversion. Data from the previous conversion will be overwritten
whether that data has been read or not. Conversions will co ntinue until the ADCO
bit is cleared. The COCO bit is set after each conversion and will stay set until the
next read of the ADC data register.
In single conversion mode, conversion begins with a write to the ADSCR. Only one
conversion occurs between writes to the ADSCR.
When a conversion is in process and the ADSCR is written, the current conversion
data should be discarded to prevent an incorrect reading.
The conversion process is monotonic and has no missing codes.
The conversion result may be formatted in four different ways:
1. Left justified
2. Right justified
3. Left Justified sign data mode
4. 8-bit truncation mode
All four of these modes are controlled using MODE0 and MODE1 bits located in
the ADC clock register (ADCLK).
16 to 17 ADC cycles
ADC frequency
Left justification will place the eight most significant bits (MSB) in the corresponding
ADC data register high, ADRH. This may be useful if the result is to be treated as
an 8-bit result where the two least significant bits (LSB), located in the ADC data
register low, ADRL, can be ignored. However, ADRL must be read after ADRH or
else the interlocking will prevent all new conversions from being stored.
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
68 Analog-to-Digital Converter (ADC) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 69
Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
Monotonicity
Right justification will place only the two MSBs in the corresponding ADC data
register high, ADRH, and the eight LSBs in ADC data register low, ADRL. This
mode of operation typically is used when a 10-bit unsigned result is desired.
Left justified sign data mode is similar to left justified mode with one exception. The
MSB of the 10-bit result, AD9 located in ADRH, is complemented. This mode of
operation is useful when a result, represented as a signed magnitude from
mid-scale, is needed. Finally, 8-bit truncation mode will place the eight MSBs in the
ADC data register low, ADRL. The two LSBs are dropped. This mode of opera tion
is used when compatibility with 8-bit ADC designs are required. No interlocking
between ADRH and ADRL is present.
NOTE: Quantization error is affected when only the most significant eight bits are used as
a result. See Figure 3-3.
nc...
I
8-BIT
RESULT
003
10-BIT
RESULT
00B
IDEAL 8-BIT CHARACTERISTIC
WITH QUANTIZATION = ±1/2
10-BIT TRUNCATED
TO 8-BIT RESULT
cale Semiconductor,
Frees
3.4 Monotonicity
002
001
000
00A
IDEAL 10-BIT CHARACTERISTIC
009
WITH QUANTIZATION = ±1/2
008
007
006
005
004
003
002
001
000
1/2 2 1/2 4 1/2 6 1/2 8 1/2
1 1/2 3 1/2 5 1/2 7 1/2 9 1/2
1/2 2 1/21 1/2
Figure 3-3. Bit Truncation Mode Error
WHEN TRUNCATION IS USED,
ERROR FROM IDEAL 8-BIT = 3/8 LSB
DUE TO NON-IDEAL QUANTIZATION.
INPUT VOLTAGE
REPRESENTED AS 10-BIT
INPUT VOLTAGE
REPRESENTED AS 8-BIT
The conversion process is monotonic and has no missing codes.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Analog-to-Digital Converter (ADC) 69
For More Information On This Product,
Go to: www.freescale.com
Page 70
Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
3.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating CPU interrupts
after each ADC conversion. A CPU interrupt is generated if the COCO bit is a 0.
The COCO bit is not used as a conversion complete flag when interrupts are
enabled.
3.6 Low-Power Modes
The WAIT and STOP instruction can put the MCU in low power- consumption
standby modes.
3.6.1 Wait Mode
nc...
I
3.6.2 Stop Mode
3.7 I/O Signals
cale Semiconductor,
Frees
3.7.1 ADC Analog Power Pin (V
The ADC continues normal operation during wait mode. Any enabled CPU interrupt
request from the ADC can bring the MCU out of wait mode. If the ADC is not
required to bring the MCU out of wait mode, power down the ADC by setting
ADCH4–ADCH0 bits in the ADC status and control register before executing the
WAIT instruction.
The ADC module is inactive after the execution of a STOP instruction. Any pending
conversion is aborted. ADC conversions resume when the MCU exits stop mode
after an external interrupt. Allow one conversion cycle to stabilize the analog
circuitry.
The ADC module has eight pins shared with port A and the KBI module:
PTA7/KBD7/AD15–PTA0/KBD0/AD8
The ADC module has eight pins shared with port B:
PTB7/AD7–PTB0/AD0
The ADC module has eight pins shared with port G:
PTG7/AD23–PTG0/AD16
)
DDAD
The ADC analog portion uses V
the same voltage potential as V
clean V
NOTE: For maximum noise immunity, route V
as close as possible to the package.
V
DDAD
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
70 Analog-to-Digital Converter (ADC) MOTOROLA
for good results.
DDAD
and V
are bonded internally.
REFH
For More Information On This Product,
Go to: www.freescale.com
as its power pin. Connect the V
DDAD
. External filtering may be necessary to ensure
DD
carefully and place bypass capacitors
DDAD
DDAD
pin to
Page 71
Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
I/O Registers
3.7.2 ADC Analog Ground Pin (V
The ADC analog portion uses V
the same voltage potential as V
NOTE: Route V
V
SSAD
3.7.3 ADC Voltage Reference High Pin (V
The ADC analog portion uses V
connect the V
often necessary to ensure a clean V
this pin will be reflected and possibly magnified in A/D conversion values.
nc...
I
3.7.4 ADC Voltage Reference Low Pin (V
cale Semiconductor,
3.7.5 ADC Voltage In (V
Frees
NOTE: For maximum noise immunity, route V
as close as possible to the package. Routing V
may improve common mode noise rejection.
V
DDAD
The ADC analog portion uses V
connect the V
often necessary to ensure a clean V
pin will be reflected and possibly magnified in A/D conversion values.
NOTE: For maximum noise immunity, route V
place bypass capacitors as close as possible to the package. Routing V
and parallel to V
V
SSAD
V
ADIN
module.
SSAD
and V
and V
and V
)
ADIN
is the input voltage signal from one of the 24 ADC channels to the ADC
)
SSAD
as its ground pin. Connect the V
SSAD
.
SS
cleanly to avoid any offset errors.
are bonded internally.
REFL
)
REFH
as its upper voltage reference pin. By default,
REFH
pin to the same voltage potential as VDD. External filtering is
REFH
for good results. Any noise present on
REFH
carefully and place bypass capacitors
REFH
close and parallel to V
REFH
are bonded internally.
REFH
)
REFL
as its lower voltage reference pin. By default,
REFL
pin to the same voltage potential as VSS. External filtering is
REFL
for good results. Any noise present on this
REFL
carefully and, if not connected to VSS,
REFL
may improve common mode noise rejection.
REFL
are bonded internally.
REFL
SSAD
REFH
pin to
REFL
close
3.8 I/O Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADRH and ADRL)
• ADC clock register (ADCLK)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Analog-to-Digital Converter (ADC) 71
For More Information On This Product,
Go to: www.freescale.com
Page 72
Analog-to-Digital Converter (ADC)
3.8.1 ADC Status and Control Register
Function of the ADC status and control register (ADSCR) is described here.
Address: $003C
Read: COCO
Write: R
Reset:00011111
COCO — Conversions Complete Bit
nc...
I
NOTE: The write function of the COCO bit is reserved. When writing to the ADSCR
In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end
of each conversion. COCO will stay set until cleared by a read of the ADC data
register. Reset clears this bit.
In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end
of a conversion. It always reads as a 0.
register, always have a 0 in the COCO bit position.
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion.
The interrupt signal is cleared when the data register is read or the status/control
register is written. Reset clears the AIEN bit.
cale Semiconductor,
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the ADR
register at the end of each conversion. Only one conversion is completed
Frees
between writes to the ADSCR when this bit is cleared. Reset clears the ADCO
bit.
Freescale Semiconductor, Inc.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled
1 = ADC interrupt enabled
0 = ADC interrupt disabled
1 = Continuous ADC conversion
0 = One ADC conversion
Bit 7654321Bit 0
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
R= Reserved
Figure 3-4. ADC Status and Control Register (ADSCR)
(AIEN = 1)
ADCH4–ADCH0 — ADC Channel Select Bits
ADCH4–ADCH0 form a 5-bit field which is used to select one of 32 ADC
channels. Only 24 channels, AD23–AD0, are available on this MCU. The
channels are detailed in Table 3-1. Care should be taken when using a port pin
as both an analog and digital input simultaneously to prevent switching noise
from corrupting the analog signal. See Table 3-1.
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
72 Analog-to-Digital Converter (ADC) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 73
Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
I/O Registers
The ADC subsystem is turned off when the channel select bits are all set to 1.
This feature allows for reduced power consumption for the MCU when the ADC
is not being used.
NOTE: Recovery from the disabled state requires one conversion cycle to stabilize.
The voltage levels supplied from internal reference nodes, as specified in
Table 3-1, are used to verify the operation of the ADC converter both in production
test and for user applications.
nc...
I
cale Semiconductor,
Frees
Table 3-1. Mux Channel Select
ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select
00000 PTB0/AD0
00001 PTB1/AD1
00010 PTB2/AD2
00011 PTB3/AD3
00100 PTB4/AD4
00101 PTB5/AD5
00110 PTB6/AD6
00111 PTB7/AD7
0 1 0 0 0 PTA0/KBD0/AD8
0 1 0 0 1 PTA1/KBD1/AD9
0 1 0 1 0 PTA2/KBD2/AD10
0 1 0 1 1 PTA3/KBD3/AD11
0 1 1 0 0 PTA4/KBD4/AD12
0 1 1 0 1 PTA5/KBD5/AD13
0 1 1 1 0 PTA6/KBD6/AD14
0 1 1 1 1 PTA7/KBD7/AD15
1 0 0 0 0 PTG0/AD16
1 0 0 0 1 PTG1/AD17
1 0 0 1 0 PTG2/AD18
1 0 0 1 1 PTG3/AD19
1 0 1 0 0 PTG4/AD20
1 0 1 0 1 PTG5/AD21
1 0 1 1 0 PTG6/AD22
1 0 1 1 1 PTG7/AD23
1
↓
1
11101
11110
11111ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be unknown or
reserved.
1
↓
1
0
↓
1
0
↓
0
(1)
0
↓
0
Unused
V
REFH
V
REFL
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Analog-to-Digital Converter (ADC) 73
For More Information On This Product,
Go to: www.freescale.com
Page 74
Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
3.8.2 ADC Data Register High and Data Register Low
3.8.2.1 Left Justified Mode
In left justified mode, the ADRH register holds the eight MSBs of the
10-bit result. The ADRL register holds the two LSBs of the 10-bit result. All other
bits read as 0. ADRH and ADRL are updated each time an ADC single channel
conversion completes. Reading ADRH latches the contents of ADRL until ADRL is
read. All subsequent results will be lost until the ADRH and ADRL reads are
completed.
Address: $003D ADRH
Bit 7654321Bit 0
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
nc...
I
3.8.2.2 Right Justified Mode
cale Semiconductor,
Frees
Write:
Reset: Unaffected by reset
Address: $003E ADRL
Read:AD1AD0000000
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 3-5. ADC Data Register High (ADRH) and Low (ADRL)
In right justified mode, the ADRH register holds the two MSBs of the
10-bit result. All other bits read as 0. The ADRL register holds the eight LSBs of the
10-bit result. ADRH and ADRL are updated each time an ADC single channel
conversion completes. Reading ADRH latches the contents of ADRL until ADRL is
read. All subsequent results will be lost until the ADRH and ADRL reads are
completed.
Address: $003D ADRH
Bit 7654321Bit 0
Read:000000AD9AD8
Write:
Reset: Unaffected by reset
Address: $003E ADRL
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 3-6. ADC Data Register High (ADRH) and Low (ADRL)
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
74 Analog-to-Digital Converter (ADC) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 75
3.8.2.3 Left Justified Signed Data Mode
In left justified signed data mode, the ADRH register holds the eight MSBs of the
10-bit result. The only difference from left justified mode is that the AD9 is
complemented. The ADRL register holds the two LSBs of the 10-bit result. All other
bits read as 0. ADRH and ADRL are updated each time an ADC single channel
conversion completes. Reading ADRH latches the contents of ADRL until ADRL is
read. All subsequent results will be lost until the ADRH and ADRL reads are
completed.
Address: $003D
nc...
I
Address: $003E
Freescale Semiconductor, Inc.
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write:
Reset: Unaffected by reset
Read:AD1AD0000000
Write:
Reset: Unaffected by reset
Analog-to-Digital Converter (ADC)
I/O Registers
Bit 7654321Bit 0
= Unimplemented
3.8.2.4 Eight Bit Truncation Mode
cale Semiconductor,
Frees
Figure 3-7. ADC Data Register High (ADRH) and Low (ADRL)
In 8-bit truncation mode, the ADRL register holds the eight MSBs of the 10-bit
result. The ADRH register is unused and reads as 0. The ADRL register is updated
each time an ADC single channel conversion completes. In 8-bit mode, the ADRL
register contains no interlocking with ADRH.
Address: $003D ADRH
Bit 7654321Bit 0
Read:00000000
Write:
Reset: Unaffected by reset
Address: $003E ADRL
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 3-8. ADC Data Register High (ADRH) and Low (ADRL)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Analog-to-Digital Converter (ADC) 75
For More Information On This Product,
Go to: www.freescale.com
Page 76
Analog-to-Digital Converter (ADC)
3.8.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
Address: $003F
ADIV2–ADIV0 — ADC Clock Prescaler Bits
nc...
I
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC
to generate the internal ADC clock. Table 3-2 shows the available clock
configurations. The ADC clock should be set to approximately 1 MHz.
Freescale Semiconductor, Inc.
Read:
Write:
Reset:00000100
Bit 7654321Bit 0
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 R
= Unimplemented R = Reserved
Figure 3-9. ADC Clock Register (ADCLK)
0
cale Semiconductor,
Frees
Table 3-2. ADC Clock Divide Ratio
ADIV2 ADIV1 ADIV0 ADC Clock Rate
0 0 0 ADC input clock ÷ 1
0 0 1 ADC input clock ÷ 2
0 1 0 ADC input clock ÷ 4
0 1 1 ADC input clock ÷ 8
1
1. X = Don’t care
ADICLK — ADC Input Clock Select Bit
ADICLK selects either the bus clock or the oscillator output clock (CGMXCLK)
as the input clock source to generate the internal ADC clock. Reset selects
CGMXCLK as the ADC clock source.
1 = Internal bus clock
0 = Oscillator output clock (CGMXCLK)
The ADC requires a clock rate of approximately 1 MHz for correct operation. If the
selected clock source is not fast enough, the ADC will generate incorrect
conversions. See 21.10 5.0-Volt ADC Characteristics.
(1)
X
(1)
X
ADC input clock ÷ 16
f
=
CGMXCLK
f
ADIC
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
76 Analog-to-Digital Converter (ADC) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
or bus frequency
≅ 1 MHz
ADIV[2:0]
Page 77
Freescale Semiconductor, Inc.
MODE1 and MODE0 — Modes of Result Justification Bits
MODE1 and MODE0 select among four modes of operation. The manner in
which the ADC conversion results will be placed in the ADC data registers is
controlled by these modes of operation. Reset returns right-justified mode.
00 = 8-bit truncation mode
01 = Right justified mode
10 = Left justified mode
11 = Left justified signed data mode
nc...
I
Analog-to-Digital Converter (ADC)
I/O Registers
cale Semiconductor,
Frees
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Analog-to-Digital Converter (ADC) 77
For More Information On This Product,
Go to: www.freescale.com
Page 78
Analog-to-Digital Converter (ADC)
nc...
I
Freescale Semiconductor, Inc.
cale Semiconductor,
Frees
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
78 Analog-to-Digital Converter (ADC) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 79
Data Sheet — MC68HC908GZ60
4.1 Introduction
This section describes the clock generator module. The CGM generates the crystal
clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM
also generates the base clock signal, CGMOUT, which is based on either the
crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK,
divided by two. In user mode, CGMOUT is the clock from which the SIM derives
the system clocks, including the bus clock, which is at a frequency of CGMOUT/2.
nc...
I
The PLL is a fully functional frequency generator designed for use with crystals or
ceramic resonators. The PLL can generate a maximum bus frequency of 8 MHz
using a 1-8MHz crystal or external clock source.
Freescale Semiconductor, Inc.
Section 4. Clock Generator Module (CGM)
4.2 Features
cale Semiconductor,
4.3 Functional Description
Frees
Features of the CGM include:
• Phase-locked loop with output frequency in integer multiples of an integer
dividend of the crystal reference
• High-frequency crystal operation with low-power operation and high-output
frequency resolution
• Programmable hardware voltage-controlled oscillator (VCO) for low-jitter
operation
• Automatic bandwidth control mode for low-jitter operation
• Automatic frequency lock detector
• CPU interrupt on entry or exit from locked condition
• Configuration register bit to allow oscillator operation during stop mode
The CGM consists of three major submodules:
• Crystal oscillator circuit — The crystal oscillator circuit generates the
constant crystal frequency clock, CGMXCLK.
• Phase-locked loop (PLL) — The PLL generates the programmable VCO
frequency clock, CGMVCLK.
• Base clock selector circuit — This software-controlled circuit selects either
CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as
the base clock, CGMOUT. The SIM derives the system clocks from either
CGMOUT or CGMXCLK.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Clock Generator Module (CGM) 79
For More Information On This Product,
Go to: www.freescale.com
Page 80
Clock Generator Module (CGM)
Figure 4-1 shows the structure of the CGM.
OSC2
OSC1
SIMOSCEN (FROM SIM)
OSCENINSTOP
(FROM CONFIG)
nc...
I
Freescale Semiconductor, Inc.
OSCILLATOR (OSC)
PHASE-LOCKED LOOP (PLL)
CGMXCLK
(TO: SIM, TBM, ADC, MSCAN)
cale Semiconductor,
Frees
CGMRCLK
V
DDA
PHASE
DETECTOR
LOCK
DETECTOR
LOCK AUTO ACQ
MUL11–MUL0
CGMXFC V
LOOP
FILTER
AUTOMATIC
MODE
CONTROL
SSA
VRS7–VRS0
PLL ANALOG
BCS
VPR1–VPR0
VOLTAGE
CONTROLLED
OSCILLATOR
INTERRUPT
CONTROL
PLLIE PLLF
CLOCK
SELECT
CIRCUIT
WHEN S = 1,
*
CGMOUT = B
CGMVCLK
A
÷
2
B
S*
CGMOUT
(TO SIM)
SIMDIV2
(FROM SIM)
CGMINT
(TO SIM)
CGMVDV
FREQUENCY
DIVIDER
Figure 4-1. CGM Block Diagram
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
80 Clock Generator Module (CGM) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 81
4.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external
crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output.
The SIMOSCEN signal from the system integration module (SIM) or the
OSCENINSTOP bit in the CONFIG register enable the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate
equal to the crystal frequency. CGMXCLK is then buffered to produce CGMRCLK,
the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for
operation. The duty cycle of CGMXCLK is not guaranteed to be 50% and depends
on external factors, including the crystal and related external components. An
externally generated clock also can feed the OSC1 pin of the crystal oscillator
nc...
I
4.3.2 Phase-Locked Loop Circuit (PLL)
circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float.
Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Functional Description
4.3.3 PLL Circuits
cale Semiconductor,
Frees
The PLL is a frequency generator that can operate in either acquisition mode or
tracking mode, depending on the accuracy of the output frequency. The PLL can
change between acquisition and tracking modes either automatically or manually.
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
The operating range of the VCO is programmable for a wide range of frequencies
and for maximum immunity to external noise, including supply and CGMXFC noise.
The VCO frequency is bound to a range from roughly one-half to twice the
center-of-range frequency, f
changes the frequency within this range. By design, f
center-of-range frequency, f
power-of-two factor, E, or (L × 2
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, f
running at a frequency, f
The modulo divider reduces the VCO clock by a factor, N. The dividers output is
the VCO feedback clock, CGMVDV, running at a frequency, f
more information, see 4.3.6 Programming the PLL.)
VCLK
. Modulating the voltage on the CGMXFC pin
VRS
is equal to the nominal
VRS
, (71.4 kHz) times a linear factor, L, and a
NOM
E
)f
.
NOM
. The VCO’s output clock, CGMVCLK,
RCLK
, is fed back through a programmable modulo divider.
VDV=fVCLK
/(N). (For
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Clock Generator Module (CGM) 81
For More Information On This Product,
Go to: www.freescale.com
Page 82
Clock Generator Module (CGM)
The phase detector then compares the VCO feedback clock, CGMVDV, with the
final reference clock, CGMRDV. A correction pulse is generated based on the
phase difference between the two signals. The loop filter then slightly alters the DC
voltage on the external capacitor connected to CGMXFC based on the width and
direction of the correction pulse. The filter can make fast or slow corrections
depending on its mode, described in 4.3.4 Acquisition and Tracking Modes. The
value of the external capacitor and the reference frequency determines the speed
of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV,
and the reference clock, CGMRCLK. Therefore, the speed of the lock detector is
directly proportional to the reference frequency, f
mode of the PLL and the lock condition based on this comparison.
4.3.4 Acquisition and Tracking Modes
nc...
I
The PLL filter is manually or automatically configurable into one of two operating
modes:
Freescale Semiconductor, Inc.
RCLK
. The circuit determines the
• Acquisition mode — In acquisition mode, the filter can make large frequency
corrections to the VCO. This mode is used at PLL start up or when the PLL
has suffered a severe noise hit and the VCO frequency is far off the desired
frequency. When in acquisition mode, the ACQ
bandwidth control register. (See 4.5.2 PLL Bandwidth Control Register.)
• Tracking mode — In tracking mode, the filter makes only small corrections
to the frequency of the VCO. PLL jitter is much lower in tracking mode, but
the response to noise is also slower. The PLL enters tracking mode when
the VCO frequency is nearly correct, such as when the PLL is selected as
the base clock source. (See 4.3.8 Base Clock Selector Circuit.) The PLL
is automatically in tracking mode when not in acquisition mode or when the
ACQ
bit is set.
cale Semiconductor,
4.3.5 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually
or automatically. Automatic mode is recommended for most users.
Frees
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically
switches between acquisition and tracking modes. Automatic bandwidth control
mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as
the source for the base clock, CGMOUT. (See 4.5.2 PLL Bandwidth Control
Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt
request and then check the LOCK bit. If interrupts are disabled, software can poll
the LOCK bit continuously (for example, during PLL start up) or at periodic
intervals. In either case, when the LOCK bit is set, the VCO clock is safe to use as
the source for the base clock. (See 4.3.8 Base Clock Selector Circuit.) If the VCO
is selected as the source for the base clock and the LOCK bit is clear, the PLL has
suffered a severe noise hit and the software must take appropriate action,
bit is clear in the PLL
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
82 Clock Generator Module (CGM) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 83
Freescale Semiconductor, Inc.
depending on the application. (See 4.6 Interrupts for information and precaut ions
on using interrupts.)
The following conditions apply when the PLL is in automatic bandwidth control
mode:
Clock Generator Module (CGM)
Functional Description
•The ACQ
indicator of the mode of the filter. (See 4.3.4 Acquisition and Tracking
Modes.)
•The ACQ
is cleared when the VCO frequency is out of a certain tolerance. (See 4.8
Acquisition/Lock Time Specifications for more information.)
• The LOCK bit is a read-only indicator of the locked state of the PLL.
• The LOCK bit is set when the VCO frequency is within a certain tolerance
nc...
I
The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by
systems that do not require an indicator of the lock condition for proper operation.
Such systems typically operate well below f
The following conditions apply when in manual mode:
cale Semiconductor,
and is cleared when the VCO frequency is out of a certain tolerance. (See
4.8 Acquisition/Lock Time Specifications for more information.)
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock
condition changes, toggling the LOCK bit. (See 4.5.1 PLL Control
Register.)
•ACQ
turning on the PLL in manual mode, the ACQ
• Before entering tracking mode (ACQ
t
ACQ
PLL by setting PLLON in the PLL control register (PCTL).
• Software must wait a given time, t
selecting the PLL as the clock source to CGMOUT (BCS = 1).
• The LOCK bit is disabled.
bit (See 4.5.2 PLL Bandwidth Control Register.) is a read-only
bit is set when the VCO frequency is within a certain tolerance and
BUSMAX
is a writable control bit that controls the mode of the filter. Before
= 1), software must wait a given time,
(See 4.8 Acquisition/Lock Time Specifications.), after turning on the
, after entering tracking mode before
AL
.
bit must be clear.
Frees
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Clock Generator Module (CGM) 83
• CPU interrupts from the CGM are disabled.
For More Information On This Product,
Go to: www.freescale.com
Page 84
Clock Generator Module (CGM)
4.3.6 Programming the PLL
Use the following procedure to program the PLL. For reference, the variables used
and their meaning are shown in Table 4-1.
nc...
I
Freescale Semiconductor, Inc.
Table 4-1. Variable Definitions
Variable Definition
f
BUSDES
f
VCLKDES
f
RCLK
f
VCLK
f
BUS
f
NOM
f
VRS
Desired bus clock frequency
Desired VCO clock frequency
Chosen reference crystal frequency
Calculated VCO clock frequency
Calculated bus clock frequency
Nominal VCO center frequency
Programmed VCO center frequency
cale Semiconductor,
Frees
NOTE: The round function in the following equations means that the real number should
be rounded to the nearest integer number.
1. Choose the desired bus frequency, f
BUSDES
.
2. Calculate the desired VCO frequency (four times the desired bus
frequency).
f
VCLKDES
3. Choose a practical PLL (crystal) reference frequency, f
= 4 x f
BUSDES
. Typically, the
RCLK
reference crystal is 1–8 MHz.
Frequency errors to the PLL are corrected at a rate of f
RCLK
.
For stability and lock time reduction, this rate must be as fast as possible.
The VCO frequency must be an integer multiple of this rate. The relationship
between the VCO frequency, f
f
VCLK
, and the reference frequency, f
VCLK
= (N) (f
RCLK
)
RCLK,
is:
N, the range multiplier, must be an integer.
In cases where desired bus frequency has some tolerance, choose f
RCLK
to
a value determined either by other module requirements (such as modules
which are clocked by CGMXCLK), cost requirements, or ideally, as high as
the specified range allows. See Section 21. Electrical Specifications.
After choosing N, the actual bus frequency can be determined using
equation in 2 above.
4. Select a VCO frequency multiplier, N.
f
VCLKDES
=
N round
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
84 Clock Generator Module (CGM) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
--------------------------
f
RCLK
Page 85
Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Functional Description
nc...
I
cale Semiconductor,
Frees
5. Calculate and verify the adequacy of the VCO and bus frequencies f
and f
BUS
.
f
VCLK
f
BUS
N() f
f
()4⁄=
VCLK
×=
RCLK
VCLK
6. Select the VCO’s power-of-two range multiplier E, according to Table 4-2.
Table 4-2. Power-of-Two Range Selectors
Frequency Range E
0 < f
8 MHz< f
16 MHz< f
1. Do not program E to a value of 3.
7. Select a VCO linear range multiplier, L, where f
≤ 8 MHz
VCLK
≤ 16 MHz
VCLK
≤ 32 MHz
VCLK
L = Round
f
VCLK
2E x f
NOM
= 71.4 kHz
NOM
0
1
(1)
2
8. Calculate and verify the adequacy of the VCO programmed center-of-range
frequency, f
. The center-of-range frequency is the midpoint between the
VRS
minimum and maximum frequencies attainable by the PLL.
f
= (L x 2E) f
VRS
NOM
9. For proper operation,
f
NOM
-------------------------- -
f
–
VRSfVCLK
≤
10. Verify the choice of N, E, and L by comparing f
For proper operation, f
f
VCLKDES
, and f
must be as close as possible to f
VRS
must be within the application’s tolerance of
VCLK
E
2
×
2
VCLK
to f
VCLK
VRS
.
and f
VCLKDES
NOTE: Exceeding the recommended maximum bus frequency or VCO frequency can
crash the MCU.
.
11. Program the PLL registers accordingly:
a. In the VPR bits of the PLL control register (PCTL), program the binary
equivalent of E.
b. In the PLL multiplier select register low (PMSL) and the PLL multiplier
select register high (PMSH), program the binary equivalent of N. If
using a 1–8 MHz reference, the PMSL register must be reprogrammed
from the reset value before enabling the PLL.
c. In the PLL VCO range select register (PMRS), program the binary
coded equivalent of L.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Clock Generator Module (CGM) 85
For More Information On This Product,
Go to: www.freescale.com
Page 86
Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Table 4-3 provides numeric examples (register values are in hexadecimal
notation):
Table 4-3. Numeric Example
nc...
I
4.3.7 Special Programming Exceptions
The programming method described in 4.3.6 Programming the PLL does not
account for two possible exceptions. A value of 0 for N or L is meaningless when
used in the equations given. To account for these exceptions:
• A 0 value for N is interpreted exactly the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the source for
See 4.3.8 Base Clock Selector Circuit.
4.3.8 Base Clock Selector Circuit
cale Semiconductor,
Frees
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock,
CGMVCLK, as the source of the base clock, CGMOUT. The two input clocks go
through a transition control circuit that waits up to three CGMXCLK cycles and
three CGMVCLK cycles to change from one clock source to the other. During this
time, CGMOUT is held in stasis. The output of the transition control circuit is then
divided by two to correct the duty cycle. Therefore, the bus clock frequency, which
is one-half of the base clock frequency, is one-fourth the frequency of the selected
clock (CGMXCLK or CGMVCLK).
f
BUS
500 kHz 1 MHz 002 0 1B
1.25 MHz 1 MHz 005 0 45
2.0 MHz 1 MHz 008 0 70
2.5 MHz 1 MHz 00A 1 45
3.0 MHz 1 MHz 00C 1 53
4.0 MHz 1 MHz 010 1 70
5.0 MHz 1 MHz 014 2 46
7.0 MHz 1 MHz 01C 2 62
8.0 MHz 1 MHz 020 2 70
the base clock.
f
RCLK
NEL
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source if the PLL
is not turned on. The PLL cannot be turned off if the VCO clock is selected. The
PLL cannot be turned on or off simultaneously with the selection or deselection of
the VCO clock. The VCO clock also cannot be selected as the base clock source
if the factor L is programmed to a 0. This value would set up a condition
inconsistent with the operation of the PLL, so that the PLL would be disabled and
the crystal clock would be forced as the source of the base clock.
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
86 Clock Generator Module (CGM) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 87
4.3.9 CGM External Connections
nc...
I
Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Functional Description
In its typical configuration, the CGM requires external components. Five of these
are for the crystal oscillator and two or four are for the PLL.
The crystal oscillator is normally connected in a Pierce oscillator configuration, as
shown in Figure 4-2. Figure 4-2 shows only the logical representation of the
internal components and may not represent actual circuitry. The oscillator
configuration uses five components:
•Crystal, X
• Fixed capacitor, C
1
1
• Tuning capacitor, C2 (can also be a fixed capacitor)
• Feedback resistor, R
B
• Series resistor, RS
The series resistor (RS) is included in the diagram to follow strict Pierce oscillator
guidelines. Refer to the crystal manufacturer’s data for more information regarding
values for C1 and C2.
cale Semiconductor,
Frees
Figure 4-2 also shows the external components for the PLL:
• Bypass capacitor, C
BYP
• Filter network
Routing should be done with great care to minimize signal cross talk and noise.
SIMOSCEN
OSCENINSTOP
(FROM CONFIG)
CGMXCLK
OSC1
X1
RB
OSC2
RS
R
CF1
CGMXFC
F1
C
F2
V
SSA
V
CBYP
DDA
V
DD
C
1
Note: Filter network in box can be replaced with a single capacitor, but will degrade stability.
C
2
Figure 4-2. CGM External Connections
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Clock Generator Module (CGM) 87
For More Information On This Product,
Go to: www.freescale.com
Page 88
Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
4.4 I/O Signals
The following paragraphs describe the CGM I/O signals.
4.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
4.4.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
4.4.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase corrections. An
nc...
I
NOTE: To prevent noise problems, the filter network should be placed as close to the
external filter network is connected to this pin. (See Figure 4-2.)
CGMXFC pin as possible, with minimum routing distances and no routing of othe r
signals across the network.
4.4.4 PLL Analog Power Pin (V
is a power pin used by the analog portions of the PLL. Connect the V
V
DDA
to the same voltage potential as the V
NOTE: Route V
close as possible to the package.
4.4.5 PLL Analog Ground Pin (V
V
SSA
to the same voltage potential as the V
DDA
is a ground pin used by the analog portions of the PLL. Connect the V
)
DDA
carefully for maximum noise immunity and place bypass capacitors as
)
SSA
cale Semiconductor,
NOTE: Route V
close as possible to the package.
4.4.6 Oscillator Enable Signal (SIMOSCEN)
Frees
The SIMOSCEN signal comes from the system integration module (SIM) and
enables the oscillator and PLL.
4.4.7 Oscillator Enable in Stop Mode Bit (OSCENINSTOP)
OSCENINSTOP is a bit in the CONFIG2 register that enables the oscillator to
continue operating during stop mode. If this bit is set, the oscillator continues
running during stop mode. If this bit is not set (default), the oscillator is controlled
by the SIMOSCEN signal which will disable the oscillator during stop mode.
carefully for maximum noise immunity and place bypass capacitors as
SSA
DD
SS
pin.
pin.
DDA
SSA
pin
pin
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
88 Clock Generator Module (CGM) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 89
Freescale Semiconductor, Inc.
4.4.8 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the
crystal (f
shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not
represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and amplitude
of CGMXCLK can be unstable at start up.
4.4.9 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which
generates the MCU clocks. CGMOUT is a 50 percent duty cycle clock running at
twice the bus frequency. CGMOUT is software programmable to be either the
oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided
nc...
I
by two.
XCLK
) and comes directly from the crystal oscillator circuit. Figure 4-2
Clock Generator Module (CGM)
CGM Registers
4.4.10 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
4.5 CGM Registers
These registers control and monitor operation of the CGM:
• PLL control register (PCTL)
• PLL bandwidth control register (PBWC)
• PLL multiplier select register high (PMSH)
cale Semiconductor,
Frees
• PLL multiplier select register low (PMSL)
• PLL VCO range select register (PMRS)
Figure 4-3 is a summary of the CGM registers.
(See 4.5.1 PLL Control Register.)
(See 4.5.2 PLL Bandwidth Control Register.)
(See 4.5.3 PLL Multiplier Select Register High.)
(See 4.5.4 PLL Multiplier Select Register Low.)
(See 4.5.5 PLL VCO Range Select Register.)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Clock Generator Module (CGM) 89
For More Information On This Product,
Go to: www.freescale.com
Page 90
Clock Generator Module (CGM)
Addr.Register Name Bit 7654321Bit 0
PLL Control Register
$0036
PLL Bandwidth Control Reg-
$0037
PLL Multiplier Select High
$0038
$0039
nc...
I
$003A
$003B Reserved Register
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Register (PMSH)
PLL Multiplier Select Low
Register (PMSL)
PLL VCO Select Range
Register (PMRS)
(PCTL)
See page 90.
ister (PBWC)
See page 92.
See page 93.
See page 94.
See page 94.
is read-only.
cale Semiconductor,
4.5.1 PLL Control Register
Frees
The PLL control register (PCTL) contains the interrupt enable and flag bits, the
on/off switch, the base clock selector bit, and the VCO power-of-two range selector
bits.
Freescale Semiconductor, Inc.
Read:
Write:
Reset:00100000
Read:
Write:
Reset:00000000
Read:0000
Write:
Reset:00000000
Read:
Write:
Reset:01000000
Read:
Write:
Reset:01000000
Read:0000
Write:
Reset:00000001
PLLIE
AUTO
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
PLLF
LOCK
= Unimplemented R = Reserved
PLLON BCS R R VPR1 VPR0
ACQ
0000
MUL11 MUL10 MUL9 MUL8
RRRR
R
Figure 4-3. CGM I/O Register Summary
Address: $0036
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PLLIE
Write:
Reset:00100 0 00
PLLF
PLLON BCS R R VPR1 VPR0
= Unimplemented R = Reserved
Figure 4-4. PLL Control Register (PCTL)
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
90 Clock Generator Module (CGM) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 91
Freescale Semiconductor, Inc.
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request when the
LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL
bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads
as 0. Reset clears the PLLIE bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL Interrupt Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF generates an
interrupt request if the PLLIE bit also is set. PLLF always reads as 0 when the
AUTO bit in the PLL bandwidth control register (PBWC) is clear. Clear the PLLF
bit by reading the PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
nc...
I
NOTE: Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on
the PLL control register clears the PLLF bit.
Clock Generator Module (CGM)
CGM Registers
cale Semiconductor,
Frees
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK.
PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT
(BCS = 1). (See 4.3.8 Base Clock Selector Circuit.) Reset sets this bit so that
the loop can stabilize as the MCU is powering up.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output, CGMXCLK, or the
VCO clock, CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT
frequency is one-half the frequency of the selected clock. BCS cannot be set
while the PLLON bit is clear. After toggling BCS, it may take up to three
CGMXCLK and three CGMVCLK cycles to complete the transition from one
source clock to the other. During the transition, CGMOUT is held in stasis. (See
4.3.8 Base Clock Selector Circuit.) Reset clears the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
NOTE: PLLON and BCS have built-in protection that prevents the base clock selector
circuit from selecting the VCO clock as the source of the base clock if the PLL is
off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set
when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires
two writes to the PLL control register. (See 4.3.8 Base Clock Selector Circuit.).
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range multiplier
E that, in conjunction with L controls the hardware center-of-range frequency,
f
. VPR1:VPR0 cannot be written when the PLLON bit is set. Reset clears
VRS
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Clock Generator Module (CGM) 91
For More Information On This Product,
Go to: www.freescale.com
Page 92
Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
these bits. (See 4.3.3 PLL Circuits, 4.3.6 Programming the PLL, and 4.5.5
PLL VCO Range Select Register.)
Table 4-4. VPR1 and VPR0 Programming
NOTE: Verify that the value of the VPR1 and VPR0 bits in the PCTL register are
nc...
I
4.5.2 PLL Bandwidth Control Register
cale Semiconductor,
appropriate for the given reference and VCO clock frequencies before enabling the
PLL. See 4.3.6 Programming the PLL for detailed instructions on selecting the
proper value for these control bits.
The PLL bandwidth control register (PBWC):
• Selects automatic or manual (software-controlled) bandwidth control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in
• In manual operation, forces the PLL into acquisition or tracking mode
Address: $0037
Read:
Write:
Reset:00000000
Frees
VPR1 and VPR0 E
00 0 1
01 1 2
10
1. Do not program E to a value of 3.
acquisition or tracking mode
Bit 7654321Bit 0
AUTO
Figure 4-5. PLL Bandwidth Control Register (PBWC)
LOCK
ACQ
= Unimplemented R= Reserved
(1)
2
0000
VCO Power-of-Two
Range Multiplier
4
R
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control. When
initializing the PLL for manual operation (AUTO = 0), clear the ACQ
turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set when the
VCO clock, CGMVCLK, is locked (running at the programmed frequency).
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
92 Clock Generator Module (CGM) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
bit before
Page 93
Freescale Semiconductor, Inc.
When the AUTO bit is clear, LOCK reads as 0 and has no meaning. The write
one function of this bit is reserved for test, so this bit must always be written a 0.
Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ
— Acquisition Mode Bit
When the AUTO bit is set, ACQ
is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ
read/write bit that controls whether the PLL is in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written value from
manual operation is stored in a temporary location and is recovered when
manual operation resumes. Reset clears this bit, enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
nc...
I
4.5.3 PLL Multiplier Select Register High
Clock Generator Module (CGM)
CGM Registers
is a read-only bit that indicates whether the PLL
is a
cale Semiconductor,
Frees
The PLL multiplier select register high (PMSH) contains the programming
information for the high byte of the modulo feedback divider.
Address: $0038
Bit 7654321Bit 0
Read:0000
MUL11 MUL10 MUL9 MUL8
Write:
Reset:00000000
= Unimplemented
Figure 4-6. PLL Multiplier Select Register High (PMSH)
MUL11–MUL8 — Multiplier Select Bits
These read/write bits control the high byte of the modulo feedback divider that
selects the VCO frequency multiplier N. (See 4.3.3 PLL Circuits and 4.3.6
Programming the PLL.) A value of $0000 in the multiplier select registers
configures the modulo feedback divider the same as a value of $0001. Reset
initializes the registers to $0040 for a default multiply value of 64.
NOTE: The multiplier select bits have built-in protection such that they cannot be written
when the PLL is on (PLLON = 1).
PMSH[7:4] — Unimplemented Bits
These bits have no function and always read as 0s.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Clock Generator Module (CGM) 93
For More Information On This Product,
Go to: www.freescale.com
Page 94
Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
4.5.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming
information for the low byte of the modulo feedback divider.
Address: $0038
Read:
Write:
Reset:01000000
NOTE: For applications using 1–8 MHz reference frequencies this register must be
reprogrammed before enabling the PLL. The reset value of this register will ca use
nc...
I
applications using 1–8 MHz reference frequencies to become unstable if the PLL
is enabled without programming an appropriate value. The programmed value
must not allow the VCO clock to exceed 32 MHz. See 4.3.6 Programming the PLL
for detailed instructions on choosing the proper value for PMSL.
Bit 7654321Bit 0
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Figure 4-7. PLL Multiplier Select Register Low (PMSL)
MUL7–MUL0 — Multiplier Select Bits
These read/write bits control the low byte of the modulo feedback divider that
selects the VCO frequency multiplier, N. (See 4.3.3 PLL Circuits and
4.3.6 Programming the PLL.) MUL7–MUL0 cannot be written when the
PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers
configures the modulo feedback divider the same as a value of $0001. Reset
initializes the register to $40 for a default multiply value of 64.
NOTE: The multiplier select bits have built-in protection such that they cannot be written
when the PLL is on (PLLON = 1).
4.5.5 PLL VCO Range Select Register
cale Semiconductor,
The PLL VCO range select register (PMRS) contains the programming information
required for the hardware configuration of the VCO.
Address: $003A
Frees
Read:
Write:
Reset:01000000
Bit 7654321Bit 0
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Figure 4-8. PLL VCO Range Select Register (PMRS)
NOTE: Verify that the value of the PMRS register is appropriate for the given reference and
VCO clock frequencies before enabling the PLL. See 4.3.6 Programming the PLL
for detailed instructions on selecting the proper value for these control bits.
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
94 Clock Generator Module (CGM) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 95
Freescale Semiconductor, Inc.
VRS7–VRS0 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L
which, in conjunction with E (See 4.3.3 PLL Circuits, 4.3.6 Programming the
PLL, and 4.5.1 PLL Control Register.), controls the hardware center-of-range
frequency, f
PCTL is set. (See 4.3.7 Special Programming Exceptions.) A value of $00 in
the VCO range select register disables the PLL and clears the BCS bit in the
PLL control register (PCTL). (See 4.3.8 Base Clock Selector Circuit and
4.3.7 Special Programming Exceptions.). Reset initializes the register to $40
for a default range multiply value of 64.
NOTE: The VCO range select bits have built-in protection such that they cannot be written
when the PLL is on (PLLON = 1) and such that the VCO clock cannot be selected
as the source of the base clock (BCS = 1) if the VCO range select bits are all cle ar.
Clock Generator Module (CGM)
. VRS7–VRS0 cannot be written when the PLLON bit in the
VRS
Interrupts
nc...
I
4.6 Interrupts
cale Semiconductor,
Frees
The PLL VCO range select register must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL
can generate a CPU interrupt request every time the LOCK bit changes state. The
PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL.
PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled
or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and
PLLF reads as 0.
Software should read the LOCK bit after a PLL interrupt request to see if the
request was due to an entry into lock or an exit from lock. When the PLL enters
lock, the VCO clock, CGMVCLK, divided by two can be selected as the CGMOUT
source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock
frequency is corrupt, and appropriate precautions should be taken. If the
application is not frequency sensitive, interrupts should be disabled to prevent PLL
interrupt service routines from impeding software performance or from exceeding
stack limitations.
NOTE: Software can select the CGMVCLK divided by two as the CGMOUT source even
if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL
is locked before setting the BCS bit.
4.7 Special Modes
The WAIT instruction puts the MCU in low power-consumption standby modes.
4.7.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and PLLON bits
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Clock Generator Module (CGM) 95
For More Information On This Product,
Go to: www.freescale.com
Page 96
Clock Generator Module (CGM)
in the PLL control register (PCTL) to save power. Less power-sensitive
applications can disengage the PLL without turning it off, so that the PLL clock is
immediately available at WAIT exit. This would be the case also when the PLL is
to wake the MCU from wait mode, such as when the PLL is first enabled and
waiting for LOCK or LOCK is lost.
4.7.2 Stop Mode
If the OSCENINSTOP bit in the CONFIG2 register is cleared (default), then the
STOP instruction disables the CGM (oscillator and phase locked loop) and holds
low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT).
If the OSCENINSTOP bit in the CONFIG2 register is set, then the phase locked
loop is shut off but the oscillator will continue to operate in stop mode.
nc...
4.7.3 CGM During Break Interrupts
I
The system integration module (SIM) controls whether status bits in other modules
can be cleared during the break state. The BCFE bit in the SIM break flag control
register (SBFCR) enables software to clear status bits during the break state. (See
15.7.3 Break Flag Control Register.)
Freescale Semiconductor, Inc.
To allow software to clear status bits during a break interrupt, write a 1 to t he BCFE
bit. If a status bit is cleared during the break state, it remains cleared when the MCU
exits the break state.
To protect the PLLF bit during the break state, write a 0 to the BCFE bit. With BCFE
at 0 (its default state), software can read and write the PLL control register during
the break state without affecting the PLLF bit.
4.8 Acquisition/Lock Time Specifications
cale Semiconductor,
4.8.1 Acquisition/Lock Time Definitions
Frees
The acquisition and lock times of the PLL are, in many applications, the most
critical PLL design parameters. Proper design and use of the PLL ensures the
highest stability and lowest acquisition/lock times.
Typical control systems refer to the acquisition time or lock time as the reaction
time, within specified tolerances, of the system to a step input. In a PLL, the step
input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance
is usually specified as a percent of the step input or when the output settles to the
desired value plus or minus a percent of the frequency change. Therefore, the
reaction time is constant in this definition, regardless of the size of the step input.
For example, consider a system with a 5 percent acquisition time tolerance. If a
command instructs the system to change from 0 Hz to 1 MHz, the acquisition time
is the time taken for the frequency to reach 1 MHz ±50 kHz. Fifty kHz = 5% of the
1-MHz step input. If the system is operating at 1 MHz and suffers a –100-kHz noise
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
96 Clock Generator Module (CGM) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 97
Freescale Semiconductor, Inc.
hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz ±5kHz.
Five kHz = 5% of the 100-kHz step input.
Other systems refer to acquisition and lock times as the time the system takes to
reduce the error between the actual output and the desired output to within
specified tolerances. Therefore, the acquisition or lock time varies according to the
original error in the output. Minor errors may not even be registered. Typical PLL
applications prefer to use this definition because the system requires the output
frequency to be within a certain tolerance of the desired frequency regardless of
the size of the initial error.
4.8.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while still
providing the highest possible stability. These reaction times are not constant,
nc...
I
cale Semiconductor,
Frees
however. Many factors directly and indirectly affect the acquisition time.
The most critical parameter which affects the reaction times of the PLL is the
reference frequency, f
and controls how often the PLL makes corrections. For stability, the corrections
must be small compared to the desired frequency, so several corrections are
required to reduce the frequency error. Therefore, the slower the reference the
longer it takes to make these corrections. This parameter is under user control via
the choice of crystal frequency f
Programming the PLL.)
Another critical parameter is the external filter network. The PLL modifies the
voltage on the VCO by adding or subtracting charge from capacitors in this
network. Therefore, the rate at which the voltage changes for a given frequency
error (thus change in charge) is proportional to the capacitance. The size of the
capacitor also is related to the stability of the PLL. If the capacitor is too small, the
PLL cannot make small enough adjustments to the voltage and the system cannot
lock. If the capacitor is too large, the PLL may not be able to adjust the voltage in
a reasonable time. (See 4.8.3 Choosing a Filter.)
Also important is the operating voltage potential applied to V
potential alters the characteristics of the PLL. A fixed value is best. Variable
supplies, such as batteries, are acceptable if they vary within a known range at very
slow speeds. Noise on the power supply is not acceptable, because it causes small
frequency errors which continually change the acquisition time of the PLL.
Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
. This frequency is the input to the phase detector
RCLK
. (See 4.3.3 PLL Circuits and 4.3.6
XCLK
. The power supply
DDA
Temperature and processing also can affect acquisition time because the electrical
characteristics of the PLL change. The part operates as specified as long as these
influences stay within the specified limits. External factors, however, can cause
drastic changes in the operation of the PLL. These factors include noise injected
into the PLL through the filter capacitor, filter capacitor leaka ge, stray impedances
on the circuit board, and even humidity or circuit board contamination.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Clock Generator Module (CGM) 97
For More Information On This Product,
Go to: www.freescale.com
Page 98
Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
4.8.3 Choosing a Filter
As described in 4.8.2 Parametric Influences on Reaction Time, the external filter
network is critical to the stability and reaction time of the PLL. The PLL is also
dependent on reference frequency and supply voltage.
Figure 4-9 shows two types of filter circuits. In low-cost applications, where stability
and reaction time of the PLL are not critical, the three component filter network
shown in Figure 4-9 (B) can be replaced by a single capacitor, C
shown in Figure 4-9 (A). Refer to Table 4-5 for recommended filter components at
various reference frequencies. For reference frequencies between the values
listed in the table, extrapolate to the nearest common capacitor value. In general,
a slightly larger capacitor provides more stability at the expense of increased lock
time.
, as shown in
F
nc...
I
cale Semiconductor,
Frees
CGMXFC
C
F
V
SSA
(A) (B)
CGMXFC
R
F1
C
F1
C
F2
V
SSA
Figure 4-9. PLL Filter
Table 4-5. Example Filter Component Values
f
RCLK
1 MHz 8.2 nF 820 pF 2k 18 nF
2 MHz 4.7 nF 470 pF 2k 6.8 nF
3 MHz 3.3 nF 330 pF 2k 5.6 nF
4 MHz 2.2 nF 220 pF 2k 4.7 nF
C
F1
C
F2
R
F1
C
F
5 MHz 1.8 nF 180 pF 2k 3.9 nF
6 MHz 1.5 nF 150 pF 2k 3.3 nF
7 MHz 1.2 nF 120 pF 2k 2.7 nF
8 MHz 1 nF 100 pF 2k 2.2 nF
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
98 Clock Generator Module (CGM) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Page 99
Data Sheet — MC68HC908GZ60
5.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2. The
configuration registers enable or disable these options:
nc...
I
Freescale Semiconductor, Inc.
Section 5. Configuration Register (CONFIG)
• Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles)
• COP timeout period (2
•STOP instruction
• Computer operating properly module (COP)
• Low-voltage inhibit (LVI) module control and voltage trip point selection
• Enable/disable the oscillator (OSC) during stop mode
• Enable/disable an extra divide by 128 prescaler in timebase module
18
– 24 or 213 – 24 COPCLK cycles)
5.2 Functional Description
cale Semiconductor,
NOTE: On a FLASH device, the options except MSCANEN and LVI5OR3 are one-time
Frees
• Enable for Motorola scalable controller area network (MSCAN)
• Selectable clockout (MCLK) feature with divide by 1, 2, and 4 of the bus or
crystal frequency
• Timebase clock select
The configuration registers are used in the initialization of various options. The
configuration registers can be written once after each reset. All of the configuration
register bits are cleared during reset. Since the various options a ffect the operation
of the microcontroller unit (MCU), it is recommended that these registers be written
immediately after reset. The configuration registers are located at $001E and
$001F and may be read at anytime.
writable by the user after each reset. These bits are one-time writable by the user
only after each POR (power-on reset). The CONFIG registers are not in the FLASH
memory but are special registers containing one-time writable latches after each
reset. Upon a reset, the CONFIG registers default to predetermined settings as
shown in Figure 5-1 and Figure 5-2.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Configuration Register (CONFIG) 99
For More Information On This Product,
Go to: www.freescale.com
Page 100
Configuration Register (CONFIG)
Address: $001E
Note: MSCANEN is only reset via POR (power-on reset).
MCLKSEL — MCLK Source Select Bit
nc...
I
MCLK1 and MCLK0 — MCLK Output Select Bits
Freescale Semiconductor, Inc.
Read: 0
Write:
Reset:0000See note0 0 1
1 = Crystal frequency
0 = Bus frequency
Setting the MCLK1 and MCLK0 bits enables the PTD0/SS
MCLK output clock. Once configured for MCLK, the PTD data direction register
for PTD0 is used to enable and disable the MCLK output.
MCLK options.
Bit 76543 2 1 Bit 0
MCLKSEL MCLK1 MCLK0 MSCANEN TBMCLKSEL OSCENINSTOP SCIBDSRC
= Unimplemented
Figure 5-1. Configuration Register 2 (CONFIG2)
pin to be used as a
See
Table 5-1
for
cale Semiconductor,
Frees
Table 5-1. MCLK Output Select
MCLK1 MCLK0 MCLK Frequency
0 0 MCLK not enabled
0 1 Clock
1 0 Clock divided by 2
1 1 Clock divided by 4
MSCANEN— MSCAN08 Enable Bit
Setting the MSCANEN
to use the PTC0/PTC1 pins.
(MSCAN08) for a more detailed description of the MSCAN08 operation.
1 = Enables MSCAN08 module
0 = Disables the MSCAN08 module
NOTE: The MSCANEN bit is cleared by a power-on reset (POR) only. Other resets will
leave this bit unaffected.
TBMCLKSEL— Timebase Clock Select Bit
TBMCLKSEL
Setting this bit enables the extra prescaler and clearing this bit disables it.
Section 17. Timebase Module (TBM) for a more detailed description of the
external clock operation.
1 = Enables extra divide-by-128 prescaler in timebase module
0 = Disables extra divide-by-128 prescaler in timebase module
enables an extra divide-by-128 prescaler in the timebase m odule.
enables the MSCAN08 module and allows the MSCAN08
See Section 12. MSCAN08 Controller
See
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
100 Configuration Register (CONFIG) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Loading...