Datasheet MC68HC908AZ60AMFU, MC68HC908AZ60AVFU, MC68HC908AS60AVFU, MC68HC908AS60AVFN, MC68HC908AS60ACFN Datasheet (Motorola)

MC68HC908AZ60A/D

MC68HC908AZ60A

REV 2.0

MC68HC908AS60A

Technical Data

HCMOS
Microcontroller Unit

M68HC08M68H

C08M68HC08M

68HC08M68HC

MC68HC908AZ60A
MC68HC908AS60A

Technical Data — Rev 2.0

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herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customer’s technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
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Motorola and are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc. © Motorola, Inc., 2001

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA 3

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Technical Data — MC68HC908AZ60A

Section 1. General Description . . . . . . . . . . . . . . . . . . . .31

Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Section 3. RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Section 4. FLASH-1 Memory . . . . . . . . . . . . . . . . . . . . . . 65

Section 5. FLASH-2 Memory . . . . . . . . . . . . . . . . . . . . . . 77

Section 6. EEPROM-1 Memory. . . . . . . . . . . . . . . . . . . . .89

Section 7. EEPROM-2 Memory. . . . . . . . . . . . . . . . . . . . 109

Section 8. Central Processor Unit (CPU) . . . . . . . . . . . 129

Section 9. System Integration Module (SIM) . . . . . . . .147

List of Paragraphs

Section 10. Clock Generator Module (CGM) . . . . . . . . . 169

Section 11. Configuration Register (CONFIG-1). . . . . . 197

Section 12. Configuration Register (CONFIG-2). . . . . . 201

Section 13. Break Module (BRK) . . . . . . . . . . . . . . . . . . 203

Section 14. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 209

Section 15. Computer Operating Properly (COP) . . . .223

Section 16. Low Voltage Inhibit (LVI) . . . . . . . . . . . . . . 229

Section 17. External Interrupt Module (IRQ). . . . . . . . . 235

Section 18. Serial Communications Interface (SCI). . . 243

Section 19. Serial Peripheral Interface (SPI). . . . . . . . . 285

Section 20. Timer Interface Module B (TIMB) . . . . . . . . 317

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List of Paragraphs

Section 21. Programmable Interrupt Timer (PIT) . . . . . 343

Section 22. Input/Output Ports . . . . . . . . . . . . . . . . . . . 353

Section 23. MSCAN Controller (MSCAN08) . . . . . . . . . 379

Section 24. Keyboard Module (KBD). . . . . . . . . . . . . . . 431

Section 25. Timer Interface Module A (TIMA) . . . . . . . . 441

Section 26. Analog-to-Digital Converter (ADC) . . . . . .471

Section 27. Byte Data Link Controller (BDLC) . . . . . . . 483

Section 28. Electrical Specifications. . . . . . . . . . . . . . . 529

Section 29. MC68HC908AS60 and MC68HC908AZ60 . 553

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Technical Data — MC68HC908AZ60A

Section 1. General Description

1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

1.6 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table of Contents

Section 2. Memory Map

2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

2.3 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

2.4 Additional Status and Control Registers. . . . . . . . . . . . . . . . . .58

2.5 Vector Addresses and Priority . . . . . . . . . . . . . . . . . . . . . . . . .61

Section 3. RAM

3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Section 4. FLASH-1 Memory

4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

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4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

4.4 FLASH-1 Control and Block Protect Registers . . . . . . . . . . . . .67

4.5 FLASH-1 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.6 FLASH-1 Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . .71

4.7 FLASH-1 Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . .72

4.8 FLASH-1 Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . .73

4.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Section 5. FLASH-2 Memory

5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

5.4 FLASH-2 Control and Block Protect Registers . . . . . . . . . . . . .79

5.5 FLASH-2 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

5.6 FLASH-2 Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . .83

5.7 FLASH-2 Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . .84

5.8 FLASH-2 Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . .85

5.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Section 6. EEPROM-1 Memory

6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

6.4 EEPROM-1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . .91

6.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

6.6 EEPROM-1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . .99

6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

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Section 7. EEPROM-2 Memory

7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

7.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

7.4 EEPROM-2 Register Summary . . . . . . . . . . . . . . . . . . . . . . .111

7.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

7.6 EEPROM-2 Register Descriptions . . . . . . . . . . . . . . . . . . . . .119

7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Section 8. Central Processor Unit (CPU)

8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

8.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

8.4 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

8.5 Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .135

8.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

8.7 CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .136

8.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

8.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Section 9. System Integration Module (SIM)

9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

9.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .150

9.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .152

9.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

9.6 Program Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . .157

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9.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

9.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

Section 10. Clock Generator Module (CGM)

10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

10.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

10.6 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

10.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

10.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

10.9 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .190

10.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .190

Section 11. Configuration Register (CONFIG-1)

11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

Section 12. Configuration Register (CONFIG-2)

12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

12.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

Section 13. Break Module (BRK)

13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

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13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

13.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

13.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Section 14. Monitor ROM (MON)

14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Section 15. Computer Operating Properly (COP)

15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

15.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

15.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

15.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

15.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

15.9 COP Module During Break Interrupts. . . . . . . . . . . . . . . . . . .228

Section 16. Low Voltage Inhibit (LVI)

16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

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16.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

16.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

16.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234

Section 17. External Interrupt Module (IRQ)

17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

17.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

17.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .240

17.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .240

Section 18. Serial Communications Interface (SCI)

18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

18.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263

18.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .264

18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

18.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265

Section 19. Serial Peripheral Interface (SPI)

19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286

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19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286

19.4 Pin Name and Register Name Conventions. . . . . . . . . . . . . .287

19.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288

19.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

19.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297

19.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301

19.9 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . .302

19.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304

19.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305

19.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .305

19.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306

19.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

Section 20. Timer Interface Module B (TIMB)

20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317

20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318

20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318

20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321

20.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328

20.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329

20.7 TIMB During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .329

20.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330

20.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331

Section 21. Programmable Interrupt Timer (PIT)

21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343

21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343

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21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344

21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344

21.5 PIT Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346

21.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346

21.7 PIT During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .347

21.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347

Section 22. Input/Output Ports

22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353

22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354

22.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355

22.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357

22.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360

22.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363

22.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366

22.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369

22.9 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373

22.10 Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376

Section 23. MSCAN Controller (MSCAN08)

23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379

23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380

23.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381

23.4 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382

23.5 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383

23.6 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .388

23.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392

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23.8 Protocol Violation Protection. . . . . . . . . . . . . . . . . . . . . . . . . .394

23.9 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394

23.10 Timer Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398

23.11 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399

23.12 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402

23.13 Programmer’s Model of Message Storage . . . . . . . . . . . . . . .403

23.14 Programmer’s Model of Control Registers . . . . . . . . . . . . . . .408

Section 24. Keyboard Module (KBD)

24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431

24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431

24.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .432

24.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .432

24.5 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .435

24.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436

24.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .436

24.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437

Section 25. Timer Interface Module A (TIMA)

25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441

25.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442

25.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442

25.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .445

25.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .454

25.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .455

25.7 TIMA During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .455

25.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .456

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25.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457

Section 26. Analog-to-Digital Converter (ADC)

26.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .471

26.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .472

26.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .472

26.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .472

26.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .475

26.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .475

26.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .476

26.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477

Section 27. Byte Data Link Controller (BDLC)

27.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .483

27.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .484

27.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .484

27.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .485

27.5 BDLC MUX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .490

27.6 BDLC Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .506

27.7 BDLC CPU Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .512

27.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .527

Section 28. Electrical Specifications

28.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .529

28.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530

28.3 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .547

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Section 29. MC68HC908AS60 and MC68HC908AZ60

29.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .553

29.2 Changes from the MC68HC908AS60 and MC68HC908AZ60

(non-A suffix devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .553

Revision History

Major Changes Between Revision 2.0 and Revision 1.0 . . . .559

Major Changes Between Revision 1.0 and Revision 0.0 . . . .559

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Technical Data — MC68HC908AZ60A

Figure Title Page

1-1 MCU Block Diagram for the MC68HC908AZ60A (64-Pin QFP)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

1-2 MCU Block Diagram for the MC68HC908AS60A (64-Pin QFP

and 52-pin PLCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

1-3 MC68HC908AZ60A (64-Pin QFP) . . . . . . . . . . . . . . . . . . . . . .37

1-4 MC68HC908AS60A (64-Pin QFP) . . . . . . . . . . . . . . . . . . . . . .38

1-5 MC68HC908AS60A (52-Pin PLCC) . . . . . . . . . . . . . . . . . . . . .39

1-6 Power supply bypassing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

2-1 Memory Map (Continued). . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

2-2 I/O Data, Status and Control Registers . . . . . . . . . . . . . . . . . .54

2-3 Additional Status and Control Registers. . . . . . . . . . . . . . . . . .59

4-1 FLASH-1 Control Register (FL1CR) . . . . . . . . . . . . . . . . . . . . .67

4-2 FLASH-1 Block Protect Register (FL1BPR) . . . . . . . . . . . . . . .68

4-3 FLASH-1 Block Protect Start Address . . . . . . . . . . . . . . . . . . .69

4-4 FLASH Programming Algorithm Flowchart. . . . . . . . . . . . . . . .75

5-1 FLASH-2 Control Register (FL2CR) . . . . . . . . . . . . . . . . . . . . .79

5-2 FLASH-2 Block Protect Register (FL2BPR) . . . . . . . . . . . . . . .80

5-3 FLASH-2 Block Protect Start Address . . . . . . . . . . . . . . . . . . .81

5-4 FLASH Programming Algorithm Flowchart. . . . . . . . . . . . . . . .87

6-1 EEPROM-1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . .91

6-2 EEPROM-1 Control Register (EE1CR). . . . . . . . . . . . . . . . . . .99

6-3 EEPROM-1 Array Configuration Register (EE1ACR). . . . . . .101

6-4 EEPROM-1 Nonvolatile Register (EE1NVR) . . . . . . . . . . . . .103

6-5 EE1DIV Divider High Register (EE1DIVH) . . . . . . . . . . . . . . .104

6-6 EE1DIV Divider Low Register (EE1DIVL). . . . . . . . . . . . . . . .104

6-7 EEPROM-1 Divider Non-Volatile Register High (EE1DIVHNVR))

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

6-8 EEPROM-1 Divider Non-Volatile Register Low (EE1DIVLNVR)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

List of Figures

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List of Figures

7-1 EEPROM-2 Register Summary . . . . . . . . . . . . . . . . . . . . . . .111

7-2 EEPROM-2 Control Register (EE2CR). . . . . . . . . . . . . . . . . .119

7-3 EEPROM-2 Array Configuration Register (EE2ACR). . . . . . .121

7-4 EEPROM-2 Nonvolatile Register (EE2NVR) . . . . . . . . . . . . .123

7-5 EE2DIV Divider High Register (EE2DIVH) . . . . . . . . . . . . . . .124

7-6 EE2DIV Divider Low Register (EE2DIVL). . . . . . . . . . . . . . . .124

7-7 EEPROM-2 Divider Non-Volatile Register High (EE2DIVHNVR))

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

7-8 EEPROM-2 Divider Non-Volatile Register Low (EE2DIVLNVR)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

8-1 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

8-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

8-3 Index register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

8-4 Stack pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

8-5 Program counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

8-6 Condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .133

9-1 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

9-2 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .149

9-3 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

9-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

9-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

9-6 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

9-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

9-8 Interrupt Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

9-9 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

9-10 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

9-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . .161

9-12 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

9-13 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . .163

9-14 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . .164

9-15 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

9-16 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . .165

9-17 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .166

9-18 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . .167

9-19 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .168

10-1 CGM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

10-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

10-3 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . .181

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List of Figures

10-4 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . .183

10-5 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . .185

10-6 PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . . . .187

11-1 Configuration Register (CONFIG-1) . . . . . . . . . . . . . . . . . . . .198

12-1 Configuration Register (CONFIG-2) . . . . . . . . . . . . . . . . . . . .201

13-1 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .204

13-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

13-3 Break Status and Control Register (BSCR) . . . . . . . . . . . . . .207

13-4 Break Address Registers (BRKH and BRKL) . . . . . . . . . . . . .208

14-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

14-2 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

14-3 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .213

14-4 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

14-5 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

14-6 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .220

15-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

15-2 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .227

16-1 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .231

16-2 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .232

16-3 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . .233

17-1 IRQ Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

17-2 IRQ Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

17-3 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .240

18-1 SCI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .246

18-2 SCI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .247

18-3 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

18-4 SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

18-5 SCI Transmitter I/O Register Summary . . . . . . . . . . . . . . . . .251

18-6 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . .254

18-7 SCI I/O Receiver Register Summary . . . . . . . . . . . . . . . . . . .255

18-8 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

18-9 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

18-10 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260

18-11 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . .266

18-12 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . .269

18-13 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . .272

18-14 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . .274

18-15 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276

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List of Figures

18-16 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . .278

18-17 SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .279

18-18 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . .279

19-1 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .289

19-2 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . .290

19-3 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . .293

19-4 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . .294

19-5 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . .296

19-6 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . .298

19-7 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . .299

19-8 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . .302

19-9 SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . . . .303

19-10 CPHA/SS

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308

19-11 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . .310

19-12 SPI Status and Control Register (SPSCR). . . . . . . . . . . . . . .313

19-13 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .316

20-1 TIMB Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319

20-2 TIMB I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .320

20-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .325

20-4 TIMB Status and Control Register (TBSC). . . . . . . . . . . . . . .331

20-5 TIMB Counter Registers (TBCNTH and TBCNTL) . . . . . . . . .334

20-6 TIMB Counter Modulo Registers (TBMODH and TBMODL) . 335
20-7 TIMB Channel Status and Control Registers (TBSC0–TBSC1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336

20-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340

20-9 TIMB Channel Registers (TBCH0H/L–TBCH1H/L) . . . . . . . .341

21-1 PIT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344

21-2 PIT I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .345

21-3 PIT Status and Control Register (PSC) . . . . . . . . . . . . . . . . .348

21-4 PIT Counter Registers (PCNTH–PCNTL). . . . . . . . . . . . . . . .350

21-5 PIT Counter Modulo Registers (PMODH–PMODL) . . . . . . . .351

22-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .354

22-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .355

22-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .355

22-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356

22-5 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .357

22-6 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .358

22-7 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359

Technical Data MC68HC908AZ60A — Rev 2.0

22 List of Figures MOTOROLA

List of Figures

22-8 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .360

22-9 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . .361

22-10 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362

22-11 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .363

22-12 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . .364

22-13 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365

22-14 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .366

22-15 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . .368

22-16 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369

22-17 Port F Data Register (PTF). . . . . . . . . . . . . . . . . . . . . . . . . . .370

22-18 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . .371

22-19 Port F I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372

22-20 Port G Data Register (PTG) . . . . . . . . . . . . . . . . . . . . . . . . . .373

22-21 Data Direction Register G (DDRG). . . . . . . . . . . . . . . . . . . . .374

22-22 Port G I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374

22-23 Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . .376

22-24 Data Direction Register H (DDRH) . . . . . . . . . . . . . . . . . . . . .377

22-25 Port H I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377

23-1 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382

23-2 User Model for Message Buffer Organization. . . . . . . . . . . . .386

23-3 Single 32-Bit Maskable Identifier Acceptance Filter . . . . . . . .389

23-4 Dual 16-Bit Maskable Acceptance Filters . . . . . . . . . . . . . . . .390

23-5 Quadruple 8-Bit Maskable Acceptance Filters . . . . . . . . . . . .391

23-6 Sleep Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . . . .396

23-7 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399

23-8 Segments within the Bit Time . . . . . . . . . . . . . . . . . . . . . . . . .401

23-9 MSCAN08 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . .402

23-10 Message Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . .403

23-11 Receive/Transmit Message Buffer Extended Identifier (IDRn)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405

23-12 Standard Identifier Mapping . . . . . . . . . . . . . . . . . . . . . . . . . .406

23-13 Transmit Buffer Priority Register (TBPR) . . . . . . . . . . . . . . . .408

23-14 MSCAN08 Control Register Structure . . . . . . . . . . . . . . . . . .409

23-15 Module Control Register 0 (CMCR0) . . . . . . . . . . . . . . . . . . .411

23-16 Module Control Register (CMCR1). . . . . . . . . . . . . . . . . . . . .413

23-17 Bus Timing Register 0 (CBTR0) . . . . . . . . . . . . . . . . . . . . . . .414

23-18 Bus Timing Register 1 (CBTR1) . . . . . . . . . . . . . . . . . . . . . . .415

23-19 Receiver Flag Register (CRFLG) . . . . . . . . . . . . . . . . . . . . . .417

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA List of Figures 23

List of Figures

23-20 Receiver Interrupt Enable Register (CRIER) . . . . . . . . . . . . .420

23-21 Transmitter Flag Register (CTFLG) . . . . . . . . . . . . . . . . . . . .421

23-22 Transmitter Control Register (CTCR) . . . . . . . . . . . . . . . . . . .423

23-23 Identifier Acceptance Control Register (CIDAC). . . . . . . . . . .424

23-24 Receiver Error Counter (CRXERR) . . . . . . . . . . . . . . . . . . . .425

23-25 Transmit Error Counter (CTXERR). . . . . . . . . . . . . . . . . . . . .426

23-26 Identifier Acceptance Registers (CIDAR0–CIDAR3) . . . . . . .427

23-27 Identifier Mask Registers (CIDMR0–CIDMR3) . . . . . . . . . . . .428

24-1 Keyboard Module Block Diagram . . . . . . . . . . . . . . . . . . . .433

24-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .433

24-3 Keyboard Status and Control Register (KBSCR) . . . . . . . . . .437

24-4 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . .438

25-1 TIMA Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443

25-2 TIMA I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .444

25-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .450

25-4 TIMA Status and Control Register (TASC). . . . . . . . . . . . . . .457

25-5 TIMA Counter Registers (TACNTH and TACNTL) . . . . . . . . .460

25-6 TIMA Counter Modulo Registers (TAMODH and TAMODL) . 461
25-7 TIMA Channel Status and Control Registers (TASC0–TASC5)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .462

25-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467

25-9 TIMA Channel Registers (TACH0H/L–TACH5H/L) . . . . . . . .468

26-1 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .473

26-2 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . .477

26-3 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . .480

26-4 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . .480

27-1 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .486

27-2 BDLC Operating Modes State Diagram . . . . . . . . . . . . . . . . .487

27-3 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .490

27-4 BDLC Rx Digital Filter Block Diagram . . . . . . . . . . . . . . . . . .491

27-5 J1850 Bus Message Format (VPW) . . . . . . . . . . . . . . . . . . . .493

27-6 J1850 VPW Symbols with Nominal Symbol Times. . . . . . . . .498

27-7 J1850 VPW Received Passive Symbol Times . . . . . . . . . . . .501

27-8 J1850 VPW Received Passive EOF and IFS Symbol Times .502

27-9 J1850 VPW Received Active Symbol Times . . . . . . . . . . . . .503

27-10 J1850 VPW Received BREAK Symbol Times . . . . . . . . . . . .504

27-11 J1850 VPW Bitwise Arbitrations . . . . . . . . . . . . . . . . . . . . . . .505

27-12 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .506

Technical Data MC68HC908AZ60A — Rev 2.0

24 List of Figures MOTOROLA

List of Figures

27-13 BDLC Protocol Handler Outline . . . . . . . . . . . . . . . . . . . . . . .507

27-14 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .512

27-15 BDLC Analog and Roundtrip Delay Register (BARD) . . . . . .513

27-16 BDLC Control Register 1 (BCR1) . . . . . . . . . . . . . . . . . . . . . .514

27-17 BDLC Control Register 2 (BCR2) . . . . . . . . . . . . . . . . . . . . . .517

27-18 Types of In-Frame Response (IFR) . . . . . . . . . . . . . . . . . . . .520

27-19 BDLC State Vector Register (BSVR) . . . . . . . . . . . . . . . . . . .524

27-20 BDLC Data Register (BDR) . . . . . . . . . . . . . . . . . . . . . . . . . .526

28-1 SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .537

28-2 SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .538

28-3 BDLC Variable Pulse Width Modulation (VPW) Symbol Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .545

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA List of Figures 25

List of Figures

Technical Data MC68HC908AZ60A — Rev 2.0

26 List of Figures MOTOROLA

Technical Data — MC68HC908AZ60A

Table Title Page

1-1 External Pins Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

1-3 Clock Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

1-2 Clock Signal Naming Conventions . . . . . . . . . . . . . . . . . . . . . .47

1-4 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

6-1 EEPROM-1 Array Address Blocks . . . . . . . . . . . . . . . . . . . . . .94

6-2 Example Selective Bit Programming Description . . . . . . . . . . .95

6-3 EEPROM-1 Program/Erase Mode Select. . . . . . . . . . . . . . . . .99

6-4 EEPROM-1 Block Protect and Security Summary . . . . . . . . .102

7-1 EEPROM-2 Array Address Blocks . . . . . . . . . . . . . . . . . . . . .114

7-2 Example Selective Bit Programming Description . . . . . . . . . .115

7-3 EEPROM-2 Program/Erase Mode Select. . . . . . . . . . . . . . . .120

7-4 EEPROM-2 Block Protect and Security Summary . . . . . . . . .122

8-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

8-2 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

9-1 I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . .150

9-2 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . .150

9-3 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

10-1 I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . .173

10-2 Variable Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

10-3 VCO Frequency Multiplier (N) Selection. . . . . . . . . . . . . . . . .188

13-1 I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . .205

14-1 Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

14-2 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

14-3 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .215

14-4 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .216

14-5 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .216

14-6 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .217

14-7 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .217

List of Tables

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA List of Tables 27

List of Tables

14-8 RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . .218

14-9 MC68HC908AS60A Monitor Baud Rate Selection. . . . . . . . .218

14-10 MC68HC908AZ60A Monitor Baud Rate Selection . . . . . . . .219

16-1 LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

17-1 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .237

18-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

18-2 SCI I/O Register Address Summary. . . . . . . . . . . . . . . . . . . .247

18-3 SCI Transmitter I/O Address Summary . . . . . . . . . . . . . . . . .251

18-4 SCI Receiver I/O Address Summary . . . . . . . . . . . . . . . . . . .255

18-5 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

18-6 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

18-7 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

18-8 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .268

18-9 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . .280

18-10 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .280

18-11 SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . .281

19-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

19-2 I/O Register Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

19-3 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .288

19-4 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301

19-5 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

19-6 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . .315

20-1 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333

20-2 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .339

21-1 PIT I/O Register Address Summary . . . . . . . . . . . . . . . . . . . .345

21-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349

22-1 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357

22-2 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359

22-3 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362

22-4 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365

22-5 Port E Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369

22-6 Port F Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372

22-7 Port G Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375

22-8 Port H Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378

23-1 MSCAN08 Interrupt Vector Addresses. . . . . . . . . . . . . . . . . .393

23-2 MSCAN08 vs CPU operating modes . . . . . . . . . . . . . . . . . . .395

23-3 Time segment syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401

23-4 CAN Standard Compliant Bit Time Segment Settings . . . . . .402

Technical Data MC68HC908AZ60A — Rev 2.0

28 List of Tables MOTOROLA

List of Tables

23-5 Data Length Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407

23-6 Synchronization Jump Width . . . . . . . . . . . . . . . . . . . . . . . . .414

23-7 Baud Rate Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415

23-8 Time Segment Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416

23-9 Identifier Acceptance Mode Settings . . . . . . . . . . . . . . . . . . .424

23-10 Identifier Acceptance Hit Indication . . . . . . . . . . . . . . . . . . . .425

24-1 I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . .433

25-1 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .459

25-2 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .466

26-1 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478

26-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .481

27-1 BDLC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .486

27-2 BDLC J1850 Bus Error Summary. . . . . . . . . . . . . . . . . . . . . .511

27-3 BDLC Transceiver Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . .514

27-4 BDLC Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .516

27-5 BDLC Transmit In-Frame Response Control Bit Priority Encoding

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .519

27-6 BDLC Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .525

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA List of Tables 29

List of Tables

Technical Data MC68HC908AZ60A — Rev 2.0

30 List of Tables MOTOROLA

Technical Data — MC68HC908AZ60A

1.1 Contents

1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

1.5.1 Power Supply Pins (V

1.5.2 Oscillator Pins (OSC1 and OSC2). . . . . . . . . . . . . . . . . . .41

1.5.3 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . .41

1.5.4 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . .41

1.5.5 Analog Power Supply Pin (V

1.5.6 Analog Ground Pin (V

1.5.7 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . .41

1.5.8 ADC Analog Power Supply Pin (VDDAREF) . . . . . . . . . .42

1.5.9 ADC Analog Ground Pin (AVSS/VREFL) . . . . . . . . . . . . .42

1.5.10 ADC Reference High Voltage Pin (VREFH) . . . . . . . . . . .42

1.5.11 Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . .42

1.5.12 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) . . . . . . . . . . . .42

1.5.13 Port C I/O Pins (PTC5–PTC0) . . . . . . . . . . . . . . . . . . . . . .42

1.5.14 Port D I/O Pins (PTD7–PTD0/ATD8) . . . . . . . . . . . . . . . . .43

1.5.15 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) . . . . . . . . . . . .43

1.5.16 Port F I/O Pins (PTF6–PTF0/TACH2). . . . . . . . . . . . . . . . .43

1.5.17 Port G I/O Pins (PTG2/KBD2–PTG0/KBD0) . . . . . . . . . . .43

1.5.18 Port H I/O Pins (PTH1/KBD4–PTH0/KBD3). . . . . . . . . . . .44

1.5.19 CAN Transmit Pin (CANTx) . . . . . . . . . . . . . . . . . . . . . . . .44

1.5.20 CAN Receive Pin (CANRx). . . . . . . . . . . . . . . . . . . . . . . . .44

1.5.21 BDLC Transmit Pin (BDTxD) . . . . . . . . . . . . . . . . . . . . . . .44

1.5.22 BDLC Receive Pin (BDRxD) . . . . . . . . . . . . . . . . . . . . . . .44

Section 1. General Description

and VSS) . . . . . . . . . . . . . . . . . .40

DD

) . . . . . . . . . . . . . . . . . . .41

DDA

). . . . . . . . . . . . . . . . . . . . . . . . .41

SSA

1.6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

1.6.1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA General Description 31

General Description

1.2 Introduction

The MC68HC908AS60A and MC68HC908AZ60A are members of the
low-cost, high-performance M68HC08 Family of 8-bit microcontroller
units (MCUs). The M68HC08 Family is based on the customer-specified
integrated circuit (CSIC) design strategy. All MCUs in the family use the
enhanced M68HC08 central processor unit (CPU08) and are available
with a variety of modules, memory sizes and types, and package types.

These parts are designed to emulate the MC68HC08ASxx and
MC68HC08AZxx automotive families and may offer extra features which
are not available on those devices. It is the user’s responsibility to ensure
compatibility between the features used on the MC68HC908AS60A and
MC68HC908AZ60A and those which are available on the device which
will ultimately be used in the application.

1.3 Features

Features of the MC68HC908AS60A and MC68HC908AZ60A include:

• High-Performance M68HC08 Architecture

• Fully Upward-Compatible Object Code with M6805, M146805,
and M68HC05 Families

• 8.4 MHz Internal Bus Frequency

• 60 Kbytes of FLASH Electrically Erasable Read-Only Memory
(FLASH)

• FLASH Data Security

• 1 Kbyte of On-Chip Electrically Erasable Programmable Read­Only Memory with Security Option (EEPROM)

• 2 Kbyte of On-Chip RAM

• Clock Generator Module (CGM)

• Serial Peripheral Interface Module (SPI)

• Serial Communications Interface Module (SCI)

• 8-Bit, 15-Channel Analog-to-Digital Converter (ADC-15)

Technical Data MC68HC908AZ60A — Rev 2.0

32 General Description MOTOROLA

General Description

• 16-Bit, 6-Channel Timer Interface Module (TIMA-6)

• Programmable Interrupt Timer (PIT)

• System Protection Features

– Computer Operating Properly (COP) with Optional Reset

– Low-Voltage Detection with Optional Reset

– Illegal Opcode Detection with Optional Reset

– Illegal Address Detection with Optional Reset

• Low-Power Design (Fully Static with Stop and Wait Modes)

• Master Reset Pin and Power-On Reset

• 16-Bit, 2-Channel Timer Interface Module (TIMB) (AZ only)

• 5-Bit Keyboard Interrupt Module (64-Pin QFP only)

Features

• MSCAN Controller (Motorola Scalable CAN) implements CAN

2.0b Protocol as Defined in BOSCH Specification September
1991 (AZ only)

• SAE J1850 Byte Data Link Controller Digital Module (AS only)

Features of the CPU08 include:

• Enhanced HC05 Programming Model

• Extensive Loop Control Functions

• 16 Addressing Modes (Eight More Than the HC05)

• 16-Bit Index Register and Stack Pointer

• Memory-to-Memory Data Transfers

•Fast 8 × 8 Multiply Instruction

• Fast 16/8 Divide Instruction

• Binary-Coded Decimal (BCD) Instructions

• Optimization for Controller Applications

• C Language Support

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA General Description 33

General Description

1.4 MCU Block Diagram

Figure 1-1 shows the structure of the MC68HC908AZ60A

Figure 1-2 shows the structure of the MC68HC908AS60A

Technical Data MC68HC908AZ60A — Rev 2.0

34 General Description MOTOROLA

General Description

MCU Block Diagram

PTA7–PTA0

PTA

DDRA

REFH

V

ANALOG-TO-DIGITAL

PTB7/ATD7–PTB0/ATD0

PTB

DDRB

MODULE

PTD3/ATD11-PTD0/ATD8

PTD4/ATD12/TBCLK

PTD6/ATD14/TACLK

PTD5/ATD13

BREAK MODULE

PTC2/MCLK

PTC

PTD7

PTC1–PTC0

DDRC

LOW-VOLTAGE INHIBIT

PTD

MODULE

PTC5–PTC3

DDRD

PROPERLY MODULE

COMPUTER OPERATING

PTE7/SPSCK

TIMER A 6 CHANNEL

PTE6/MOSI

PTE5/MISO

INTERFACE MODULE

PTE4/SS

TIMER B INTERFACE

PTE3/TACH1

PTE

DDRE

MODULE

PTE2/TACH0

PTE1/RxD

INTERFACE MODULE

SERIAL COMMUNICATIONS

PTE0/TxD

PTF6

PTF5/TBCH1–PTF4/TBCH0

PTF

DDRF

SERIAL PERIPHERAL

INTERFACE MODULE

PTF3/TACH5-PTF0/TACH2

KEYBOARD INTERRUPT

PTG2/KBD2–PTG0/KBD0

PTG

MODULE

PTH1/KBD4–PTH0/KBD3

DDRG

PROGRAMMABLE INTERRUPT TIMER

PTH

DDRH

MODULE

CANTx

CANRx

MSCAN MODULE

REFL

/V

SS

DDAREF

V

AV

UNIT (ALU)

ARITHMETIC/LOGIC

M68HC08 CPU

USER RAM — 2048BYTES

CPU

REGISTERS

USER FLASH — 60 kBYTES

CONTROL AND STATUS REGISTERS — 62 BYTES

MONITOR ROM — 256 BYTES

USER EEPROM — 1024 BYTES

USER FLASH VECTOR SPACE — 52 BYTES

MODULE

CLOCK GENERATOR

OSC1

OSC2

CGMXFC

MODULE

IRQ MODULE

SYSTEM INTEGRATION

IRQ

RST

POWER-ON RESET

MODULE

POWER

Figure 1-1. MCU Block Diagram for the MC68HC908AZ60A (64-Pin QFP)

SS

DD

V

SSA

DDA

V

V

V

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA General Description 35

General Description

PTD4/ATD12/TBCLK

PTD6/ATD14/TACLK

PTD5/ATD13

PTA7–PTA0

PTA

DDRA

REFH

V

ANALOG-TO-DIGITAL

PTB7/ATD7–PTB0/ATD0

PTB

DDRB

MODULE

PTC5*

PTC4

PTC3

BREAK MODULE

PTD7*

PTC2/MCLK

PTC1–PTC0

PTC

DDRC

MODULE

LOW-VOLTAGE INHIBIT

PTD

COMPUTER OPERATING

PTD3/ATD11-PTD0/ATD8

DDRD

PROPERLY MODULE

TIMER A 6 CHANNEL

PTE7/SPSCK

PTE6/MOSI

INTERFACE MODULE

PTE5/MISO

PTE4/SS

PTE3/TACH1

PTE

DDRE

MODULE

SERIAL COMMUNICATIONS

PROGRAMMABLE INTERRUPT TIMER

PTE2/TACH0

INTERFACE MODULE

PTF6*

PTE1/RxD

PTE0/TxD

PTF5/TBCH1–PTF4/TBCH0*

PTF

SERIAL PERIPHERAL

INTERFACE MODULE

PTF3/TACH5-PTF0/TACH2

DDRF

KEYBOARD INTERRUPT

PTG2/KBD2–PTG0/KBD0*

MODULE*

PTH1/KBD4–PTH0/KBD3*

PTG*

PTH*

DDRG

DDRH

BDTxD

BDRxD

BYTE DATA LINK CONTROLLER

REFL

/V

SS

DDAREF

V

AV

UNIT (ALU)

ARITHMETIC/LOGIC

M68HC08 CPU

CPU

REGISTERS

MODULE

CLOCK GENERATOR

USER RAM — 2048BYTES

USER FLASH — 60 kBYTES

CONTROL AND STATUS REGISTERS — 62 BYTES

MONITOR ROM — 256 BYTES

USER EEPROM — 1024 BYTES

USER FLASH VECTOR SPACE — 52 BYTES

OSC1

OSC2

CGMXFC

MODULE

IRQ MODULE

SYSTEM INTEGRATION

IRQ

RST

POWER-ON RESET

POWER

MODULE

SS

DD

V

SSA

DDA

V

V

V

Figure 1-2. MCU Block Diagram for the MC68HC908AS60A (64-Pin QFP and 52-pin PLCC)

* = Feature only available on the 64-pin QFP MC68HC908AS60A

Technical Data MC68HC908AZ60A — Rev 2.0

36 General Description MOTOROLA

1.5 Pin Assignments

Figure 1-3 shows the MC68HC908AZ60A pin assignments.

PTC5

General Description

Pin Assignments

SSAVDDA

CGMXFC

PTC3

PTC2/MCLK

PTC1

PTC0

OSC1

OSC2

V

REFH

V

PTD7

PTD6/ATD14/TACLK

PTD5/ATD13

PTD4/ATD12/TBCLK

PTH1/KBD4

PTC4

IRQ

RST

PTF0/TACH2

PTF1/TACH3

PTF2/TACH4

PTF3/TACH5

PTF4/TBCH0

CANRx

CANTx

PTF5/TBCH1

PTF6

PTE0/TxD

PTE1/RxD

PTE2/TACH0

PTE3/TACH1

16

64

63

62

61

60

59

58

57

56

55

54

53

52

29

PTA3

51

30

PTA4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

18

19

20

21

22

23

24

25

26

27

28

17

SS

DD

V

V

PTE4/SS

PTE6/MOSI

PTE5/MISO

PTE7/SPSCK

PTG0/KBD0

PTG1/KBD1

PTA0

PTA1

PTA2

PTG2/KBD2

50

31

PTA5

47

46

45

44

43

42

41

40

39

38

37

36

35

34

49

48

33

32

PTA6

PTH0/KBD3

PTD3/ATD11

PTD2/ATD10

AV

SS /VREFL

V

DDAREF

PTD1/ATD9

PTD0/ATD8

PTB7/ATD7

PTB6/ATD6

PTB5/ATD5

PTB4/ATD4

PTB3/ATD3

PTB2/ATD2

PTB1/ATD1

PTB0/ATD0

PTA7

Figure 1-3. MC68HC908AZ60A (64-Pin QFP)

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA General Description 37

General Description

PTC4

IRQ

RST

PTF0/TACH2

PTF1/TACH3

PTF2/TACH4

PTF3/TACH5

PTF4

BDRxD

BDTxD

PTF5

PTF6

PTE0/TxD

PTE1/RxD

PTE2/TACH0

PTE3/TACH1

Figure 1-4 shows the MC68HC908AS60A 64-pin QFP pin assignments.

16

SSAVDDA

CGMXFC

57

24

PTG1/KBD1

V

56

25

PTG2/KBD2

PTC5

PTC3

PTC2/MCLK

PTC1

PTC0

OSC1

OSC2

64

63

62

61

60

59

22

V

58

23

DD

PTG0/KBD0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

18

19

20

21

17

SS

V

PTE4/SS

PTE6/MOSI

PTE5/MISO

PTE7/SPSCK

55

26

PTA0

REFH

V

54

27

PTA1

PTD7

53

28

PTA2

PTD6/ATD14/TACLK

52

29

PTA3

PTD5/ATD13

51

30

PTA4

PTD4/ATD12

50

31

PTA5

47

46

45

44

43

42

41

40

39

38

37

36

35

34

PTH1/KBD4

49

48

33

32

PTA6

PTH0/KBD3

PTD3/ATD11

PTD2/ATD10

AV

SS /VREFL

V

DDAREF

PTD1/ATD9

PTD0/ATD8

PTB7/ATD7

PTB6/ATD6

PTB5/ATD5

PTB4/ATD4

PTB3/ATD3

PTB2/ATD2

PTB1/ATD1

PTB0/ATD0

PTA7

Figure 1-4. MC68HC908AS60A (64-Pin QFP)

Technical Data MC68HC908AZ60A — Rev 2.0

38 General Description MOTOROLA

PTC4

General Description

Pin Assignments

Figure 1-5 shows MC68HC908AS60A 52-pin PLCC pin assignments.

DDAREF

REFL

/V

/V

SSA

DDA

CGMXFC

PTC3

PTC2/MCLK

PTC1

PTC0

OSC1

OSC2

7

6

5

4

3

2

8

V

1

52

REFH

V

V

PTD6/ATD14/TACLK

PTD5/ATD13

PTD4/ATD12

47

51

50

49

48

46

PTD3/ATD11

IRQ

RST

PTF0/TACH2

PTF1/TACH3

PTF2/TACH4

PTF3/TACH5

BDRxD

BDTxD

PTE0/TxD

PTE1/RxD

PTE2/TACH0

PTE3/TACH1

34

PTD2/ATD10

PTD1/ATD9

PTD0/ATD8

PTB7/ATD7

PTB6/ATD6

PTB5/ATD5

PTB4/ATD4

PTB3/ATD3

PTB2/ATD2

PTB1/ATD1

PTB0/ATD0

PTA7

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

SS

DD

V

V

PTA0

PTA1

PTA2

PTA3

PTA4

PTA5

PTE4/SS

PTE5/MISO

PTE6/MOSI

PTE7/SPSCK

45

44

43

42

41

40

39

38

37

36

35

32

33

PTA6

Figure 1-5. MC68HC908AS60A (52-Pin PLCC)

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA General Description 39

General Description

NOTE: The following pin descriptions are just a quick reference. For a more

detailed representation, see Input/Output Ports on page 353.

1.5.1 Power Supply Pins (VDD and VSS)

and VSS are the power supply and ground pins. The MCU operates

V

DD

from a single power supply.

Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as shown in Figure

1-6. Place the C1 bypass capacitor as close to the MCU as possible. Use

a high-frequency response ceramic capacitor for C1. C2 is an optional
bulk current bypass capacitor for use in applications that require the port
pins to source high current levels.

V

DD

V

DD

NOTE: Component values shown represent typical applications.

MCU

C1

µF

0.1

+

C2

V

SS

Figure 1-6. Power supply bypassing

VSS is also the ground for the port output buffers and the ground return
for the serial clock in the Serial Peripheral Interface module (SPI). See

Serial Peripheral Interface (SPI) on page 285.

NOTE: V

must be grounded for proper MCU operation.

SS

Technical Data MC68HC908AZ60A — Rev 2.0

40 General Description MOTOROLA

1.5.2 Oscillator Pins (OSC1 and OSC2)

The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. See Clock Generator Module (CGM) on page 169.

General Description

Pin Assignments

1.5.3 External Reset Pin (RST

)

A logic 0 on the RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted. See System Integration Module

(SIM) on page 147 for more information.

1.5.4 External Interrupt Pin (IRQ)

IRQ is an asynchronous external interrupt pin. See External Interrupt

Module (IRQ) on page 235.

1.5.5 Analog Power Supply Pin (V

V

is the power supply pin for the analog portion of the Clock

DDA

Generator Module (CGM). See Clock Generator Module (CGM) on
page 169.

DDA

pin forces the MCU to a known startup state. RST

)

1.5.6 Analog Ground Pin (V

V

SSA

)

SSA

is the ground connection for the analog portion of the Clock
Generator Module (CGM). See Clock Generator Module (CGM) on
page 169.

1.5.7 External Filter Capacitor Pin (CGMXFC)

CGMXFC is an external filter capacitor connection for the Clock
Generator Module (CGM). See Clock Generator Module (CGM) on
page 169.

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA General Description 41

General Description

1.5.8 ADC Analog Power Supply Pin (V

V

DDAREF

is the power supply pin for the analog portion of the Analog-to­Digital Converter (ADC). See Analog-to-Digital Converter (ADC) on
page 471.

1.5.9 ADC Analog Ground Pin (AV

The AVSS/V

SS/VREFL

REFL

the reference low voltage for the Analog-to-Digital Converter (ADC). See

Analog-to-Digital Converter (ADC) on page 471.

1.5.10 ADC Reference High Voltage Pin (V

V

provides the reference high voltage for the Analog-to-Digital

REFH

Converter (ADC). See Analog-to-Digital Converter (ADC) on page

471.

DDAREF

)

)

pin provides both the analog ground connection and

)

REFH

1.5.11 Port A Input/Output (I/O) Pins (PTA7–PTA0)

PTA7–PTA0 are general-purpose bidirectional I/O port pins. See

Input/Output Ports on page 353.

1.5.12 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0)

Port B is an 8-bit special function port that shares all eight pins with the
Analog-to-Digital Converter (ADC). See Analog-to-Digital Converter

(ADC) on page 471 and Input/Output Ports on page 353.

1.5.13 Port C I/O Pins (PTC5–PTC0)

PTC5–PTC3 and PTC1–PTC0 are general-purpose bidirectional I/O
port pins. PTC2/MCLK is a special function port that shares its pin with
the system clock which has a frequency equivalent to the system clock.
See Input/Output Ports on page 353.

Technical Data MC68HC908AZ60A — Rev 2.0

42 General Description MOTOROLA

1.5.14 Port D I/O Pins (PTD7–PTD0/ATD8)

Port D is an 8-bit special-function port that shares seven of its pins with
the Analog-to-Digital Converter module (ADC-15), one of its pins with
the Timer Interface Module A (TIMA), and one more of its pins with the
Timer Interface Module B (TIMB). See Timer Interface Module A

(TIMA) on page 441, Timer Interface Module B (TIMB) on page 317,
Analog-to-Digital Converter (ADC) on page 471 and Input/Output
Ports on page 353.

1.5.15 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD)

Port E is an 8-bit special function port that shares two of its pins with the
Timer Interface Module A (TIMA), four of its pins with the Serial
Peripheral Interface module (SPI), and two of its pins with the Serial
Communication Interface module (SCI). See Serial Communications

Interface (SCI) on page 243, Serial Peripheral Interface (SPI) on page

285, Timer Interface Module A (TIMA) on page 441, and Input/Output

Ports on page 353.

General Description

Pin Assignments

1.5.16 Port F I/O Pins (PTF6–PTF0/TACH2)

Port F is a 7-bit special function port that shares its pins with the Timer
Interface Module B (TIMB). Six of its pins are shared with the Timer
Interface Module A (TIMA-6). See Timer Interface Module A (TIMA) on
page 441, Timer Interface Module B (TIMB) on page 317, and

Input/Output Ports on page 353.

1.5.17 Port G I/O Pins (PTG2/KBD2–PTG0/KBD0)

Port G is a 3-bit special function port that shares all of its pins with the
Keyboard Module (KBD). See Keyboard Module (KBD) on page 431
and Input/Output Ports on page 353.

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA General Description 43

General Description

1.5.18 Port H I/O Pins (PTH1/KBD4–PTH0/KBD3)

Port H is a 2-bit special-function port that shares all of its pins with the
Keyboard Module (KBD). See Keyboard Module (KBD) on page 431
and Input/Output Ports on page 353.

1.5.19 CAN Transmit Pin (CANTx)

This pin is the digital output from the CAN module (CANTx). See

MSCAN Controller (MSCAN08) on page 379.

1.5.20 CAN Receive Pin (CANRx)

This pin is the digital input to the CAN module (CANRx). See MSCAN

Controller (MSCAN08) on page 379.

1.5.21 BDLC Transmit Pin (BDTxD)

This pin is the digital output from the BDLC module (BDTxD). See Byte

Data Link Controller (BDLC) on page 483.

1.5.22 BDLC Receive Pin (BDRxD)

This pin is the digital input to the CAN module (BDRxD). See Byte Data

Link Controller (BDLC) on page 483.

Table 1-1. External Pins Summary

Pin Name Function

PTA7–PTA0 General-Purpose I/O Dual State No Input Hi-Z

PTB7/ATD7–PTB0/ATD0

PTC5–PTC0 General-Purpose I/O Dual State No Input Hi-Z

General-Purpose I/O

ADC Channel

Driver

Type

Dual State No Input Hi-Z

Hysteresis

(1)

Reset State

PTD7 General Purpose I/O Dual State No Input Hi-Z

Technical Data MC68HC908AZ60A — Rev 2.0

44 General Description MOTOROLA

Table 1-1. External Pins Summary (Continued)

General Description

Pin Assignments

Pin Name Function

PTD6/ATD14/TACLK ADC Channel

PTD5/ATD13 ADC Channel

PTD4/ATD12/TBCLK ADC Channel

PTD3/ATD11–PTD0/ATD8 ADC Channels

PTE7/SPSCK

PTE6/MOSI

PTE5/MISO

PTE4/SS

General-Purpose I/O

ADC Channel/Timer
External Input Clock

General-Purpose I/O

ADC Channel

General-Purpose I/O

ADC Channel/Timer
External Input Clock

General-Purpose I/O

ADC Channel

General-Purpose I/O

SPI Clock

General-Purpose I/O

SPI Data Path

General-Purpose I/O

SPI Data Path

General-Purpose I/O

SPI Slave Select

Driver

Type

Dual State No Input Hi-Z

Dual State No Input Hi-Z

Dual State No Input Hi-Z

Dual State No Input Hi-Z

Dual State

Open Drain

Dual State

Open Drain

Dual State

Open Drain

Dual State Yes Input Hi-Z

Hysteresis

(1)

Yes Input Hi-Z

Yes Input Hi-Z

Yes Input Hi-Z

Reset State

PTE3/TACH1

PTE2/TACH0

PTE1/RxD

PTE0/TxD

PTF6 General-Purpose I/O Dual State No Input Hi-Z

PTF5/TBCH1–PTF4/TBCH0

PTF3/TACH5

PTF2/TACH4

PTF1/TACH3

General-Purpose I/O

Timer A Channel 1

General-Purpose I/O

Timer A Channel 0

General-Purpose I/O

SCI Receive Data

General-Purpose I/O

SCI Transmit Data

General-Purpose

I/O/Timer B Channel

General-Purpose I/O

Timer A Channel 5

General-Purpose I/O

Timer A Channel 4

General-Purpose I/O

Timer A Channel 3

Dual State Yes Input Hi-Z

Dual State Yes Input Hi-Z

Dual State Yes Input Hi-Z

Dual State No Input Hi-Z

Dual State Yes Input Hi-Z

Dual State Yes Input Hi-Z

Dual State Yes Input Hi-Z

Dual State Yes Input Hi-Z

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA General Description 45

General Description

Table 1-1. External Pins Summary (Continued)

Pin Name Function

PTF0/TACH2

General-Purpose I/O

Timer A Channel 2

Driver

Type

Dual State Yes Input Hi-Z

Hysteresis

(1)

Reset State

General-Purpose I/O/

PTG2/KBD2–PTG0/KBD0

Keyboard Wakeup

Dual State Yes Input Hi-Z

Pin

General-Purpose I/O/

PTH1/KBD4 –PTH0/KBD3

Keyboard Wakeup

Dual State Yes Input Hi-Z

Pin

V

DD

V

SS

V

DDA

V

SSA

V

DDAREF

A

VSS/VREFL

Chip Power Supply N/A N/A N/A

Chip Ground N/A N/A N/A

CGM Analog Power

Supply

CGM Analog Ground

ADC Power Supply N/A N/A N/A

ADC Ground/ADC

Reference Low

N/A N/A N/A

Voltage

V

REFH

A/D Reference High

Voltage

OSC1 External Clock In N/A N/A Input Hi-Z

OSC2 External Clock Out N/A N/A Output

CGMXFC PLL Loop Filter Cap N/A N/A N/A

IRQ

RST

External Interrupt

Request

Reset N/A N/A Output Low

CANRx CAN Serial Input N/A Yes Input Hi-Z

CANTx CAN Serial Output Output No Output

BDRxD BDLC Serial Input N/A Yes Input Hi-Z

BDTxD BDLC Serial Output Output No Output

1. Hysteresis is not 100% tested but is typically a minimum of 300mV.

N/A N/A N/A

N/A N/A Input Hi-Z

Technical Data MC68HC908AZ60A — Rev 2.0

46 General Description MOTOROLA

Table 1-2. Clock Signal Naming Conventions

Clock Signal Name Description

General Description

Pin Assignments

CGMXCLK

CGMOUT

Bus Clock CGMOUT divided by two

SPSCK SPI serial clock

TACLK External clock input for TIMA

TBCLK External clock input for TIMB

PLL-based or OSC1-based clock output from

Buffered version of OSC1 from

Clock Generation Module (CGM)

Clock Generator Module (CGM)

Table 1-3. Clock Source Summary

Module Clock Source

ADC CGMXCLK or Bus Clock

CAN CGMXCLK or CGMOUT

COP CGMXCLK

CPU Bus Clock

FLASH Bus Clock

EEPROM CGMXCLK or Bus Clock

RAM Bus Clock

SPI Bus Clock/SPSCK

SCI CGMXCLK

TIMA Bus Clock or PTD6/ATD14/TACLK

TIMB Bus Clock or PTD4/TBCLK

PIT Bus Clock

SIM CGMOUT and CGMXCLK

IRQ Bus Clock

BRK Bus Clock

LVI Bus Clock

CGM OSC1 and OSC2

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA General Description 47

General Description

1.6 Ordering Information

This section contains instructions for ordering the MC68HC908AZ60A /
MC68HC908AS60A.

1.6.1 MC Order Numbers

Table 1-4. MC Order Numbers

MC Order Number

MC68HC908AS60ACFU (64-Pin QFP) –40°C to + 85°C

MC68HC908AS60AVFU (64-Pin QFP) –40

MC68HC908AS60AMFU (64-Pin QFP) –40°C to + 125°C

MC68HC908AS60ACFN (52-Pin PLCC) –40

MC68HC908AS60AVFN (52-Pin PLCC) –40

MC68HC908AS60AMFN (52-Pin PLCC) –40°C to + 125°C

MC68HC908AZ60ACFU (64-Pin QFP) –40

MC68HC908AZ60AVFU (64-Pin QFP) –40

MC68HC908AZ60AMFU (64-Pin QFP) –40°C to + 125°C

Operating

Temperature Range

°C to + 105°C

°C to + 85°C

°C to + 105°C

°C to + 85°C

°C to + 105°C

Technical Data MC68HC908AZ60A — Rev 2.0

48 General Description MOTOROLA

Technical Data — MC68HC908AZ60A

2.1 Contents

2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

2.3 I/O Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

2.4 Additional Status and Control Registers . . . . . . . . . . . . . . .58

2.5 Vector Addresses and Priority . . . . . . . . . . . . . . . . . . . . . . .61

2.2 Introduction

The CPU08 can address 64K bytes of memory space. The memory
map, shown in Figure 2-1, includes:

Section 2. Memory Map

• 60K Bytes of FLASH EEPROM

• 2048 Bytes of RAM

• 1024 Bytes of EEPROM with Protect Option

• 52 Bytes of User-Defined Vectors

• 256 Bytes of Monitor ROM

The following definitions apply to the memory map representation of
reserved and unimplemented locations.

• Reserved — Accessing a reserved location can have
unpredictable effects on MCU operation.

• Unused — These locations are reserved in the memory map for
future use, accessing an unused location can have unpredictable
effects on MCU operation.

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Memory Map 49

Memory Map

• Unimplemented — Accessing an unimplemented location can
cause an illegal address reset (within the constraints as outlined
in the System Integration Module (SIM)).

MC68HC908AZ60A MC68HC908AS60A

$0000

↓ ↓

$003F $003F

$0040

↓

$004F $004F

$0050

↓ ↓

$044F $044F

$0450

↓

$04FF

I/O REGISTERS, 16 BYTES

FLASH-2, 176 BYTES

I/O REGISTERS (64 BYTES)

UNIMPLEMENTED , 11 BYTES

I/O REGISTERS, 5 BYTES

RAM-1, 1024 BYTES

$0000

$0040

↓

$004A

$004B

$0050

$0450

$0500

↓

$057F

$0580

↓

$05FF $05FF

$0600

↓ ↓

$07FF $07FF

Technical Data MC68HC908AZ60A — Rev 2.0

50 Memory Map MOTOROLA

CAN CONTROL AND MESSAGE

BUFFERS, 128 BYTES

FLASH-2, 128 BYTES

EEPROM-2, 512 BYTES

FLASH-2, 432 BYTES

↓

$0600

MC68HC908AZ60A MC68HC908AS60A

Memory Map

Introduction

$0800

↓ ↓

$09FF $09FF

$0A00

↓ ↓

$0DFF $0DFF

$0E00

↓ ↓

$7FFF $7FFF

$8000

↓ ↓

$FDFF $FDFF

$FE00 SIM BREAK STATUS REGISTER (SBSR) $FE00

$FE01 SIM RESET STATUS REGISTER (SRSR) $FE01

$FE02

EEPROM-1, 512 BYTES

RAM-2 , 1024 BYTES

FLASH-2, 29,184 BYTES

FLASH-1, 32,256BYTES

RESERVED $FE02

$0800

$0A00

$0E00

$8000

$FE03 SIM BREAK FLAG CONTROL REGISTER (SBFCR) $FE03

$FE04

$FE05

$FE06

$FE07

$FE08 FLASH-2 CONTROL REGISTER (FL2CR) $FE08

$FE09 CONFIGURATION WRITE-ONCE REGISER (CONFIG-2) $FE09

$FE0A

$FE0B

$FE0C BREAK ADDRESS REGISTER HIGH (BRKH) $FE0C

$FE0D BREAK ADDRESS REGISTER LOW (BRKL) $FE0D

$FE0E BREAK STATUS AND CONTROL REGISTER (BSCR) $FE0E

$FE0F LVI STATUS REGISTER (LVISR) $FE0F

$FE10 EEPROM-1EEDIVH NON-VOLATILE REGISTER(EE1DIVHNVR) $FE10

RESERVED $FE04

RESERVED $FE05

RESERVED $FE06

RESERVED $FE07

RESERVED $FE0A

RESERVED $FE0B

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Memory Map 51

Memory Map

MC68HC908AZ60A MC68HC908AS60A

$FE11 EEPROM-1EEDIVL NON-VOLATILE REGISTER(EE1DIVLNVR) $FE11

$FE12

$FE13 RESERVED $FE13

$FE14

$FE15

$FE16 RESERVED $FE16

$FE17

$FE18

$FE19

$FE1A EEPROM-1 EE DIVIDER HIGH REGISTER(EE1DIVH) $FE1A

$FE1B EEPROM-1 EE DIVIDER LOW REGISTER(EE1DIVL) $FE1B

$FE1C EEPROM-1 EEPROM NON-VOLATILE REGISTER (EE1NVR) $FE1C

$FE1D EEPROM-1 EEPROM CONTROL REGISTER (EE1CR) $FE1D

$FE1E

RESERVED $FE12

RESERVED $FE14

RESERVED $FE15

RESERVED $FE17

RESERVED $FE18

RESERVED $FE19

RESERVED $FE1E

$FE1F EEPROM-1 EEPROM ARRAY CONFIGURATION REGISTER (EE1ACR) $FE1F

$FE20

$FE20

↓ ↓

$FF1F $FF1F

$FF20

↓

$FF6F

$FF70 EEPROM-2 EEDIVH NON-VOLATILE REGISTER (EE2DIVHNVR) $FF70

$FF71 EEPROM-2 EEDIVL NON-VOLATILE REGISTER (EE2DIVLNVR) $FF71

$FF72

$FF73

$FF74

$FF75 RESERVED $FF75

$FF76

$FF77

$FF78 RESERVED $FF78

$FF79

MONITOR ROM (256BYTES)

UNIMPLEMENTED (80 BYTES)

RESERVED $FF72

RESERVED $FF73

RESERVED $FF74

RESERVED $FF76

RESERVED $FF77

RESERVED $FF79

$FF20

↓

$FF6F

Technical Data MC68HC908AZ60A — Rev 2.0

52 Memory Map MOTOROLA

Memory Map

Introduction

MC68HC908AZ60A MC68HC908AS60A

$FF7A EEPROM-2 EE DIVIDER HIGH REGISTER (EE2DIVH) $FF7A

$FF7B EEPROM-2 EE DIVIDER LOW REGISTER (EE2DIVL) $FF7B

$FF7C EEPROM-2 EEPROM NON-VOLATILE REGISTER (EE2NVR) $FF7C

$FF7D EEPROM-2 EEPROM CONTROL REGISTER (EE2CR) $FF7D

$FF7E

$FF7F EEPROM-2 EEPROM ARRAY CONFIGURATION REGISTER (EE2ACR) $FF7F

$FF80 FLASH-1 BLOCK PROTECT REGISTER (FL1BPR) $FF80

$FF81 FLASH-2 BLOCK PROTECT REGISTER (FL2BPR) $FF81

$FF82

↓ ↓

$FF87 $FF87

$FF88 FLASH-1 CONTROL REGISTER (FL1CR) $FF88

$FF89

$FF8A

$FF8B

↓ ↓

$FFCB $FFCB

$FFCC $FFCC

↓

RESERVED $FF7E

RESERVED (6 BYTES)

RESERVED $FF89

RESERVED $FF8A

RESERVED (64 BYTES)

VECTORS (52BYTES)

See Table 2-1 on page 61

$FF82

$FF8B

↓

$FFFF $FFFF

Figure 2-1. Memory Map (Continued)

Note 1: Registers appearing in italics are for Motorola test purpose only and only appear in the Memory Map for reference.
Note2: While some differences between MC68HC908AS60A and MC68HC908AZ60A are highlighted, some registers remain available

on both parts. Refer to individual modules for details whether these registers are active or inactive.

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Memory Map 53

Memory Map

2.3 I/O Section

Addresses $0000–$004F, shown in Figure 2-2, contain the I/O Data,
Status and Control Registers.

Addr.Register Name Bit 7654321Bit 0

$0000 Port A Data Register (PTA)

$0001 Port B Data Register (PTB)

$0002 Port C Data Register (PTC)

$0003 Port D Data Register (PTD)

$0004

$0005

$0006

$0007

$0008 Port E Data Register (PTE)

$0009 Port F Data Register (PTF)

$000A Port G Data Register (PTG)

$000B Port H Data Register (PTH)

$000C

$000D

$000E

Data Direction Register A

Data Direction Register B

Data Direction Register C

Data Direction Register D

Data Direction Register E

Data Direction Register F

Data Direction Register G

(DDRA)

(DDRB)

(DDRC)

(DDRD)

(DDRE)

(DDRF)

(DDRG)

Read:

Write:

Read:

Write:

Read: 0 0

Write: R R

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write: R

Read:

Write:

Read:

Write:

Read: 0

Write: R

Read: 00000

Write:RRRRR

Read: 000000

Write:RRRRRR

Read:

Write:

Read: 0

Write: R

Read: 00000

Write:RRRRR

PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0

PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0

PTC5 PTC4 PTC3 PTC2 PTC1 PTC0

PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0

DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0

DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

MCLKE

N

DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDR2 DDRD1 DDRD0

PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0

DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0

0

DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0

PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0

PTG2 PTG1 PTG0

PTH1 PTH0

DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0

DDRG2 DDRG1 DDRG0

Figure 2-2. I/O Data, Status and Control Registers (Sheet 1 of 5)

Technical Data MC68HC908AZ60A — Rev 2.0

54 Memory Map MOTOROLA

Memory Map

I/O Section

Addr.Register Name Bit 7654321Bit 0

$000F

$0010 SPI Control Register (SPCR)

$0011

$0012 SPI Data Register (SPDR)

$0013 SCI Control Register 1 (SCC1)

$0014 SCI Control Register 2 (SCC2)

$0015 SCI Control Register 3 (SCC3)

$0016 SCI Status Register 1 (SCS1)

$0017 SCI Status Register 2 (SCS2)

$0018 SCI Data Register (SCDR)

$0019 SCI Baud Rate Register (SCBR)

$001A

$001B

$001C PLL Control Register (PCTL)

$001D

$001E

$001F

$0020

Data Direction Register H

(DDRH)

SPI Status and Control

Register (SPSCR)

IRQ Status and Control

Register (ISCR)

Keyboard Status and Control

Register (KBSCR)

PLL Bandwidth Control

Register (PBWC)

PLL Programming Register

(PPG)

Configuration Write-Once

Register (CONFIG-1)

Timer A Status and Control

Register (TASC)

Read: 000000

Write:RRRRRR

Read:

Write:

Read: SPRF

Write:

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Read:

Write:

Read:

Write:

Read: R8

Write:

Read: SCTE TC SCRF IDLE OR NF FE PE

Write:

Read: 000000BKFRPF

Write:

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Read: 0 0

Write:

Read: 0000IRQF0

Write:RRRRRACK

Read: 0000KEYF0

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read: TOF

Write: 0 TRST R

SP RIE R SPMSTR CPOL CPHA SPWOM S PE SP TIE

ERRIE

LOOPS ENSCI TXINV M WAKE ILTY PEN PTY

SCTIE TCIE SCRIE ILIE TE RE RWU SBK

T8 R R ORIE NEIE FEIE PEIE

PLLIE

AUTO

MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4

LVI STO

P

PLLF

LOCK

R LVIRST LVIPWR SSREC COPL STOP COPD

TOIE TSTOP

OVRF MODF SPTE

SCP1 SCP0 R SCR2 SCR1 SCR0

PLLON BCS

ACQ XLD

00

MODFE

ACKK

1111

0000

PS2 PS1 PS0

DDRH1 DDRH0

N

SPR1 SPR0

IMASK MODE

IMASKK MODEK

Figure 2-2. I/O Data, Status and Control Registers (Sheet 2 of 5)

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Memory Map 55

Memory Map

Addr.Register Name Bit 7654321Bit 0

Read: 0 0 0

Write:

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:RRRRRRRR

Read: Bit 7 654321Bit 0

Write:RRRRRRRR

Read:

Write:

Read:

Write:

Read: CH0F

Write: 0

Read:

Write:

Read:

Write:

Read: CH1F

Write: 0 R

Read:

Write:

Read:

Write:

Read: CH2F

Write: 0

Read:

Write:

Read:

Write:

Read: CH3F

Write: 0 R

Read:

Write:

Read:

Write:

Read: CH4F

Write: 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

CH1IE

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

CH3IE

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

CH4IE MS4B MS4A ELS4B ELS4A TOV4 CH4MAX

KBIE4 KBIE3 KBIE2 KBIE1 KBIE0

0

MS1A ELS1B ELS1A TOV1 CH1MAX

0

MS3A ELS3B ELS3A TOV3 CH3MAX

$0021

$0022

$0023

$0024

$0025

$0026

$0027

$0028

$0029

$002A

$002B

$002C

$002D

$002E

$002F

$0030

$0031

$0032

Keyboard Interrupt Enable

Register (KBIER)

Timer A Counter Register

High (TACNTH)

Timer A Counter Register

Low (TACNTL)

Timer A Modulo Register

High (TAMODH)

Timer A Modulo Register

Low (TAMODL)

Timer A Channel 0 Status and

Control Register (TASC0)

Timer A Channel 0 Register

High (TACH0H)

Timer A Channel 0 Register

Low (TACH0L)

Timer A Channel 1 Status and

Control Register (TASC1)

Timer A Channel 1 Register

High (TACH1H)

Timer A Channel 1 Register

Low (TACH1L)

Timer A Channel 2 Status and

Control Register (TASC2)

Timer A Channel 2 Register

High (TACH2H)

Timer A Channel 2 Register

Low (TACH2L)

Timer A Channel 3 Status and

Control Register (TASC3)

Timer A Channel 3 Register

High (TACH3H)

Timer A Channel 3 Register

Low (TACH3L)

Timer A Channel 4 Status and

Control Register (TASC4)

Figure 2-2. I/O Data, Status and Control Registers (Sheet 3 of 5)

Technical Data MC68HC908AZ60A — Rev 2.0

56 Memory Map MOTOROLA

Memory Map

I/O Section

Addr.Register Name Bit 7654321Bit 0

$0033

$0034

$0035

$0036

$0037

$0038

$0039

$003A

$003B

$003C BDLC Control Register 1 (BCR1)

$003D BDLC Control Register 2 (BCR2)

$003E

$003F BDLC Data Register (BDR)

$0040

$0041

$0042

$0043

$0044

Timer A Channel 4 Register High

(TACH4H)

Timer A Channel 4 Register Low

(TACH4L)

Timer A Channel 5 Status and

Control Register (TASC5)

Timer A Channel 5 Register

High (TACH5H)

Timer A Channel 5 Register

Low (TACH5L)

Analog-to-Digital Status and

Control Register (ADSCR)

Analog-to-Digital Data Register

(ADR)

Analog-to-Digital Input Clock

Register (ADICLK)

BDLC Analog and Roundtrip Delay

Register (BARD)

BDLC State Vector Register

(BSVR)

Timer B Status and Control

Register (TBSCR)

Timer B Counter Register High

(TBCNTH)

Timer B Counter Register Low

(TBCNTL)

Timer B Modulo Register High

(TBMODH)

Timer B Modulo Register Low

(TBMODL)

Read:

Write:

Read:

Write:

Read: CH5F

Write: 0 R

Read:

Write:

Read:

Write:

Read: COCO

Write: R

Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

Write:RRRRRRRR

Read:

Write: RRRR

Read:

Write: R R

Read:

Write: R R

Read:

Write:

Read: 0 0 I3 I2 I1 I0 0 0

Write:RRRRRRRR

Read:

Write:

Read: TOF

Write: 0 TRST R

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:RRRRRRRR

Read: Bit 7 654321Bit 0

Write:RRRRRRRR

Read:

Write:

Read:

Write:

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

CH5IE

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0

ADIV2 ADIV1 ADIV0 ADICLK

ATE RXPOL

IMSG CLKS R1 R0

ALOOP DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFR0

BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0

TOIE TSTOP

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

0

MS5A ELS5B ELS5A TOV5 CH5MAX

0000

00

00

BO3 BO2 BO1 BO0

00

PS2 PS1 PS0

IE WCM

Figure 2-2. I/O Data, Status and Control Registers (Sheet 4 of 5)

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Memory Map 57

Memory Map

Addr.Register Name Bit 7654321Bit 0

$0045

$0046

$0047

$0048 Write: 0 R

$0049

$004A

$004B

$004C

$004D

$004E

$004F

Timer B CH0 Status and Control

Register (TBSC0)

Timer B CH0 Register High

(TBCH0H)

Timer B CH0 Register Low

(TBCH0L)

Timer B CH1 Status and Control

Register (TBSC1)

Timer B CH1 Register High

(TBCH1H)

Timer B CH1 Register Low

(TBCH1L)

PIT Status and Control Register

(PSC)

PIT Counter Register High

(PCNTH)

PIT Counter Register Low

(PCNTL)

PIT Modulo Register High

(PMODH)

PIT Modulo Register Low

(PMODL)

Read: CH0F

Write: 0

Read:

Write:

Read:

Write:

Read: CH1F

Read:

Write:

Read:

Write:

Read: POF

Write: 0 PRST

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Read: Bit 7 654321Bit 0

Write:

Read:

Write:

Read:

Write:

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

CH1IE

POIE PSTOP

0

MS1A ELS1B ELS1A TOV1 CH1MAX

00

PPS2 PPS1 PPS0

= Unimplemented R = Reserved

Figure 2-2. I/O Data, Status and Control Registers (Sheet 5 of 5)

All registers are shown for both MC68HC908AS60A and
MC68HC908AZ60A. Refer to individual module sections to determine if
the module is available and the register active or not.

2.4 Additional Status and Control Registers

Selected addresses in the range $FE00 to $FFCB contain additional
Status and Control registers as shown inFigure 2-3. A noted exception
is the COP Control Register (COPCTL) at address $FFFF.

Technical Data MC68HC908AZ60A — Rev 2.0

58 Memory Map MOTOROLA

Memory Map

Additional Status and Control Registers

Addr.Register Name Bit 7654321Bit 0

$FE00

SIM Break Status Register

(SBSR)

$FE01 SIM Reset Status Register (SRSR)

Read:

Write: 0

RRRRRR

Read: POR PIN COP ILOP ILAD 0 LVI 0

BW

R

Write:

$FE03

$FE08

SIM Break Flag Control Register

(SBFCR)

FLASH-2 Control Register

(FL2CR)

Read:

Write:

Read:

Write:

BCFERRRRRRR

0000

HVEN VERF ERASE PGM

$FE09

$FE0C

$FE0D

$FE0E

Configuration Write-Once Register

(CONFIG-2)

Break Address Register High

(BRKH)

Break Address Register Low

(BRKL)

Break Status and Control

Register (BRKSCR)

$FE0F LVI Status Register (LVISR)

$FE10

EE1DIV Hi Non-volatile Register

(EE1DIVHNVR)

$FE11 EE1DIV Lo Non-volatile Register

(EE1DIVLNVR)

$FE1A EE1DIV Divider High Register

(EE1DIVH)

$FE1B EE1DIV Divider Low Register

(EE1DIVL)

$FE1C

$FE1D

$FE1F

$FF70

EEPROM-1 Nonvolatile Register

(EE1NVR)

EEPROM-1 Control Register

(EE1CR)

EEPROM-1 Array Configuration

Register (EE1ACR)

EE2DIV Hi Non-volatile Register

(EE2DIVHNVR)

Read:

EEDIVCLK

Write: R

Read:

Bit 15 14 13 12 11 10 9 Bit 8

RR

MSCAN

D

AT60A

RRAZxx

Write:

Read:

Bit 7654321Bit 0

Write:

Read:

Write:

BRKE BRKA

000000

Read: LVIOUT 0000000

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

EEDIVSECD

RRRR

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

EEDIVSECD

0000

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

UNUSEDUNUSEDUNUSE

UNUSE

D

0

EEOFF EERAS1 EERAS0 EELAT AUTO EEPGM

UNUSEDUNUSEDUNUSE

EEPRTC

D

EEPRTC

D

EEBP3 EEBP2 EEBP1 EEBP0

T

EEBP3 EEBP2 EEBP1 EEBP0

T

EEDIV1

0

EEDIV1

0

EEDIV9 EEDIV8

EEDIV9 EEDIV8

Write:

Read:

EEDIVSECD

RRRR

EEDIV1

0

EEDIV9 EEDIV8

Figure 2-3. Additional Status and Control Registers (Sheet 1 of 2)

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Memory Map 59

Memory Map

Addr.Register Name Bit 7654321Bit 0

$FF71 EE2DIV Lo Non-volatile Register Read:

(EE2DIVLNVR)

$FF7A EE2DIV Divider High Register Read:

(EE2DIVH)

$FF7B EE2DIV Divider Low Register Read:

(EE2DIVL)

EEPROM-2 Nonvolatile Register

(EE2NVR)

EEPROM-2 Control Register

(EE2CR)

EEPROM-2 Array Configuration

Register (EE2ACR)

FLASH-1 Block Protect Register

(FL1BPR)

FLASH-2 Block Protect Register

(FL2BPR)

FLASH-1 Control Register

(FL1CR)

$FE7C

$FE7D

$FE7F

$FF80

$FF81

$FF88

Read:

Read:

Read:

Read:

Read:

Read: 0000

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

EEDIVSECD

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

UNUSEDUNUSEDUNUSE

Write:

UNUSE

Write:

Write:

Write:

Write:

Write:

D

UNUSEDUNUSEDUNUSE

BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

0000

EEPRTC

D

0

EEOFF EERAS1 EERAS0 EELAT AUTO EEPGM

EEPRTC

D

EEBP3 EEBP2 EEBP1 EEBP0

T

EEBP3 EEBP2 EEBP1 EEBP0

T

HVEN VERF ERASE PGM

EEDIV1

0

EEDIV9 EEDIV8

$FFFF COP Control Register (COPCTL)

Figure 2-3. Additional Status and Control Registers (Sheet 2 of 2)

Read: LOW BYTE OF RESET VECTOR

Write: WRITING TO $FFFF CLEARS COP COUNTER

= Unimplemented R = Reserved

Technical Data MC68HC908AZ60A — Rev 2.0

60 Memory Map MOTOROLA

2.5 Vector Addresses and Priority

Addresses in the range $FFCC to $FFFF contain the user-specified
vector locations. The vector addresses are shown inTable 2-1. Please
note that certain vector addresses differ between the
MC68HC908AS60A and the MC68HC908AZ60A as shown in the table.
It is recommended that all vector addresses are defined.

Table 2-1. Vector Addresses

Address MC68HC908AZ60A MC68HC908AS60A

Memory Map

Vector Addresses and Priority

Vector

Lowest Priority

$FFCC TIMA Channel 5 Vector (High) Reserved

$FFCD TIMA Channel 5 Vector (Low) Reserved

$FFCE TIMA Channel 4 Vector (High) Reserved

$FFCF TIMA Channel 4 Vector (Low) Reserved

$FFD0 ADC Vector (High) Reserved

$FFD1 ADC Vector (Low) Reserved

$FFD2 Keyboard Vector (High)

$FFD3 Keyboard Vector (Low)

$FFD4 SCI Transmit Vector (High) Reserved

$FFD5 SCI Transmit Vector (Low) Reserved

$FFD6 SCI Receive Vector (High) Reserved

$FFD7 SCI Receive Vector (Low) Reserved

$FFD8 SCI Error Vector (High) Reserved

$FFD9 SCI Error Vector (Low) Reserved

$FFDA CAN Transmit Vector (High) PIT Vector (High)

$FFDB CAN Transmit Vector (Low) PIT Vector (Low)

$FFDC CAN Receive Vector (High) BDLC Vector (High)

$FFDD CAN Receive Vector (Low) BDLC Vector (Low)

$FFDE CAN Error Vector (High) ADC Vector (High)

$FFDF CAN Error Vector (Low) ADC Vector (Low)

$FFE0 CAN Wakeup Vector (High) SCI Transmit Vector (High)

$FFE1 CAN Wakeup Vector (Low) SCI Transmit Vector (Low)

$FFE2 SPI Transmit Vector (High) SCI Receive Vector (High)

$FFE3 SPI Transmit Vector (Low) SCI Receive Vector (Low)

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Memory Map 61

Memory Map

Table 2-1. Vector Addresses

Vector

Address MC68HC908AZ60A MC68HC908AS60A

$FFE4 SPI Receive Vector (High) SCI Error Vector (High)

$FFE5 SPI Receive Vector (Low) SCI Error Vector (Low)

$FFE6 TIMB Overflow Vector (High) SPI Transmit Vector (High)

$FFE7 TIMB Overflow Vector (Low) SPI Transmit Vector (Low)

$FFE8 TIMB CH1 Vector (High) SPI Receive Vector (High)

$FFE9 TIMB CH1 Vector (Low) SPI Receive Vector (Low)

$FFEA TIMB CH0 Vector (High) TIMA Overflow Vector (High)

$FFEB TIMB CH0 Vector (Low) TIMA Overflow Vector (Low)

$FFEC TIMA Overflow Vector (High) TIMA Channel 5 Vector (High)

$FFED TIMA Overflow Vector (Low) TIMA Channel 5 Vector (Low)

$FFEE TIMA CH3 Vector (High) TIMA Channel 4 Vector (High)

$FFEF TIMA CH3 Vector (Low) TIMA Channel 4 Vector (Low)

$FFF0 TIMA CH2 Vector (High) TIMA Channel 3 Vector (High)

Highest Priority

$FFF1 TIMA CH2 Vector (Low) TIMA Channel 3 Vector (Low)

$FFF2 TIMA CH1 Vector (High) TIMA Channel 2 Vector (High)

$FFF3 TIMA CH1 Vector (Low) TIMA Channel 2 Vector (Low)

$FFF4 TIMA CH0 Vector (High) TIMA Channel 1 Vector (High)

$FFF5 TIMA CH0 Vector (Low) TIMA Channel 1 Vector (Low)

$FFF6 PIT Vector (High) TIMA Channel 0 Vector (High)

$FFF7 PIT Vector (Low) TIMA Channel 0 Vector (Low)

$FFF8 PLL Vector (High)

$FFF9 PLL Vector (Low)

$FFFA IRQ1 Vector (High)

$FFFB IRQ1 Vector (Low)

$FFFC SWI Vector (High)

$FFFD SWI Vector (Low)

$FFFE Reset Vector (High)

$FFFF Reset Vector (Low)

Technical Data MC68HC908AZ60A — Rev 2.0

62 Memory Map MOTOROLA

Technical Data — MC68HC908AZ60A

3.1 Contents

3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.2 Introduction

This section describes the 2048 bytes of random-access memory
(RAM).

Section 3. RAM

3.3 Functional Description

Addresses $0050 through $044F and $0A00 through $0DFF are RAM
locations. The location of the stack RAM is programmable with the reset
stack pointer instruction (RSP). The 16-bit stack pointer allows the stack
RAM to be anywhere in the 64K-byte memory space.

NOTE: For correct operation, the stack pointer must point only to RAM

locations.

Within page zero are 176 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for input/output (I/O) control and user data or code. When the stack
pointer is moved from its reset location at $00FF, direct addressing
mode instructions can access all page zero RAM locations efficiently.
Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.

Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA RAM 63

RAM

NOTE: For M68HC05, M6805, and M146805 compatibility, the H register is not

stacked.

During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.

NOTE: Be careful when using nested subroutines. The CPU could overwrite

data in the RAM during a subroutine or during the interrupt stacking
operation.

Technical Data MC68HC908AZ60A — Rev 2.0

64 RAM MOTOROLA

Technical Data — MC68HC908AZ60A

4.1 Contents

4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

4.3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

4.4 FLASH-1 Control and Block Protect Registers . . . . . . . . . .67

4.4.1 FLASH-1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . .67

4.4.2 FLASH-1 Block Protect Register. . . . . . . . . . . . . . . . . . . .68

4.5 FLASH-1 Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.6 FLASH-1 Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . .71

Section 4. FLASH-1 Memory

4.2 Introduction

4.7 FLASH-1 Page Erase Operation . . . . . . . . . . . . . . . . . . . . . .72

4.8 FLASH-1 Program Operation. . . . . . . . . . . . . . . . . . . . . . . . .73

4.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

4.9.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

4.9.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

This section describes the operation of the embedded FLASH-1
memory. This memory can be read, programmed and erased from a
single external supply. The program and erase operations are enabled
through the use of an internal charge pump.

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA FLASH-1 Memory 65

FLASH-1 Memory

4.3 Functional Description

The FLASH-1 memory is an array of 32,256 bytes with two bytes of block
protection (one byte for protecting areas within FLASH-1 array and one
byte for protecting areas within FLASH-2 array) and an additional 40
bytes of user vectors on the MC68HC908AS60A and 52 bytes of user
vectors on the MC68HC908AZ60A. An erased bit reads as a logic 1 and
a programmed bit reads as a logic 0.

Memory in the FLASH-1 array is organized into rows within pages. There
are two rows of memory per page with 64 bytes per row. The minimum
erase block size is a single page,128 bytes. Programming is performed
on a per-row basis, 64 bytes at a time. Program and erase operations
are facilitated through control bits in the FLASH-1 Control Register
(FL1CR). Details for these operations appear later in this section.

The FLASH-1 memory map consists of:

• $8000–$FDFF: User Memory (32,256 bytes)

• $FF80: FLASH-1 Block Protect Register (FL1BPR)

• $FF81: FLASH-2 Block Protect Register (FL2BPR)

• $FF88: FLASH-1 Control Register (FL1CR)

• $FFCC–$FFFF: these locations are reserved for user-defined
interrupt and reset vectors (Please see Vector Addresses and

Priority on page 61 for details)

Programming tools are available from Motorola. Contact your local
Motorola representative for more information.

NOTE: A security feature prevents viewing of the FLASH contents.

(1)

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.

Technical Data MC68HC908AZ60A — Rev 2.0

66 FLASH-1 Memory MOTOROLA

FLASH-1 Control and Block Protect Registers

4.4 FLASH-1 Control and Block Protect Registers

The FLASH-1 array has two registers that control its operation, the
FLASH-1 Control Register (FL1CR) and the FLASH-1 Block Protect
Register (FL1BPR).

4.4.1 FLASH-1 Control Register

The FLASH-1 Control Register (FL1CR) controls FLASH-1 program and
erase operations.

Address: $FF88

Bit 7654321Bit 0

FLASH-1 Memory

Read: 0000

HVEN MASS ERASE PGM

Write:

Reset:00000000

Figure 4-1. FLASH-1 Control Register (FL1CR)

HVEN — High-Voltage Enable Bit

This read/write bit enables the charge pump to drive high voltages for
program and erase operations in the array. HVEN can only be set if
either PGM = 1 or ERASE = 1 and the proper sequence for program
or erase is followed.

1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off

MASS — Mass Erase Control Bit

Setting this read/write bit configures the FLASH-1 array for mass or
page erase operation.

1 = Mass erase operation selected
0 = Page erase operation selected

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA FLASH-1 Memory 67

FLASH-1 Memory

ERASE — Erase Control Bit

This read/write bit configures the memory for erase operation.
ERASE is interlocked with the PGM bit such that both bits cannot be
set at the same time.

1 = Erase operation selected
0 = Erase operation unselected

PGM — Program Control Bit

This read/write bit configures the memory for program operation.
PGM is interlocked with the ERASE bit such that both bits cannot be
equal to 1 or set to 1 at the same time.

1 = Program operation selected
0 = Program operation unselected

4.4.2 FLASH-1 Block Protect Register

The FLASH-1 Block Protect Register (FL1BPR) is implemented as a
byte within the FLASH-1 memory and therefore can only be written
during a FLASH programming sequence. The value in this register
determines the starting location of the protected range within the
FLASH-1 memory.

Address: $FF80

Bit 7654321Bit 0

Read:

Write:

BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

Figure 4-2. FLASH-1 Block Protect Register (FL1BPR)

FL1BPR[7:0] — Block Protect Register Bit7 to Bit0

These eight bits represent bits [14:7] of a 16-bit memory address. Bit­15 is logic 1 and bits [6:0] are logic 0s.

Technical Data MC68HC908AZ60A — Rev 2.0

68 FLASH-1 Memory MOTOROLA

FLASH-1 Memory

FLASH-1 Control and Block Protect Registers

The resultant 16-bit address is used for specifying the start address
of the FLASH-1 memory for block protection. FLASH-1 is protected
from this start address to the end of FLASH-1 memory at $FFFF. With
this mechanism, the protect start address can be $XX00 and $XX80
(128 byte page boundaries) within the FLASH-1 array.

16-bit memory address

Start address of FLASH block protect

1

FLBPR value

0000000

Figure 4-3. FLASH-1 Block Protect Start Address

FLASH-1 Protected Ranges:

FL1BPR[7:0] Protected Range

$FF No Protection

$FE $FF00 – $FFFF

$FD $FE80 – $FFFF

$0B $8580 – $FFFF

$0A $8500 – $FFFF

$09 $8480 – $FFFF

$08 $8400 – $FFFF

$04 $8200 – $FFFF

$03 $8180 – $FFFF

$02 $8100 – $FFFF

$01 $8080 – $FFFF

$00 $8000 – $FFFF

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA FLASH-1 Memory 69

FLASH-1 Memory

Decreasing the value in FL1BPR by one increases the protected range
by one page (128 bytes). However, programming the block protect
register with $FE protects a range twice that size, 256 bytes, in the
corresponding array. $FE means that locations $FF00–$FFFF are
protected in FLASH-1.

The FLASH memory does not exist at some locations. The block
protection range configuration is unaffected if FLASH memory does not
exist in that range. Refer to the memory map and make sure that the
desired locations are protected.

4.5 FLASH-1 Block Protection

Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made for protecting
blocks of memory from unintentional erase or program operations due to
system malfunction. This protection is done by using the FLASH-1 Block
Protection Register (FL1BPR). FL1BPR determines the range of the
FLASH-1 memory which is to be protected. The range of the protected
area starts from a location defined by FL1BPR and ends at the bottom
of the FLASH-1 memory ($FFFF). When the memory is protected, the
HVEN bit can not be set in either ERASE or PROGRAM operations.

NOTE: In performing a program or erase operation, the FLASH-1 Block Protect

Register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.

When the FLASH-1 Block Protect Register is programmed with all 0’s,
the entire memory is protected from being programmed and erased.
When all the bits are erased (all 1’s), the entire memory is accessible for
program and erase.

When bits within FL1BPR are programmed (logic 0), they lock a block of
memory address ranges as shown in FLASH-1 Block Protect Register
on page 68. If FL1BPR is programmed with any value other than $FF,
the protected block of FLASH memory can not be erased or
programmed.

Technical Data MC68HC908AZ60A — Rev 2.0

70 FLASH-1 Memory MOTOROLA

NOTE: The vector locations and the FLASH Block Protect Registers are located

in the same page. FL1BPR and FL2BPR are not protected with special
hardware or software; therefore, if this page is not protected by FL1BPR
and the vector locations are erased by either a page or a mass erase
operation, both FL1BPR and FL2BPR will also get erased.

4.6 FLASH-1 Mass Erase Operation

Use this step-by-step procedure to erase the entire FLASH-1 memory to
read as logic 1:

1. Set both the ERASE bit and the MASS bit in the FLASH-1 Control
Register (FL1CR).

2. Read the FLASH-1 Block Protect Register (FL1BPR).

FLASH-1 Memory

FLASH-1 Mass Erase Operation

3. Write to any FLASH-1 address within the FLASH-1 array with any
data.

NOTE: If the address written to in Step 3 is within address space protected by

the FLASH-1 Block Protect Register (FL1BPR), no erase will occur.

4. Wait for a time, t

NVS

.

5. Set the HVEN bit.

6. Wait for a time, t

MERASE

.

7. Clear the ERASE bit.

8. Wait for a time, t

NVHL

.

9. Clear the HVEN bit.

10. Wait for a time, t

, after which the memory can be accessed in

RCV

normal read mode.

NOTE: A. Programming and erasing of FLASH locations can not be performed

by code being executed from the same FLASH array.

B. While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
however to ensure that these operations do not access any address

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA FLASH-1 Memory 71

FLASH-1 Memory

within the FLASH array memory space such as the COP Control
Register (COPCTL) at $FFFF.

C. It is highly recommended that interrupts be disabled during
program/erase operations.

4.7 FLASH-1 Page Erase Operation

Use this step-by-step procedure to erase a page (128 bytes) of FLASH­1 memory to read as logic 1:

1. Set the ERASE bit and clear the MASS bit in the FLASH-1 Control
Register (FL1CR).

2. Read the FLASH-1 Block Protect Register (FL1BPR).

3. Write any data to any FLASH-1 address within the address range
of the page (128 byte block) to be erased.

4. Wait for time, t

5. Set the HVEN bit.

6. Wait for time, t

.

NVS

ERASE

.

7. Clear the ERASE bit.

8. Wait for time, t

NVH

.

9. Clear the HVEN bit.

10. Wait for a time, t

, after which the memory can be accessed in

RCV

normal read mode.

NOTE: A. Programming and erasing of FLASH locations can not be performed

by code being executed from the same FLASH array.

B. While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
however to ensure that these operations do not access any address
within the FLASH array memory space such as the COP Control
Register (COPCTL) at $FFFF.

C. It is highly recommended that interrupts be disabled during
program/erase operations.

Technical Data MC68HC908AZ60A — Rev 2.0

72 FLASH-1 Memory MOTOROLA

4.8 FLASH-1 Program Operation

Programming of the FLASH memory is done on a row basis. A row
consists of 64 consecutive bytes with address ranges as follows:

• $XX00 to $XX3F

• $XX40 to $XX7F

• $XX80 to $XXBF

• $XXC0 to $XXFF

During the programming cycle, make sure that all addresses being
written to fit within one of the ranges specified above. Attempts to
program addresses in different row ranges in one programming cycle will
fail. Use this step-by-step procedure to program a row of FLASH-1
memory.

FLASH-1 Memory

FLASH-1 Program Operation

NOTE: In order to avoid program disturbs, the row must be erased before any

byte on that row is programmed.

1. Set the PGM bit in the FLASH-1 Control Register (FL1CR). This
configures the memory for program operation and enables the
latching of address and data programming.

2. Read the FLASH-1 Block Protect Register (FL1BPR).

3. Write to any FLASH-1 address within the row address range
desired with any data.

4. Wait for time, t

5. Set the HVEN bit.

6. Wait for time, t

7. Write data byte to the FLASH-1 address to be programmed.

8. Wait for time, t

9. Repeat step 7 and 8 until all the bytes within the row are
programmed.

.

NVS

.

PGS

PROG

.

10. Clear the PGM bit.

11. Wait for time, t

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA FLASH-1 Memory 73

NVH

.

FLASH-1 Memory

12. Clear the HVEN bit.

13. Wait for a time, t

, after which the memory can be accessed in

RCV

normal read mode.

The FLASH Programming Algorithm Flowchart is shown in Figure 4-4.

NOTE: A. Programming and erasing of FLASH locations can not be performed

by code being executed from the same FLASH array.

B. While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
however to ensure that these operations do not access any address
within the FLASH array memory space such as the COP Control
Register (COPCTL) at $FFFF.

C. It is highly recommended that interrupts be disabled during
program/erase operations.

D. Do not exceed t

PROG

maximum or t
cumulative high voltage programming time to the same row before next
erase. t

must satisfy this condition: t

HV

max. Please also see FLASH Memory Characteristics on page 543.

maximum. t

HV

+ t

NVS

NVH

+ t

PGS

is defined as the

HV

+ (t

PROG

X 64) ð t

HV

E. The time between each FLASH address change (step 7 to step 7), or
the time between the last FLASH address programmed to clearing the
PGM bit (step 7 to step 10) must not exceed the maximum programming
time, t

PROG

max.

F. Be cautious when programming the FLASH-1 array to ensure that
non-FLASH locations are not used as the address that is written to when
selecting either the desired row address range in step 3 of the algorithm
or the byte to be programmed in step 7 of the algorithm. This applies
particularly to:

• $FFD2-$FFD3 and $FFDA-$FFFF: Vector area on
MC68HC908AS60A (40 bytes)

• $FFCC-$FFFF: Vector area on MC68HC908AZ60A (52 bytes)

Technical Data MC68HC908AZ60A — Rev 2.0

74 FLASH-1 Memory MOTOROLA

FLASH-1 Memory

FLASH-1 Program Operation

Algorithm for programming
a row (64 bytes) of FLASH memory

1

2

Read the FLASH block protect register

3

Write any data to any FLASH address

Set PGM bit

within the row address range desired

4

5

6

7

Wait for a time, t

Set HVEN bit

Wait for a time, t

Write data to the FLASH address

to be programmed

8

Wait for a time, t

nvs

pgs

PROG

Completed

programming

Y

this row?

N

NOTE:

10

Clear PGM bit

The time between each FLASH address change (step 7 to step 7), or

the time between the last FLASH address programmed

to clearing PGM bit (step 7 to step 10)

11

Wait for a time, t

nvh

must not exceed the maximum programming
time, t

PROG

max.

12

Clear HVEN bit

This row program algorithm assumes the row/s
to be programmed are initially erased.

13

Wait for a time, t

rcv

End of programming

Figure 4-4. FLASH Programming Algorithm Flowchart

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA FLASH-1 Memory 75

FLASH-1 Memory

4.9 Low-Power Modes

The WAIT and STOP instructions will place the MCU in low power
consumption standby modes.

4.9.1 WAIT Mode

Putting the MCU into wait mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly; however, no
memory activity will take place since the CPU is inactive.

The WAIT instruction should not be executed while performing a
program or erase operation on the FLASH. Wait mode will suspend any
FLASH program/erase operations and leave the memory in a Standby
Mode.

4.9.2 STOP Mode

Putting the MCU into stop mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly; however, no
memory activity will take place since the CPU is inactive.

The STOP instruction should not be executed while performing a
program or erase operation on the FLASH. Stop mode will suspend any
FLASH program/erase operations and leave the memory in a Standby
Mode.

NOTE: Standby Mode is the power saving mode of the FLASH module, in which

all internal control signals to the FLASH are inactive and the current
consumption of the FLASH is minimum.

Technical Data MC68HC908AZ60A — Rev 2.0

76 FLASH-1 Memory MOTOROLA

Technical Data — MC68HC908AZ60A

5.1 Contents

5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

5.3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

5.4 FLASH-2 Control and Block Protect Registers . . . . . . . . . .79

5.4.1 FLASH-2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . .79

5.4.2 FLASH-2 Block Protect Register. . . . . . . . . . . . . . . . . . . .80

5.5 FLASH-2 Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . .82

5.6 FLASH-2 Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . .83

Section 5. FLASH-2 Memory

5.2 Introduction

5.7 FLASH-2 Page Erase Operation . . . . . . . . . . . . . . . . . . . . . .84

5.8 FLASH-2 Program Operation. . . . . . . . . . . . . . . . . . . . . . . . .85

5.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

5.9.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

5.9.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

This section describes the operation of the embedded FLASH-2
memory. This memory can be read, programmed and erased from a
single external supply. The program and erase operations are enabled
through the use of an internal charge pump.

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA FLASH-2 Memory 77

FLASH-2 Memory

5.3 Functional Description

The FLASH-2 memory is a non-continuos array consisting of a total of
29,616 bytes on the MC68HC908AS60A and 29,488 bytes on the
MC68HC908AZ60A. An erased bit reads as a logic 1 and a programmed
bit reads as a logic 0.

Memory in the FLASH-2 array is organized into rows within pages. There
are two rows of memory per page with 64 bytes per row. The minimum
erase block size is a single page,128 bytes. Programming is performed
on a per-row basis, 64 bytes at a time. Program and erase operations
are facilitated through control bits in the FLASH-2 Control Register
(FL2CR). Details for these operations appear later in this section.

The FLASH-2 memory map consists of:

• $0450–$05FF: User Memory on MC68HC908AS60A (432 bytes)

• $0450–$04FF: User Memory on MC68HC908AZ60A (176 bytes)

• $0580–$05FF: User Memory on MC68HC908AZ60A (128 bytes)

• $0E00–$7FFF: User Memory (29,616 bytes)

• $FF81: FLASH-2 Block Protect Register (FL2BPR)

– Note that FL2BPR physically resides within FLASH-1 memory

addressing space

• $FE08: FLASH-2 Control Register (FL2CR)

Programming tools are available from Motorola. Contact your local
Motorola representative for more information.

NOTE: A security feature prevents viewing of the FLASH contents.

(1)

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.

Technical Data MC68HC908AZ60A — Rev 2.0

78 FLASH-2 Memory MOTOROLA

FLASH-2 Control and Block Protect Registers

5.4 FLASH-2 Control and Block Protect Registers

The FLASH-2 array has two registers that control its operation, the
FLASH-2 Control Register (FL2CR) and the FLASH-2 Block Protect
Register (FL2BPR).

5.4.1 FLASH-2 Control Register

The FLASH-2 Control Register (FL2CR) controls FLASH-2 program and
erase operations.

Address: $FE08

Bit 7654321Bit 0

FLASH-2 Memory

Read: 0000

HVEN MASS ERASE PGM

Write:

Reset:00000000

Figure 5-1. FLASH-2 Control Register (FL2CR)

HVEN — High-Voltage Enable Bit

This read/write bit enables the charge pump to drive high voltages for
program and erase operations in the array. HVEN can only be set if
either PGM = 1 or ERASE = 1 and the proper sequence for program
or erase is followed.

1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off

MASS — Mass Erase Control Bit

Setting this read/write bit configures the FLASH-2 array for mass or
page erase operation.

1 = Mass erase operation selected
0 = Page erase operation selected

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA FLASH-2 Memory 79

FLASH-2 Memory

ERASE — Erase Control Bit

This read/write bit configures the memory for erase operation.
ERASE is interlocked with the PGM bit such that both bits cannot be
set at the same time.

1 = Erase operation selected
0 = Erase operation unselected

PGM — Program Control Bit

This read/write bit configures the memory for program operation.
PGM is interlocked with the ERASE bit such that both bits cannot be
equal to 1 or set to 1 at the same time.

1 = Program operation selected
0 = Program operation unselected

5.4.2 FLASH-2 Block Protect Register

The FLASH-2 Block Protect Register (FL2BPR) is implemented as a
byte within the FLASH-1 memory and therefore can only be written
during a FLASH programming sequence. The value in this register
determines the starting location of the protected range within the
FLASH-2 memory.

Address: $FF81

Bit 7654321Bit 0

Read:

Write:

BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

Figure 5-2. FLASH-2 Block Protect Register (FL2BPR)

NOTE: The FLASH-2 Block Protect Register (FL2BPR) controls the block

protection for the FLASH-2 array. However, FL2BPR is implemented
within the FLASH-1 memory array and therefore, the FLASH-1 Control
Register (FL1CR) must be used to program/erase FL2BPR.

FL2BPR[7:0] — Block Protect Register Bit7 to Bit0

These eight bits represent bits [14:7] of a 16-bit memory address. Bit­15 is logic 1 and bits [6:0] are logic 0s.

Technical Data MC68HC908AZ60A — Rev 2.0

80 FLASH-2 Memory MOTOROLA

FLASH-2 Memory

FLASH-2 Control and Block Protect Registers

The resultant 16-bit address is used for specifying the start address
of the FLASH-2 memory for block protection. FLASH-2 is protected
from this start address to the end of FLASH-2 memory at $7FFF. With
this mechanism, the protect start address can be $XX00 and $XX80
(128 byte page boundaries) within the FLASH-2 array.

16-bit memory address

Start address of FLASH block protect

1

FLBPR value

0000000

Figure 5-3. FLASH-2 Block Protect Start Address

FLASH-2 Protected Ranges:

FL2BPR[7:0] Protected Range

$FF No Protection

$FE $7F00 – $7FFF

$FD $7E80 – $7FFF

$0B $0580 – $7FFF

$0A $0500 – $7FFF

$09 $0480 – $7FFF

$08 $0450 – $7FFF

$04 $0450 – $7FFF

$03 $0450 – $7FFF

$02 $0450 – $7FFF

$01 $0450 – $7FFF

$00 $0450 – $7FFF

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA FLASH-2 Memory 81

FLASH-2 Memory

Decreasing the value in FL2BPR by one increases the protected range
by one page (128 bytes). However, programming the block protect
register with $FE protects a range twice that size, 256 bytes, in the
corresponding array. $FE means that locations $7F00–$7FFF are
protected in FLASH-2.

The FLASH memory does not exist at some locations. The block
protection range configuration is unaffected if FLASH memory does not
exist in that range. Refer to the memory map and make sure that the
desired locations are protected.

5.5 FLASH-2 Block Protection

Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made for protecting
blocks of memory from unintentional erase or program operations due to
system malfunction. This protection is done by using the FLASH-2 Block
Protection Register (FL2BPR). FL2BPR determines the range of the
FLASH-2 memory which is to be protected. The range of the protected
area starts from a location defined by FL2BPR and ends at the bottom
of the FLASH-2 memory ($7FFF). When the memory is protected, the
HVEN bit can not be set in either ERASE or PROGRAM operations.

NOTE: In performing a program or erase operation, the FLASH-2 Block Protect

Register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.

When the FLASH-2 Block Protect Register is programmed with all 0’s,
the entire memory is protected from being programmed and erased.
When all the bits are erased (all 1’s), the entire memory is accessible for
program and erase.

When bits within FL2BPR are programmed (logic 0), they lock a block of
memory address ranges as shown in FLASH-2 Block Protect Register
on page 80. If FL2BPR is programmed with any value other than $FF,
the protected block of FLASH memory can not be erased or
programmed.

Technical Data MC68HC908AZ60A — Rev 2.0

82 FLASH-2 Memory MOTOROLA

NOTE: The vector locations and the FLASH Block Protect Registers are located

in the same page. FL1BPR and FL2BPR are not protected with special
hardware or software; therefore, if this page is not protected by FL1BPR
and the vector locations are erased by either a page or a mass erase
operation, both FL1BPR and FL2BPR will also get erased.

5.6 FLASH-2 Mass Erase Operation

Use this step-by-step procedure to erase the entire FLASH-2 memory to
read as logic 1:

1. Set both the ERASE bit and the MASS bit in the FLASH-2 Control
Register (FL2CR).

2. Read the FLASH-2 Block Protect Register (FL2BPR).

FLASH-2 Memory

FLASH-2 Mass Erase Operation

3. Write to any FLASH-2 address within the FLASH-2 array with any
data.

NOTE: If the address written to in Step 3 is within address space protected by

the FLASH-2 Block Protect Register (FL2BPR), no erase will occur.

4. Wait for a time, t

NVS

.

5. Set the HVEN bit.

6. Wait for a time, t

MERASE

.

7. Clear the ERASE bit.

8. Wait for a time, t

NVHL

.

9. Clear the HVEN bit.

10. Wait for a time, t

, after which the memory can be accessed in

RCV

normal read mode.

NOTE: A. Programming and erasing of FLASH locations can not be performed

by code being executed from the same FLASH array.

B. While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
however to ensure that these operations do not access any address

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA FLASH-2 Memory 83

FLASH-2 Memory

within the FLASH array memory space such as the COP Control
Register (COPCTL) at $FFFF.

C. It is highly recommended that interrupts be disabled during
program/erase operations.

5.7 FLASH-2 Page Erase Operation

Use this step-by-step procedure to erase a page (128 bytes) of FLASH­2 memory to read as logic 1:

1. Set the ERASE bit and clear the MASS bit in the FLASH-2 Control
Register (FL2CR).

2. Read the FLASH-2 Block Protect Register (FL2BPR).

3. Write any data to any FLASH-2 address within the address range
of the page (128 byte block) to be erased.

4. Wait for time, t

5. Set the HVEN bit.

6. Wait for time, t

.

NVS

ERASE

.

7. Clear the ERASE bit.

8. Wait for time, t

NVH

.

9. Clear the HVEN bit.

10. Wait for a time, t

, after which the memory can be accessed in

RCV

normal read mode.

NOTE: A. Programming and erasing of FLASH locations can not be performed

by code being executed from the same FLASH array.

B. While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
however to ensure that these operations do not access any address
within the FLASH array memory space such as the COP Control
Register (COPCTL) at $FFFF.

C. It is highly recommended that interrupts be disabled during
program/erase operations.

Technical Data MC68HC908AZ60A — Rev 2.0

84 FLASH-2 Memory MOTOROLA

5.8 FLASH-2 Program Operation

Programming of the FLASH memory is done on a row basis. A row
consists of 64 consecutive bytes with address ranges as follows:

• $XX00 to $XX3F

• $XX40 to $XX7F

• $XX80 to $XXBF

• $XXC0 to $XXFF

During the programming cycle, make sure that all addresses being
written to fit within one of the ranges specified above. Attempts to
program addresses in different row ranges in one programming cycle will
fail. Use this step-by-step procedure to program a row of FLASH-2
memory.

FLASH-2 Memory

FLASH-2 Program Operation

NOTE: In order to avoid program disturbs, the row must be erased before any

byte on that row is programmed.

1. Set the PGM bit in the FLASH-2 Control Register (FL2CR). This
configures the memory for program operation and enables the
latching of address and data programming.

2. Read the FLASH-2 Block Protect Register (FL2BPR).

3. Write to any FLASH-2 address within the row address range
desired with any data.

4. Wait for time, t

5. Set the HVEN bit.

6. Wait for time, t

7. Write data byte to the FLASH-2 address to be programmed.

8. Wait for time, t

9. Repeat step 7 and 8 until all the bytes within the row are
programmed.

.

NVS

.

PGS

PROG

.

10. Clear the PGM bit.

11. Wait for time, t

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA FLASH-2 Memory 85

NVH

.

FLASH-2 Memory

12. Clear the HVEN bit.

13. Wait for a time, t

, after which the memory can be accessed in

RCV

normal read mode.

The FLASH Programming Algorithm Flowchart is shown in Figure 5-4.

NOTE: A. Programming and erasing of FLASH locations can not be performed

by code being executed from the same FLASH array.

B. While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
however to ensure that these operations do not access any address
within the FLASH array memory space such as the COP Control
Register (COPCTL) at $FFFF.

C. It is highly recommended that interrupts be disabled during
program/erase operations.

D. Do not exceed t

PROG

maximum or t
cumulative high voltage programming time to the same row before next
erase. t

must satisfy this condition: t

HV

max. Please also see FLASH Memory Characteristics on page 543.

maximum. t

HV

+ t

NVS

NVH

+ t

PGS

is defined as the

HV

+ (t

PROG

X 64) ð t

HV

E. The time between each FLASH address change (step 7 to step 7), or
the time between the last FLASH address programmed to clearing the
PGM bit (step 7 to step 10) must not exceed the maximum programming
time, t

PROG

max.

F. Be cautious when programming the FLASH-2 array to ensure that
non-FLASH locations are not used as the address that is written to when
selecting either the desired row address range in step 3 of the algorithm
or the byte to be programmed in step 7 of the algorithm. This applies
particularly to:

• $0450-$047F: First row of FLASH-2 (48 bytes)

Technical Data MC68HC908AZ60A — Rev 2.0

86 FLASH-2 Memory MOTOROLA

FLASH-2 Memory

FLASH-2 Program Operation

Algorithm for programming
a row (64 bytes) of FLASH memory

1

2

Read the FLASH block protect register

3

Write any data to any FLASH address

Set PGM bit

within the row address range desired

4

5

6

7

Wait for a time, t

Set HVEN bit

Wait for a time, t

Write data to the FLASH address

to be programmed

8

Wait for a time, t

nvs

pgs

PROG

Completed

programming

Y

this row?

N

NOTE:

10

Clear PGM bit

The time between each FLASH address change (step 7 to step 7), or

the time between the last FLASH address programmed

to clearing PGM bit (step 7 to step 10)

11

Wait for a time, t

nvh

must not exceed the maximum programming
time, t

PROG

max.

12

Clear HVEN bit

This row program algorithm assumes the row/s
to be programmed are initially erased.

13

Wait for a time, t

rcv

End of programming

Figure 5-4. FLASH Programming Algorithm Flowchart

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA FLASH-2 Memory 87

FLASH-2 Memory

5.9 Low-Power Modes

The WAIT and STOP instructions will place the MCU in low power
consumption standby modes.

5.9.1 WAIT Mode

Putting the MCU into wait mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly; however, no
memory activity will take place since the CPU is inactive.

The WAIT instruction should not be executed while performing a
program or erase operation on the FLASH. Wait mode will suspend any
FLASH program/erase operations and leave the memory in a Standby
Mode.

5.9.2 STOP Mode

Putting the MCU into stop mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly; however, no
memory activity will take place since the CPU is inactive.

The STOP instruction should not be executed while performing a
program or erase operation on the FLASH. Stop mode will suspend any
FLASH program/erase operations and leave the memory in a Standby
Mode.

NOTE: Standby Mode is the power saving mode of the FLASH module, in which

all internal control signals to the FLASH are inactive and the current
consumption of the FLASH is minimum.

Technical Data MC68HC908AZ60A — Rev 2.0

88 FLASH-2 Memory MOTOROLA

Technical Data — MC68HC908AZ60A

6.1 Contents

6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

6.4 EEPROM-1 Register Summary . . . . . . . . . . . . . . . . . . . . . . .91

6.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

6.5.1 EEPROM-1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . .92

6.5.2 EEPROM-1 Timebase Requirements . . . . . . . . . . . . . . . .93

6.5.3 EEPROM-1 Program/Erase Protection . . . . . . . . . . . . . . .93

6.5.4 EEPROM-1 Block Protection . . . . . . . . . . . . . . . . . . . . . . .94

6.5.5 EEPROM-1 Programming and Erasing. . . . . . . . . . . . . . .95

6.6 EEPROM-1 Register Descriptions. . . . . . . . . . . . . . . . . . . . .99

6.6.1 EEPROM-1 Control Register . . . . . . . . . . . . . . . . . . . . . . .99

6.6.2 EEPROM-1 Array Configuration Register . . . . . . . . . . .101

6.6.3 EEPROM-1 Nonvolatile Register. . . . . . . . . . . . . . . . . . .103

6.6.4 EEPROM-1 Timebase Divider Register . . . . . . . . . . . . .104

6.6.5 EEPROM-1 Timebase Divider Non-Volatile Register . .106

Section 6. EEPROM-1 Memory

6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

6.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA EEPROM-1 Memory 89

EEPROM-1 Memory

6.2 Introduction

6.3 Features

This section describes the 512 bytes of electrically erasable
programmable read-only memory (EEPROM) residing at address range
$0800 to $09FF. There are 1024 bytes of EEPROM available on the
MC68HC908AS60A and MC68HC908AZ60A which are physically
located in two 512 byte arrays. For information relating to the array
covering address range $0600 to $07FF please see EEPROM-2

Memory on page 109.

Features of the EEPROM-1 include the following:

• 512 bytes Non-Volatile Memory

• Byte, Block, or Bulk Erasable

• Non-Volatile EEPROM Configuration and Block Protection
Options

• On-chip Charge Pump for Programming/Erasing

• Security Option

• AUTO Bit Driven Programming/Erasing Time Feature

Technical Data MC68HC908AZ60A — Rev 2.0

90 EEPROM-1 Memory MOTOROLA

EEPROM-1 Memory

EEPROM-1 Register Summary

6.4 EEPROM-1 Register Summary

The EEPROM-1 Register Summary is shown in Figure 6-1.

Addr.Register Name Bit 7654321Bit 0

EE1DIV Non-volatile

$FE10

EE1DIV Non-volatile

$FE11

EE1 Divider Register High

$FE1A

$FE1B

$FE1C

EE1 Divider Register Low

EEPROM-1 Non-volatile

Register High

(EE1DIVHNVR)*

Register Low

(EE1DIVLNVR)*

(EE1DIVH)

(EE1DIVL)

Register

(EE1NVR)*

Read:

EEDIVSECD

Write:

Reset: Unaffected by reset; $FF when blank

Read:

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

Write:

Reset: Unaffected by reset; $FF when blank

Read:

EEDIVSECD

Write:

Reset: Contents of EE1DIVHNVR ($FE10), Bits [6:3] = 0

Read:

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

Write:

Reset: Contents of EE1DIVLNVR ($FE11)

Read:

UNUSED UNUSED UNUSED EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0

Write:

Reset: Unaffected by reset; $FF when blank; factory programmed $F0

RRRREEDIV10EEDIV9EEDIV8

0000

EEDIV10 EEDIV9 EEDIV8

EEPROM-1 Control

$FE1D

EEPROM-1 Array

$FE1F

* Non-volatile EEPROM register; write by programming.

Configuration Register

Register

(EE1CR)

(EE1ACR)

Read:

UNUSED

Write:

Reset:00000000

Read: UNUSED UNUSED UNUSED EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0

Write:

Reset: Contents of EE1NVR ($FE1C)

0

EEOFF EERAS1 EERAS0 EELAT AUTO EEPGM

= Unimplemented R = Reserved UNUSED = Unused

Figure 6-1. EEPROM-1 Register Summary

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA EEPROM-1 Memory 91

EEPROM-1 Memory

6.5 Functional Description

The 512 bytes of EEPROM-1 are located at $0800-$09FF and can be
programmed or erased without an additional external high voltage
supply. The program and erase operations are enabled through the use
of an internal charge pump. For each byte of EEPROM, the write/erase
endurance is 10,000 cycles.

6.5.1 EEPROM-1 Configuration

The 8-bit EEPROM-1 Non-Volatile Register (EE1NVR) and the 16-bit
EEPROM-1 Timebase Divider Non-Volatile Register (EE1DIVNVR)
contain the default settings for the following EEPROM configurations:

• EEPROM-1 Timebase Reference

• EEPROM-1 Security Option

• EEPROM-1 Block Protection

EE1NVR and EE1DIVNVR are non-volatile EEPROM registers. They
are programmed and erased in the same way as EEPROM bytes. The
contents of these registers are loaded into their respective volatile
registers during a MCU reset. The values in these read/write volatile
registers define the EEPROM-1 configurations.

For EE1NVR, the corresponding volatile register is the EEPROM-1
Array Configuration Register (EE1ACR). For the EE1DIVNCR (two 8-bit
registers: EE1DIVHNVR and EE1DIVLNVR), the corresponding volatile
register is the EEPROM-1 Divider Register (EE1DIV: EE1DIVH and EE1
DIVL).

Technical Data MC68HC908AZ60A — Rev 2.0

92 EEPROM-1 Memory MOTOROLA

6.5.2 EEPROM-1 Timebase Requirements

A 35µs timebase is required by the EEPROM-1 control circuit for
program and erase of EEPROM content. This timebase is derived from
dividing the CGMXCLK or bus clock (selected by EEDIVCLK bit in
CONFIG-2 Register) using a timebase divider circuit controlled by the
16-bit EEPROM-1 Timebase Divider EE1DIV Register (EE1DIVH and
EE1DIVL).

As the CGMXCLK or bus clock is user selected, the EEPROM-1
Timebase Divider Register must be configured with the appropriate
value to obtain the 35 µs. The timebase divider value is calculated by
using the following formula:

EE1DIV= INT[Reference Frequency(Hz) x 35 x10

This value is written to the EEPROM-1 Timebase Divider Register
(EE1DIVH and EE1DIVL) or programmed into the EEPROM-1
Timebase Divider Non-Volatile Register prior to any EEPROM program
or erase operations(see EEPROM-1 Configuration on page 92 and

EEPROM-1 Timebase Requirements on page 93).

EEPROM-1 Memory

Functional Description

-6

+0.5]

6.5.3 EEPROM-1 Program/Erase Protection

The EEPROM has a special feature that designates the 16 bytes of
addresses from $08F0 to $08FF to be permanently secured. This
program/erase protect option is enabled by programming the EEPRTCT
bit in the EEPROM-1 Non-Volatile Register (EE1NVR) to a logic zero.

Once the EEPRTCT bit is programmed to 0 for the first time:

• Programming and erasing of secured locations $08F0 to $08FF is
permanently disabled.

• Secured locations $08F0 to $08FF can be read as normal.

• Programming and erasing of EE1NVR is permanently disabled.

• Bulk and Block Erase operations are disabled for the unprotected
locations $0800-$08EF, $0900-$09FF.

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA EEPROM-1 Memory 93

EEPROM-1 Memory

• Single byte program and erase operations are still available for
locations $0800-$08EF and $0900-$09FF for all bytes that are not
protected by the EEPROM-1 Block Protect EEBPx bits (see

EEPROM-1 Block Protection on page 94 and EEPROM-1 Array
Configuration Register on page 101)

NOTE: Once armed, the protect option is permanently enabled. As a

consequence, all functions in the EE1NVR will remain in the state they
were in immediately before the security was enabled.

6.5.4 EEPROM-1 Block Protection

The 512 bytes of EEPROM-1 are divided into four 128-byte blocks. Each
of these blocks can be protected from erase/program operations by
setting the EEBPx bit in the EE1NVR. Table 6-1 shows the address
ranges for the blocks.

Table 6-1. EEPROM-1 Array Address Blocks

Block Number (EEBPx) Address Range

EEBP0 $0800–$087F

EEBP1 $0880–$08FF

EEBP2 $0900–$097F

EEBP3 $0980–$09FF

These bits are effective after a reset or a upon read of the EE1NVR
register. The block protect configuration can be modified by
erasing/programming the corresponding bits in the EE1NVR register
and then reading the EE1NVR register. Please see EEPROM-1 Array

Configuration Register on page 101 for more information.

NOTE: Once EEDIVSECD in the EE1DIVHNVR is programmed to 0 and after a

system reset, the EE1DIV security feature is permanently enabled
because the EEDIVSECD bit in the EE1DIVH is always loaded with 0
thereafter. Once this security feature is armed, erase and program mode
are disabled for EE1DIVHNVR and EE1DIVLNVR. Modifications to the
EE1DIVH and EE1DIVL registers are also disabled. Therefore, be
cautious on programming a value into the EE1DIVHNVR.

Technical Data MC68HC908AZ60A — Rev 2.0

94 EEPROM-1 Memory MOTOROLA

6.5.5 EEPROM-1 Programming and Erasing

The unprogrammed or erase state of an EEPROM bit is a logic 1. The
factory default for all bytes within the EEPROM-1 array is $FF.

The programming operation changes an EEPROM bit from logic 1 to
logic 0 (programming cannot change a bit from logic 0 to a logic 1). In a
single programming operation, the minimum EEPROM programming
size is one bit; the maximum is eight bits (one byte).

The erase operation changes an EEPROM bit from logic 0 to logic 1. In
a single erase operation, the minimum EEPROM erase size is one byte;
the maximum is the entire EEPROM-1 array.

The EEPROM can be programmed such that one or multiple bits are
programmed (written to a logic 0) at a time. However, the user may never
program the same bit location more than once before erasing the entire
byte. In other words, the user is not allowed to program a logic 0 to a bit
that is already programmed (bit state is already logic 0).

EEPROM-1 Memory

Functional Description

For some applications it might be advantageous to track more than 10K
events with a single byte of EEPROM by programming one bit at a time.
For that purpose, a special selective bit programming technique is
available. An example of this technique is illustrated in Table 6-2.

Table 6-2. Example Selective Bit Programming Description

Description

Original state of byte (erased) n/a 1111:1111

First event is recorded by programming bit position 0 1111:1110 1111:1110

Second event is recorded by programming bit position 1 1111:1101 1111:1100

Third event is recorded by programming bit position 2 1111:1011 1111:1000

Fourth event is recorded by programming bit position 3 1111:0111 1111:0000

Events five through eight are recorded in a similar fashion

Program Data

in Binary

Result

in Binary

Note that none of the bit locations are actually programmed more than
once although the byte was programmed eight times.

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA EEPROM-1 Memory 95

EEPROM-1 Memory

When this technique is utilized, a program/erase cycle is defined as
multiple program sequences (up to eight) to a unique location followed
by a single erase operation.

Program/Erase
Using AUTO Bit

EEPROM-1
Programming

An additional feature available for EEPROM-1 program and erase
operations is the AUTO mode. When enabled, AUTO mode will activate
an internal timer that will automatically terminate the program/erase
cycle and clear the EEPGM bit. Please see EEPROM-1 Programming
on page 96, EEPROM-1 Erasing on page 97 and EEPROM-1 Control

Register on page 99 for more information.

The unprogrammed or erase state of an EEPROM bit is a logic 1.
Programming changes the state to a logic 0. Only EEPROM bytes in the
non-protected blocks and the EE1NVR register can be programmed.

Use the following procedure to program a byte of EEPROM:

1. Clear EERAS1 and EERAS0 and set EELAT in the EE1CR.

NOTE: If using the AUTO mode, also set the AUTO bit during Step 1.

2. Write the desired data to the desired EEPROM address.

3. Set the EEPGM bit.

(C)

Go to Step 7 if AUTO is set.

(A)

(B)

4. Wait for time, t

EEPGM

, to program the byte.

5. Clear EEPGM bit.

6. Wait for time, t

EEFPV

, for the programming voltage to fall. Go to

Step 8.

7. Poll the EEPGM bit until it is cleared by the internal timer.

8. Clear EELAT bits.

(E)

(D)

NOTE: A. EERAS1 and EERAS0 must be cleared for programming. Setting the

EELAT bit configures the address and data buses to latch data for
programming the array. Only data with a valid EEPROM-1 address will
be latched. If EELAT is set, other writes to the EE1CR will be allowed
after a valid EEPROM-1 write.

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96 EEPROM-1 Memory MOTOROLA

EEPROM-1 Memory

Functional Description

B. If more than one valid EEPROM write occurs, the last address and
data will be latched overriding the previous address and data. Once data
is written to the desired address, do not read EEPROM-1 locations other
than the written location. (Reading an EEPROM location returns the
latched data and causes the read address to be latched).

C. The EEPGM bit cannot be set if the EELAT bit is cleared or a non­valid EEPROM address is latched. This is to ensure proper
programming sequence. Once EEPGM is set, do not read any
EEPROM-1 locations; otherwise, the current program cycle will be
unsuccessful. When EEPGM is set, the on-board programming
sequence will be activated.

D. The delay time for the EEPGM bit to be cleared in AUTO mode is less
than t

EEPGM

. However, on other MCUs, this delay time may be different.
For forward compatibility, software should not make any dependency on
this delay time.

E. Any attempt to clear both EEPGM and EELAT bits with a single
instruction will only clear EEPGM. This is to allow time for removal of
high voltage from the EEPROM-1 array.

EEPROM-1 Erasing The programmed state of an EEPROM bit is logic 0. Erasing changes

the state to a logic 1. Only EEPROM-1 bytes in the non-protected blocks
and the EE1NVR register can be erased.

Use the following procedure to erase a byte, block or the entire
EEPROM-1 array:

1. Configure EERAS1 and EERAS0 for byte, block or bulk erase; set
EELAT in EE1CR.

(A)

NOTE: If using the AUTO mode, also set the AUTO bit in Step 1.

2. Byte erase: write any data to the desired address.

Block erase: write any data to an address within the desired
block.

(B)

(B)

Bulk erase: write any data to an address within the array.

3. Set the EEPGM bit.

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MOTOROLA EEPROM-1 Memory 97

(C)

Go to Step 7 if AUTO is set.

(B)

EEPROM-1 Memory

4. Wait for a time: t
t

EEBULK.

for bulk erase.

EEBYTE

for byte erase; t

EEBLOCK

for block erase;

5. Clear EEPGM bit.

6. Wait for a time, t

EEFPV

7. Poll the EEPGM bit until it is cleared by the internal timer.

8. Clear EELAT bits.

, for the erasing voltage to fall. Go to Step 8.

(D)

(E)

NOTE: A. Setting the EELAT bit configures the address and data buses to latch

data for erasing the array. Only valid EEPROM-1 addresses will be
latched. If EELAT is set, other writes to the EE1CR will be allowed after
a valid EEPROM-1 write.

B. If more than one valid EEPROM write occurs, the last address and
data will be latched overriding the previous address and data. Once data
is written to the desired address, do not read EEPROM-1 locations other
than the written location. (Reading an EEPROM location returns the
latched data and causes the read address to be latched).

C. The EEPGM bit cannot be set if the EELAT bit is cleared or a non­valid EEPROM address is latched. This is to ensure proper
programming sequence. Once EEPGM is set, do not read any
EEPROM-1 locations; otherwise, the current program cycle will be
unsuccessful. When EEPGM is set, the on-board programming
sequence will be activated.

D. The delay time for the EEPGM bit to be cleared in AUTO mode is less
than t

EEBYTE /tEEBLOCK/tEEBULK

. However, on other MCUs, this delay
time may be different. For forward compatibility, software should not
make any dependency on this delay time.

E. Any attempt to clear both EEPGM and EELAT bits with a single
instruction will only clear EEPGM. This is to allow time for removal of
high voltage from the EEPROM-1 array.

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6.6 EEPROM-1 Register Descriptions

Four I/O registers and three non-volatile registers control program, erase
and options of the EEPROM-1 array.

6.6.1 EEPROM-1 Control Register

This read/write register controls programming/erasing of the array.

Address: $FE1D

Bit 7654321Bit 0

EEPROM-1 Memory

EEPROM-1 Register Descriptions

Read:

UNUSED

Write:

Reset:00000000

0

EEOFF EERAS1 EERAS0 EELAT AUTO EEPGM

= Unimplemented

Figure 6-2. EEPROM-1 Control Register (EE1CR)

Bit 7— Unused bit

This read/write bit is software programmable but has no functionality.

EEOFF — EEPROM-1 power down

This read/write bit disables the EEPROM-1 module for lower power
consumption. Any attempts to access the array will give unpredictable
results. Reset clears this bit.

1 = Disable EEPROM-1 array
0 = Enable EEPROM-1 array

EERAS1 and EERAS0 — Erase/Program Mode Select Bits

These read/write bits set the erase modes. Reset clears these bits.

Table 6-3. EEPROM-1 Program/Erase Mode Select

EEBPx EERAS1 EERAS0 MODE

000Byte Program

001Byte Erase

010Block Erase

0 1 1 Bulk Erase

1 X X No Erase/Program

X = don’t care

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EEPROM-1 Memory

EELAT — EEPROM-1 Latch Control

This read/write bit latches the address and data buses for
programming the EEPROM-1 array. EELAT cannot be cleared if
EEPGM is still set. Reset clears this bit.

1 = Buses configured for EEPROM-1 programming or erase

operation

0 = Buses configured for normal operation

AUTO — Automatic termination of program/erase cycle

When AUTO is set, EEPGM is cleared automatically after the
program/erase cycle is terminated by the internal timer.

(See note D for EEPROM-1 Programming on page 96, EEPROM-1

Erasing on page 97 and EEPROM Memory Characteristics on

page 542)

1 = Automatic clear of EEPGM is enabled
0 = Automatic clear of EEPGM is disabled

EEPGM — EEPROM-1 Program/Erase Enable

This read/write bit enables the internal charge pump and applies the
programming/erasing voltage to the EEPROM-1 array if the EELAT
bit is set and a write to a valid EEPROM-1 location has occurred.
Reset clears the EEPGM bit.

1 = EEPROM-1 programming/erasing power switched on
0 = EEPROM-1 programming/erasing power switched off

NOTE: Writing logic 0s to both the EELAT and EEPGM bits with a single

instruction will clear EEPGM only to allow time for the removal of high
voltage.

Technical Data MC68HC908AZ60A — Rev 2.0

100 EEPROM-1 Memory MOTOROLA