Datasheet MC68160AFB Datasheet (Motorola)

Enhanced Ethernet Transceiver

The MC68160A Enhanced Ethernet Interface Circuit is a BiCMOS device
which supports both IEEE 802.3 Access Unit Interface (AUI) and 10BASE–T
Twisted Pair (TP) Interface media connections through external isolation
transformers. It encodes NRZ data to Manchester data and supplies the
signals which are required for data communication via 10BASE–T or AUI
interfaces. The MC68160A gluelessly interface to the Ethernet controller
contained in the MC68360 Quad Integrated Communications Controller
(QUICC) device. The MC68160A also interfaces easily to most other
industry–standard IEEE 802.3 LAN controllers. Prior to twisted pair data
reception, Smart Squelch circuitry qualifies input signals for correct
amplitude, pulse width, and sequence requirements.

• Automatic Twisted Pair Wiring Polarity Fault Detection and Correction

Option

• Automatic Port Selection Option with Status Output

• Driver Pre–emphasis for Twisted Pair Output Data

Order this document by MC68160A/D

MC68160A

ENHANCED ETHERNET

INTERFACE TRANSCEIVER

SEMICONDUCTOR

TECHNICAL DATA

• Crystal Controlled Clock Oscillator or External Clock Generator Option

• Digital Phase–Locked–Loop (DPLL) Timing Recovery and Data Decoding

• Standby Mode with Reduced Power Consumption

• Twisted Pair Signal Quality Error (Heartbeat) Test Option

• Diagnostic Local Loop Back Option

• Transmit, Receive and Collision Detection Status Output

• Full–Duplex Operation Option on Twisted Pair Port

• Twisted Pair Jabber Detection and Status Output

• Link Integrity Testing and Status Output

The sale and use of this product is licensed under technology covered by one
or more Digital Equipment Corporation patents.

52 1

FB SUFFIX

PLASTIC PACKAGE

CASE 848D

(LQFP–52)

ORDERING INFORMATION

Operating

Device

MC68160AFB TA = 0° to + 70°C LQFP

Temperature Range

Package

 Motorola, Inc. 2000 Rev 1

MC68160A

Figure 1. 10Base–T Interface Block Diagram

RX

RCLK

MFILT

RXLED

RENA

CLLED

CLSN

TXLED

TENA

TX
X1

SIA INTERFACE

X2

TCLK

CS0
CS1
CS2

TPEN

APORT
TPAPCE
TPSQEL

TPFULDL

LOOP

Pulse Conditioner

Pulse Conditioner

Pulse

Conditioner

Mode

Select

Manchester

Encoder

20 MHz

Osc

÷2

Jabber
Control

TPJABB

Manchester

Decoder

Carrier
Detect

Mux

Mux

Driver

Pre–emphasis

Control

This device contains 20,000 active transistors.

Link

Pulse

Control

Mux

Collision

Detect

Collision
Detector

Control

Squelch

Test

Circuit

Mux

Receiver

Mux

TPRX– TPRX+TPSQELTPLILTPTX–TPTX+

Receiver

Squelch

Data

Receiver

Noise

Reject

Filter

Noise

Reject

Filter

ARX+

ARX–

ACX+
ACX–

ATX–

ATX+

Twisted

Pair

Polarity

Error

Control

TPPLR

AUI INTERFACE

2

MOTOROLA ANALOG IC DEVICE DATA

MC68160A

Enhanced Ethernet Serial Transceiver

Table 1. Pin Descriptions 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Controller Interface Pins 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AUI Interface Pins 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Twisted Pair Interface Pins 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Oscillator and Frequency Multiplier Pins 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Mode Select Pins 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Status Indicator Pins 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supply and Ground Pins 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 2. Controller Interface Selection 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3. Controller Independent Mode Selection 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Ratings 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ESD 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC Characteristics 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supply DC Characteristics 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TTL/CMOS Input and Output DC Characteristics 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Twisted Pair Input and Output DC Characteristics 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AUI Input and Output DC Characteristics 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AC Characteristics 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Clock Input (X1) Switching Characteristics 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive Phase Locked Loop Switching Characteristics 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Controller Transmit Switching Characteristics (Motorola Mode) 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Controller Receive Switching Characteristics (Motorola Mode) 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Controller Transmit Switching Characteristics (Intel Mode) 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Controller Receive Switching Characteristics (Intel Mode) 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Controller Transmit Switching Characteristics (Fujitsu Mode) 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Controller Receive Switching Characteristics (Fujitsu Mode) 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Controller Transmit Switching Characteristics (National Mode) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Controller Receive Switching Characteristics (National Mode) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TP Transmit Switching Characteristics 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TP Transmit Jabber Switching Characteristics 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TP Transmit Signal Quality Error Test Switching Characteristics 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TP Receive Switching Characteristics 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TP Receive Link Integrity Switching Characteristics 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TP Collision Switching Characteristics 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TP Full Duplex Switching Characteristics 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AUI Transmit Switching Characteristics 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AUI Receive Switching Characteristics 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Description 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Transmission 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Reception 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Collision 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Jabber 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Full Duplex 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Auto Port Selection 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Auto Polarity Selection 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Loop Back Mode 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Applications 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Selection of Crystal and External Components 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL Filter Components 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10BASE–T Filter and Transformer Choice 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AUI Transformer Choice 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MOTOROLA ANALOG IC DEVICE DATA

3

MC68160A

T able 1. Pin Function Descriptiont

Pin(s) Symbol Type Name/Function

CONTROLLER INTERFACE

1 RENA O

TTL/CMO

2 RX O

TTL/CMOS

48 TCLK O

TTL/CMOS

49 TENA I

TTL

50 RCLK O

TTL/CMOS

51 CLSN O

TTL/CMOS

52 TX I

TTL

Receive Enable Output: Indication of the presence of network activity , synchronous to
RCLK. In the standby mode, RENA is driven to the high impedance state.

Receive Data Output: Recovered data, synchronous to RCLK. Following a reset operation,
100 ms should be allowed before attempting to read data processed by the MC68160A, B
and C. This delay is needed to insure that the receive phase locked loop is properly
synchronized with incoming data. In the standby mode, RX is driven to the high impedance
state.

Transmit Clock Output CMOS/TTL Output: TCLK provides a symmetrical clock signal at
10 MHz for reference timing of data to be encoded. In the standby mode, TCLK is driven to
the high impedance state.

Transmit Enable Input: Input signal synchronous to TCLK which enables data transmission
on the active port. An internal pull–down resistor is provided so that the input is low under no
connect conditions. (This resistor is removed in the standby mode). If TENA is asserted at
the conclusion of a reset operation, it must first be deasserted and then reasserted before
data transmission can occur. In the standby mode, TENA is driven to the high impedance
state.

Receive Clock Output: Recovered clock. In the standby mode, RCLK is driven to the high
impedance state.

Collision Output: In the AUI mode, indicates the presence of signals at the ACX+ and
ACX– terminals which meet threshold and pulse width requirements. In the TP mode,
indicates simultaneous transmit and receive activity, a heartbeat (SQE Test) signal was
generated, or the jabber timer has expired. In the standby mode, CLSN is driven to the high
impedance state.

Transmit Data Input: Input signal synchronous to TCLK which provides NRZ serial data to
be Manchester encoded. In the standby mode, TX is driven to the high impedance state.

AUI INTERFACE

21
22

23
24

25
26

ACX–
ACX+

ARX–
ARX+

ATX–

ATX+

I AUI Differential Collision Inputs: These inputs are connected to a pair of internally biased

line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to
detect the line activity. Signals at ACX+/– have no ef fect on data path functions.

I AUI Differential Receiver Inputs: These inputs are connected to a pair of internally biased

line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to
detect the line activity, and a data receiver with no of fset for Manchester Data reception.

O AUI Differential Transmit Outputs : This line pair is intended to operate into terminated

transmission lines. For TX signals meeting setup and hold time to TCLK when TENA is
previously asserted, Manchester encoded data is outputted at ATX+/–. When operating into a
78 Ω terminated transmission line, signaling meets the required output levels and skew for
IEEE–802.3 drop cables. When the 10BASE–T port is automatically or manually selected,
the AUI outputs are driven to a low power standby state in which the outputs deliver a
balanced high state voltage.

TWISTED PAIR INTERFACE

31
32

36
37

NOTE: The sense of the controller interface pins will change, depending on the controller selected.

TPRX–
TPRX+

TPTX–
TPTX+

I Twisted Pair Differential Receiver Inputs: These inputs are connected to a receiver with

Smart Squelch capability which only allows differential receive data to pass as long as the
input amplitude is greater than a minimum signal threshold level and a specific pulse
sequence is received. This assures a good signal to noise ratio while the signal pair is active
by preventing crosstalk and impulse noise conditions from activating the receive function.

O Twisted Pair Differential Transmitter Outputs: These lines have pre–distortion drive

capability and are intended to drive terminated twisted pair transmission lines. When the AUI
port is manually selected, the 10BASE–T outputs are driven to a low power standby state in
which the outputs deliver a balanced high state voltage. However, when the AUI port is
automatically selected, the 10BASE–T outputs remain active.

4

MOTOROLA ANALOG IC DEVICE DATA

MC68160A

T able 1. Pin Function Description (continued)

Pin(s) Symbol Type Name/Function

OSCILLATOR AND FREQUENCY MULTIPLIER

12 MFILT C Frequency Multiplier Filter Connection Point: An external resistor capacitor filter must be

16 X1 I/C

17 X2 O/C

CMOS

CMOS

MODE SELECT

3
4
5

6 LOOP I

9 APORT I

27 TPSQEL I

28 TPFULDL I

29 TPAPCE I

46 TPEN I/O

CS0
CS1
CS2

I

TTL

TTL

TTL

TTL

TTL

TTL

TTL

(TTL/CMOS)

attached to this pin.
Oscillator Inverter Input and Crystal Connection Point: When connected for crystal

oscillator operation, the frequency of the clock which appears at TCLK is half that of the
crystal oscillator. As an option, instead of connecting to a crystal, X1 may be driven from an
external 20 MHz CMOS compatible clock generator.

Oscillator Inverter Output and Crystal Connection Point: This pin is used only for the
connection of an external crystal and capacitor. It must be left unconnected if X1 is driven by
an external CMOS Clock generator.

Mode Select: The logic states applied to these pins select the appropriate interface for the
desired IEEE–802.3 controller or enable the standby mode. When the standby mode is
selected, the MC68160A power supply current is greatly reduced. Additionally, in the standby
mode, all of the controller inputs and outputs are driven to the high impedance state.

Diagnostic Loopback: Asserting this function causes serial NRZ data at the TX input to be
Manchester encoded and then looped back through the Manchester decoder, appearing at
the RX output. This diagnostic loopback function operates independent of Twisted Pair (TP)
or Access Unit Interface (AUI) port connectivity or activity. Neither the TP port nor the AUI
port transmits data from the controller while diagnostic loopback is selected. Likewise, the
controller interface receives data neither from the TP nor the AUI receivers while in this
mode. The polarity fault detection and link integrity functions are not inhibited by the
diagnostic loopback mode. If otherwise enabled, they continue to function. If the twisted pair
port is selected, and TPSQEL is driven to the low logic state, a collision detect pulse is
delivered following each transmission to simulate the twisted pair SQE test.

Automatic Port Selection Enable: When high, MC68160A will automatically select the TP
or AUI port based on the presence or absence of valid link beats or frames at the TP receive
input. If the AUI port is automatically selected, the MC68160A will continue to produce link
pulses for the TP port. Changing ports requires approximately 1.0 ms to allow the circuitry for
the new port to resume normal operation. The power consumption is minimized in the
circuitry associated with the unselected port.

Twisted Pair Signal Quality Error Test Enable: Forcing this pin low enables testing of the
internal TP collision detect circuitry after each transmit operation to the TP media. This
function provides a simulated collision to as much of the MC68160A collision detect circuitry
as possible without affecting the attached twisted pair channel. A normal SQE test results in
a high logic state at the CLSN controller interface pin which begins 6 to 16–bit times after the
last transition of a transmitted signal and continues for 5 to 15–bit times. (When the AUI port
is selected, SQE test signals are generated by the coaxial cable transceiver and delivered to
the controller via the MC68160A ACX+/– receive inputs)

Twisted Pair Full Duplex Mode Select: Forcing this pin low allows simultaneous transmit
and receive operation on the twisted pair port without an indicated collision. This pin is not to
be asserted with LOOP as a test mode is enabled that disrupts normal operation.

Twisted Pair Automatic Polarity Correction Enable: When TPAPCE is high, automatic
polarity correction is enabled, and MC68160A will internally correct for a polarity fault on the
receive circuit. Additionally, when TPAPCE is high, the presence of a polarity fault is
indicated on TPPLR.

Twisted Pair Port Enable: If APOR T is low, TPEN is an input which determines whether the
AUI port (TPEN low) or TP port (TPEN high) will be manually selected. If the AUI port is
manually selected, the MC68160A will not produce link pulses for the TP port.

If APORT is high, TPEN is an output which will indicate which port has been automatically
selected by driving TPEN low (for AUI) or high (for TP). In its output mode TPEN can sink
10 mA in the low output state and source 10 mA in the high output state. (See Pin 9
Description.)

Changing ports requires approximately 1.0 ms to allow the circuitry for the new port to
resume normal operation. The power consumption is minimized in the circuitry associated
with the unselected port. In the standby mode, this pin is driven to the high impedance state.

MOTOROLA ANALOG IC DEVICE DATA

5

MC68160A

T able 1. Pin Function Description (continued)

Pin(s) Symbol Type Name/Function

STATUS INDICATOR

40 TXLED O

TTL/CMOS

41 RXLED O

TTL/CMOS

42 CLLED O

TTL/CMOS

43 TPLIL O

TTL/CMOS

44 TPPLR O

TTL/CMOS

45 TPJABB O

TTL/CMOS

Transmit Status LED Driver Output: This pin indicates the transmit status of the currently
selected TP or AUI port. When there is no transmit activity detected, an internal pull–up takes
this pin to its normal off (high) state. When transmit activity is detected, the LED driver turns
on. In its on state, TXLED flashes the LED by driving low at approximately 10 Hz at a 50%
duty cycle. In the standby mode, this output is driven to the high impedance state.

Receive Status LED Driver Output: This pin indicates the receive status of the currently
selected TP or AUI port. When there is no receive activity detected, an internal pull–up takes
this pin to its normal off (high) state. When receive activity is detected, the LED driver turns
on. In its on state, RXLED flashes the LED by driving low at approximately 10 Hz at a 50%
duty cycle. In the standby mode, this output is driven to the high impedance state.

Collision Status LED Driver Output: This pin indicates the collision status of the currently
selected TP or AUI port. When there is no collision activity detected, an internal pull–up takes
this pin to its normal off (high) state. When collision activity is detected, the LED driver turns
on. In its on state, CLLED flashes the LED by driving low at approximately 10 Hz at a 50%
duty cycle. In the standby mode, this output is driven to the high impedance state.

Twisted Pair Link Integrity Output: This output is driven to the low output state to indicate
good link integrity on the TP port during TP mode. It is deasserted (high) when link integrity
fails in TP mode. The TPLIL output is driven to the high impedance state when the AUI port
is selected. In the standby mode, this output is also driven to the high impedance state.

Twisted Pair Polarity Error Output: If TPAPCE is high and the wires connected to the
Twisted Pair Receiver Inputs (TPRX+, TPRX–) are reversed, TPPLR will be driven to the low
logic state to indicate the fault. TPPLR remains low when the MC68160A, AB and AC has
automatically corrected for the reversed wires. If the twisted pair link integrity tests fail, this
output will be driven to the high logic state. When the AUI mode is selected this output is
driven to the high impedance state. In the standby mode, this output is also driven to the high
impedance state.

Twisted Pair Jabber Output: This pin is driven high to indicate a jabber condition at the
TPTX+/– outputs. (Jabber condition also causes CLLED to be driven alternately to the high
and low output levels). TPJABB is driven to the low output state when no jabber condition is
present. When the AUI mode is selected this output is driven to the high impedance state. In
the standby mode, this output is also driven to the high impedance state.

POWER SUPPLY AND GROUND

10 VDDDIV Frequency Divider Supply Pin
11

13
14

15
20 GNDSUB Substrate Ground Pin

7

8
18
19

30
33

34
35
38
39

47 GNDCTL Controller Interface Ground Pin

NOTE: Power and ground pins are not connected internally. Failure to connect externally may cause malfunction or damage to the IC.

VDDFM
GNDFM

GNDVCO
VDDVCO

VDDDIG
GNDDIG
VDDDIG
GNDDIG

VDDANA
GNDANA

GNDPWR
VDDPWR
VDDPWR
GNDPWR

Frequency Multiplier Supply and Ground Pins

Voltage Controlled Oscillator Ground and Supply Pins

Digital Supply and Ground Pins

Analog Supply and Ground Pins

Power Supply and Ground Pins

6

MOTOROLA ANALOG IC DEVICE DATA

MC68160A

T able 2. Controller Interface Selection

Motorola

Transceiver

MC68160A

(EEST)

CS0
CS1
CS2

Pin Pin Sense Pin Sense Pin Sense Pin Sense

TCLK TCLK High TXC Low TCKN Low TXC High

TX TX High TXD High TXD High TXD High

TENA TENA High RTS Low TEN High TXE High
RCLK RCLK High RXC Low RCN Low RXC High

RX RX High RXD High RXD High RXD High

RENA RENA High CRS Low XCD High CRS High
CLSN CLSN High CDT Low XCOL Low COL High

1

LOOP

NOTES: 1. Although LOOP input is not ordinarily classifed as a controller pin, it is included in this table because its sense varies according to the controller used.

2. The Motorola controller interface contained in the MC68360 (QUICC

3. The pin sense is shown from the perspective of the identified controller pin.

4. Supported only by MC68160A.

Motorola

Controller

MC68360

(QUICC)

N.A. High LPBK Low LBC High LPBK High

2

82586, 82590,

82593, 82596

1
1
0

4

Intel

Controllers

0
1
0

Controllers

86950 (Etherstar)

86960 (NICE)

) is compatible with the AMD 7990 (LANCE) and 79C900 (ILACC) controllers.

Fujitsu

1
0
0

4

National

Controllers

8390, 83C690,

83932B (SONIC)

4

0
0
0

LAN

Controller

T able 3. Controller Independent Mode Selection

Pin Standby Mode Reserved Reserved Reserved

CS0
CS1
CS2

NOTE: In standby mode, the MC68160A consumes less power supply current than in any other

mode. Additionally, in the standby mode, all of the controller inputs and outputs are
driven to the high impedance state. When the standby mode is deasserted, an internal
reset pulse of approximately 6.0 µs duration is generated.

Following a period of operation in the standby mode, the time required to insure stable
data reception is approximately 100 ms.

1
1
1

0
1
1

1
0
1

0
0
1

Figure 2. Applications Block Diagram

TCLK
TX
TENA
RCLK
RX

MC68160A

ATX+
ATX–
ARX+
ARX–
ACX+
ACX–

Pulse

Transformers

ATX+
ATX–
ARX+
ARX–
ACX+
ACX–

DB–15

Connector

RENA
CLSN

MOTOROLA ANALOG IC DEVICE DATA

TPTX+
TPTX–
TPRX+
TPRX–

Filters

and

Pulse

Transformers

TPTX+
TPTX–
TPRX+
TPRX–

RJ–45

Connector

7

MC68160A

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Characteristic Symbol Min Max Unit

Storage Temperature Range T
Power Supply Voltage Range

Analog
Digital

Voltage on any TTL compatible input pin with

respect to Ground

Voltage on TPRX, ARX, or ACX input pins with

respect to Ground

Differential Voltage on TPRX, ARX, or ACX Input

Pins

NOTE: Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the

device. Functional operation of the device is not implied at these or any other conditions in
excess of those indicated in the operation sections of this data sheet. Exposure to Absolute
Maximum Ratings conditions for extended periods can adversely affect device reliability.

V
V

V

stg

DDA
DDD

DIFF

RECOMMENDED OPERATING CONDITIONS

Characteristic Symbol Min Max Unit

Power Supply Voltage Range V
Power Supply Ripple (20 kHz to 100 kHz) – – 50 mV
Power Supply Impulse Noise (Either Polarity) – – 100 mV
Ambient Operating Temperature Range T
ARX/ACX Input Differential Rise and Fall Time (see Figure 39) t
ARX Pair Idle Time after Transmission (see Figure 39) t

ESD

Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge
(ESD) during handling and mounting. Motorola employs a Human Body Model (HBM) and a Charged Device Model (CDM) for ESD–susceptibility
testing and protection design evaluation. ESD has been adopted for the CDM, however, a standard HBM (resistance = 1500 Ω capacitance –
100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using
the circuit parameters contained in this specification. ESD threshold voltage is designed to 700 V Human Body Model.

–65 150 °C

–
–

V –0.5

–0.5

–6.0 6.0 V

7.0

7.0

VDD + 0.5

6.0

V

V

DD

A
260
265

4.75 5.25 V

0 70 °C

2.0 10 ns

8.0 – µs

DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended

ambient operating temperature and power supply voltage ranges.)

Characteristic

POWER SUPPLY

Undervoltage Shutdown Threshold – – – – 4.4 V
Power Supply Current I

8

Symbol Test Conditions Min Typ Max Unit

DD

–

Standby Mode

–
–

145

–

200

5.0

MOTOROLA ANALOG IC DEVICE DATA

mA

MC68160A

DC ELECTRICAL CHARACTERISTICS (T

= 25°C, VCC = 5.0 V ± 5%. Unless otherwise noted, minimum and maximum

A

limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160A except where noted.)

Characteristic

Symbol Test Conditions Min Max Unit

TTL COMPATIBLE INPUTS

TTL Compatible Input Voltage

Low State
High State

Input Current TTL Compatible Input Pins (Note 1)
Input Current TENA TTL Compatible Input Pin:

VIL(TTL)

VIH(TTL)

–

0 V < VI < V

DD

2.0

–

0.8
–

V

–

±10

µA

with Pull–Down Resistor

I

IH

I

IL

with Pull–Down Resistor removed in Standby Mode

I

IH

I

IL

IIH & I

–
–

IL

–

+200

–20
±10

CMOS COMPATIBLE INPUTS

CMOS Compatible Input Voltage

Low State
High State

VIL(CMOS)
VIH(CMOS)

Input Current (Pin X1) IIH & I

IL

–

0 V < VI < V

DD

–

3.0

1.0
–

– ±100 µA

V

TTL/CMOS COMPATIBLE OUTPUTS

TTL/CMOS Compatible Output Voltage

Low State (Note 2)
Low State (Note 3)

TTL/CMOS Compatible Output Voltage

High State (Note 4)
High State (Note 5)
High State (Note 2)

Three State Output Leakage Current I

V

OL

V

OH

OZ

IOL = 4.0 mA
IOL = 10 mA

IOH = –500 µA

IOH = –10 mA

IOH = –4.0 mA

0 V ≤ VOZ ≤ V

DD

–
–

3.9

3.9

2.4

0.45

0.45

–
–
–

– ±10 µA

V

V

Characteristic Symbol Test Conditions Min Max Unit

TWISTED PAIR RECEIVER INPUTS

Input Voltage Range (DC + AC) V
Differential Input Squelch Threshold Voltage V
Common Mode Bias Generator Voltage V
Common Mode Input Resistance R
Differential Input Resistance R

ITP

ITPSQ

BCMTP

CMTP

DIFFTP

– 1.5 4.3 V

Note 10 270 390 mV

Note 9 1.8 3.2 V

– 1000 – Ω
– 2.5 – kΩ

TWISTED PAIR TRANSMITTER OUTPUTS

Differential Output Voltage

Pre–Emphasis Level
Signal Level

Common Mode Output Voltage Range V
Common Mode Output Voltage in Standby Mode V

NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode).

2. TCLK, RX, RCLK, RENA and CLSN.

3. TPPLR, TPLIL, TPJABB, TXLED, RXLED, CLLED and TPEN (In Output Mode).

4. TPPLR, TPLIL, CLLED, TXLED and RXLED.

5. TPJABB and TPEN (In Output Mode).

6. Measured with T est Load B1 (shown in Figure 3), applied directly to the TPTX+/– pins of the device.

7. Measured differentially with Test Load B2 (shown in Figure 4), applied directly to the TPTX+/– pins of the device.

8. Measured directly on the TPTX+/– pins of the device.

9. Measured with T est Load B3 (shown in Figure 5), applied directly to the TPRX+/– pins of the device.

10. The Common Mode Input Voltage is between 1.8 V and 3.2 V.

V

ODFTPP

V

ODFTPS

OCMTP

OCMTPSB

Note 7

Note 6 0 4.0 V

IOH = –100 µA VDD – 1.0 V

±2.2

±1.56

±2.8

±1.98

DD

V

V

MOTOROLA ANALOG IC DEVICE DATA

9

MC68160A

DC ELECTRICAL CHARACTERISTICS

(continued) (TA = 25°C, VCC = 5.0 V ± 5%. Unless otherwise noted, minimum and maximum

limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160A except where noted.)

Characteristic

Symbol Test Conditions Min Max Unit

TWISTED PAIR TRANSMITTER OUTPUTS

Differential Output Voltage

IDLE Mode
Open Circuit

Differential Output Impedance

TRANSMISSION Mode
IDLE Mode

Common Mode Output Impedance

TRANSMISSION Mode
IDLE Mode

NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode).

2. TCLK, RX, RCLK, RENA and CLSN.

3. TPPLR, TPLIL, TPJABB, TXLED, RXLED, CLLED and TPEN (In Output Mode).

4. TPPLR, TPLIL, CLLED, TXLED and RXLED.

5. TPJABB and TPEN (In Output Mode).

6. Measured with T est Load B1 (shown in Figure 3), applied directly to the TPTX+/– pins of the device.

7. Measured differentially with Test Load B2 (shown in Figure 4), applied directly to the TPTX+/– pins of the device.

8. Measured directly on the TPTX+/– pins of the device.

9. Measured with T est Load B3 (shown in Figure 5), applied directly to the TPRX+/– pins of the device.

10. The Common Mode Input Voltage is between 1.8 V and 3.2 V.

V

ODFTPI

V

ODFTPO

R

ODFTPT

R

ODFTPI

R

OCMTPT

R

OCMTPI

Note 6
Note 8

Note 8

Note 8

12

8.0

3.0

1.0

–
–

±50

5.25

mV

V

Ω

28
29

7.0

Ω

10

DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended

ambient operating temperature and power supply voltage ranges.)

Characteristic

AUI RECEIVER INPUTS

Input Voltage Range (DC + AC) V
Differential Mode Input Voltage Range V
Differential Input Squelch Threshold Voltage V
Common Mode Input Resistance R
Differential Input Resistance (ARX, ACX Inputs) R

AUI TRANSMITTER OUTPUTS

Common Mode Output Voltage

IDLE Mode
ACTIVE Mode
STANDBY Mode

Differential Output Voltage

IDLE Mode
ACTIVE Mode

Differential Output Load Current

IDLE Mode

Output Short Circuit Current I

Symbol Test Conditions Min Max Unit

IA

IDFA
IASQ
ICMA

IDFA

1.0 V < V

1.0 V < V

318 mV < V

– 1.0 4.2 V
– ±318 ±1315 mV
– –275 –175 mV

< 4.2 V 1.5 – kΩ

ICMA
ICMA

IDMA

< 4.2 V

< 1315 mV

5.0 – kΩ

Figure 6

V

OCMIA

V

OCMAA

V

OCMSA

V

ODFIA

V

ODFAA

I

ODFIA

ODSA

IO = –100 µA

Figure 6

Figure 7

Output Short Circuited to

VDD or GND

1.0

1.0

VDD – 2.0

–

±600

4.2

4.2

VDD – 1.2

±40

±1315

– ±4.0
– ±150 mA

mV

mA

V

10

MOTOROLA ANALOG IC DEVICE DATA

MC68160A

Figure 3. T est Load B1 Figure 4. T est Load B2

Device

39 Ω

V1

1.0 k Ω

39 Ω

NOTE: A total of 50 Ω per driver output is required for proper series line termination. This is realized with the

39 Ω external resistors shown in Figures 3, 4 and 5, together with the internal driver output resistance.

RCM

+
VCMD

–

Device

Figure 6. AUI Common Mode Termination

39 Ω

39 Ω

I

O

V

CM

Figure 5. T est Load B3

V

DIFF

39 Ω

39 Ω

–

+

RCM

10 kΩ

Device

+
VCMD

–

39 Ω

39 Ω

Figure 7. AUI Differential Output

Short Circuit Current

100 Ω

I

OD

MOTOROLA ANALOG IC DEVICE DATA

11

MC68160A

AC ELECTRICAL CHARACTERISTICS

temperature and power supply voltage ranges.)

Characteristic

EXTERNAL CLOCK INPUT (X1)

Cycle Time (Note 1) (See Figure 8)
Fall Time
Rise Time
Low Time
High Time

RECEIVE PHASE–LOCKED–LOOP SWITCHING

Stabilization Time t

CONTROLLER TRANSMIT SWITCHING (MOTOROLA MODE)

TCLK Cycle Time
TCLK High Time
TCLK Low Time
TCLK Rise and Fall Time

TX Setup Time to TCLK ↑
TX Hold Time to TCLK ↑

TENA Setup Time to TCLK ↑
TENA Hold Time to TCLK ↑

CONTROLLER RECEIVE SWITCHING

RCLK Cycle Time
RCLK High Time
RCLK Low Time
RCLK Rise and Fall Time

RX Hold Time from RCLK ↑
RX Set–Up Time to RCLK ↑

RCLK Delay from RENA ↑
RX Delay from RENA ↑

RENA Deassertion Delay from RCLK ↑ (See Figure 12) t

NOTES: 1. To meet IEEE–802.3 specifications.

2. Load on specified output is 20 pF to ground, unless otherwise noted.

3. ↑ = Rising Edge

(Unless otherwise noted, minimum and maximum limits apply over the recommended

Symbol Min Max Unit

t
t
t
t
t

t

10

t

11

t

12

t

13

t

14

t

15

t

16

t

17

t

20

t

21

t

22

t

23

t

24

t

24.1
t

25

t

26
27

1
2
3
4
5

7

49.995
–
–

20
20

– 100 ms

99
45
45

–

20

0

20

0

90
42
47

–

10
70

–
–

10 30 ns

50.005

5.0

5.0
30
30

101

55
55

8.0

–
–

–
–

–
–

55

8.0

–
–

650
600

ns

ns

ns

ns

ns

ns

ns

12

Figure 8. X1 Input Voltage Levels for Timing Measurements

t

1

t

4.0V

0V

2

3.6V

1.5V

t

5

0.4V

1.5V1.5V

0.4V

t

4

3.6V

t

3

MOTOROLA ANALOG IC DEVICE DATA

MC68160A

Figure 9. Receive Phase–Locked–Loop Switching

CS0 D CS1 D CS2

TCLK

1.5V

TPRX

t

7

RENA

NOTE: CS0 • CS1 • CS2 is the logical AND operation and refers to the pins not at Logic 1.

Figure 10. Transmit T iming (Motorola Mode)

t

3V

13t13

0.8V

3V

1.5V 1.5V

1.5V1.5V

t

10

t

11

1.5V1.5V

t

16

t

12

1.5V

t

17

TENA

TX

RENA

RCLK

RX

1.5V
t

14t15

1.5V

1.5V

Figure 11. Receive T iming (Motorola Start of Frame)

1.5V
t

25

1.5V

t

26

t

23

3V

0.8V

t

24.1

t

23

3V

0.8V

t

24

1.5V1.5V

1.5V 1.5V 1.5V

1.5V

t

20

1.5V

t

22

t

21

MOTOROLA ANALOG IC DEVICE DATA

13

MC68160A

Figure 12. Receive Timing (Motorola End of Frame)

RENA

RCLK

RX

CONTROLLER TRANSMIT SWITCHING (Intel Mode – Support by MC68160A Only)

Characteristic

TXC Cycle Time

High and Low Time

TXC
TXC

Rise and Fall Time

TXD Setup Time to TXC ↓
TXD Hold Time to TXC

RTS Setup Time to TXC ↓
RTS

Hold Time to TXC ↓

CONTROLLER RECEIVE SWITCHING

RXC Cycle Time

High Time

RXC
RXC

Low Time
Rise and Fall Time

RXC
RXD Hold Time from RXC ↓

RXD Set–Up Time to RXC

Delay from RXC ↑

CRS

NOTE: Load on specified output is 20 pF to ground, unless otherwise noted.

↑ = Rising Edge
↓ = Falling Edge

↓

↓

Symbol Min Max Unit

t

40

t

41

t

42

t

43

t

44

t

45

t

46

t

80

t

81

t

82

t

83

t

85

t

85.1
t

86

Last Bit

t

27

1.5V

1.5V

99
40

20

20

90
45
40

50
35
12

101

–

0

0

–

–

5.0
–

–
–

–

–

55

–

5.0
–

–

30

ns

ns

ns

ns

ns

14

TXC

RTS

TXD

3V

t42t

0.8V

1.5V

Figure 13. Transmit T iming (Intel)

42

3V

t

45

t

43

1.5V

t

41

1.5V1.5V 1.5V

1.5V

t

t

41

40

1.5V

t

t

44

43

1.5V 1.5V
11000 1 / 0

Last Bit

1.5V

t

46

1.5V

MOTOROLA ANALOG IC DEVICE DATA

MC68160A

Figure 14. Receive Timing (Intel)

CRS

t

t

80

1.5V

RXC

RXD

CONTROLLER TRANSMIT SWITCHING (Fujitsu Mode – Supported by MC68160A Only)

Characteristic

TCKN Cycle Time
TCKN High and Low Time
TCKN Rise and Fall Time

TXD Setup Time to TCKN ↓
TXD Hold Time to TCKN ↓

TEN Setup Time to TCKN ↓
TEN Hold Time to TCKN ↓

CONTROLLER RECEIVE SWITCHING

RCKN Cycle Time
RCKN High Time
RCKN Low Time
RCKN Rise and Fall Time

RXD Hold Time from RCKN ↓
RXD Set–Up Time RCLK ↓
RCKN Delay from XCD ↑

XCD Deassertion Delay from RCKN ↑ (See Figure 17) t

NOTE: Load on specified output is 20 pF to ground, unless otherwise noted.

↑ = Rising Edge
↓ = Falling Edge

1.5V 1.5V

81t82

1.5V

1.5V

t

t

85

85.1

Symbol Min Max Unit

t

90

t

91

t

92

t

93

t

94

t

95

t

96

t

100

t

101

t

102

t

103

t

104

t

104.1
t

105
106

1.5V

t

86

1.5V

3V

t

83

3V

.8V

t

83

99
45

–

20

0

20

0

90
40
45

–

50
35

–
0 – ns

101

55

8.0
–

–
–

–

–
–

55

8.0
–

–

600

ns

ns

ns

ns

ns

t

90

TCKN

TEN

TXD

1.5V

1.5V

t

95

1.5V

t

93

t

94

MOTOROLA ANALOG IC DEVICE DATA

Figure 15. Transmit T iming (Fujitsu)

t

91

1.5V 1.5V

t

91

1.5V

0.8V

3V

0.8V

t

t

92

92

1.5V1.5V

t

96

1.5V

15

XCD

RCKN

RXD

1.5V

MC68160A

Figure 16. Receive Timing (Fujitsu Start of Frame)

t

105

1.5V

Figure 17. Receive Timing (Fujitsu End of Frame)

t

101

3V

1.5V 1.5V 1.5V 1.5V
t

104.1

t

102

1.5V 1.5V

t

104

t

0.8V

103

t

103

t

100

XCD

RCKN

RXD

CONTROLLER TRANSMIT SWITCHING (National Mode – Supported by MC68160A Only)

Characteristic

TXC Cycle Time
TXC High and Low Time
TXC Rise and Fall Time

TXD Setup Time to TXC ↑
TXD Hold Time to TXC ↑

TXE Setup Time to TXC ↑
TXE Hold Time to TXC ↑

CONTROLLER RECEIVE SWITCHING

RXC Cycle Time
RXC Low Time
RXC High Time
RXC Rise and Fall Time

RXD Hold Time from RXC ↑
RXD Set–Up Time from RXC ↑
RXC Delay from CRS ↑

CRS Deassertion Delay from RXC ↓ t
RXC continuing beyond CRS ↓ t

NOTE: Load on specified output is 20 pF to ground, unless otherwise noted.

↑ = Rising Edge
↓ = Falling Edge

1.5V

t

106

1.5V

Symbol Min Max Unit

t

110

t

111

t

112

t

113

t

114

t

115

t

116

t

120

t

121

t

122

t

123

t

124

t

124.1
t

125
126
127

99
45

–

20

0

20

0

90
40
40

–

50
35

–
0 15 ns

5.0 – cycles

101

55

8.0
–

–
–

–

–
–

60

8.0
–

–

600

ns

ns

ns

ns

ns

16

MOTOROLA ANALOG IC DEVICE DATA

MC68160A

Figure 18. Transmit T iming (National)

t

111

t

110

TXC

TXE

TXD

CRS

RXC

1.5V 1.5V

t

115

1.5V

1.5V

t

125

3V

t

0.8V1.5V

112

0.8V

t

111

1.5V

t

113t114

1.5V

t

112

Figure 19. Receive Timing (National)

t

122

t

120

1.5V1.5V 1.5V 1.5V

3V

0.8V

t

126

1.5V
t

116

1.5V

t

1.5V

127

1.5V

RXD

t

121

t

123t123

t

124.1t124

1.5V

MOTOROLA ANALOG IC DEVICE DATA

17

MC68160A

TP TRANSMIT SWITCHING

Characteristic

TPTX Common Mode AC Output Voltage (Note 3) V
TX to TPTX Steady State Propagation Delay (Note 2) (See Figure 24)

Bit Duration Center–to–Center

Half–Bit Cell Duration Center–to–Boundary
TENA Assert to RENA Assert Delay (Note 7) (See Figure 24) t
Internal Loopback Delay from TX to RX (Note 7) (See Figure 24) t
TPTX End of Packet Hold Time from last positive TPTX Signal Edge to

+585 mV Differential Output Level (Note 5) (See Figure 25)
TPTX Precompensation Pulse Width (Notes 2 and 6) (See Figure 25) t
RENA Deassert Delay from TENA Deassert when Receiver is inactive

Motorola Mode
Fujitsu Mode
National Mode
Intel Mode (Note 4) (See Figure 26)

TPTX Data–to–Link Test Pulse (Note 2) (See Figure 27)
TPTX Link Test Pulse Width (Note 2)
TPTX Link Test Pulse Decay–to–Idle Condition (Note 1)
TPTX Link Test Pulse to next Link Test Pulse (Note 2)

NOTES: 1. Measured differentially across the output of Test Load A which is connected directly to the TPTX+/– pins of the device.

2. Measured differentially across the output of Test Load D shown in Figure 23 which is connected directly to the TPTX+/– pins of the device.

3. Measured across the output of Test Load C which is connected directly to the TPTX+/– pins of the device.

4. Same as t

5. Measured across the output of T est Load B shown in Figure 21.

6. Measured at the +/–90% points of the precompensation voltage feature of the waveform. (The 0% reference is 0 V differential.)

7. Load on specified output is 20 pF to ground.

except the logic states for TENA and RENA are inverted.

137

Symbol Min Typ Max Unit

OCMTP

t

130

t

131

t

132
133
134

t

135

136

t

137

t

137

t

137

t

138

t

139

t

140

t

141

t

142

– – 50 mVrms

–
98
48

–
–

–
– – 400 ns
– – 650 ns

250 – 400 ns

– 45–58 – ns

250
250
250
250

8.0
80
80

8.0

–
–
–
–

–
–
–
–

200
102

52

450
450
450
450

24
240
240

24

ns

ns

ms

ns
ns

ms

Figure 20. T est Load A Figure 21. T est Load B

39Ω

100pF 100pF V

39Ω

1.0µH

1.0µH

100µH

Figure 22. T est Load C Figure 23. T est Load D

200µH
39Ω
39Ω

NOTE: A total of 50 Ω per driver output is required for proper series line termination.

47.5Ω

V

out

47.5Ω

This is realized with the 39 Ω external resistors shown in Figures 20 to 23,
together with the internal driver output resistance.

100Ω

49.9Ω V

OUT

CM

Device

39Ω
39Ω

39Ω
39Ω

200µH

100Ω

100Ω

V

OUT

18

MOTOROLA ANALOG IC DEVICE DATA

X1

MC68160A

Figure 24. TPTX Transmit Timing (Start of Frame) Switching

TCLK

TENA

RENA

TPTX +/– Differential

(Logic Levels)

TPTX +/– Differential

(Pre–Emphasis)

TX

RX

1.5V

1.5V

1 1 1 1000

1.5V

t

134

t

133

1.5V

1.5V

1 1 1 1000

101

t

130

1010011

0V

0

0

t

131t132

Figure 25. TPTX Transmit Timing (End of Frame) Switching

t

136

t

135

11

TPTX +/–

Differential

TENA

RENA

90% 90%

+585mV

Figure 26. RENA Deassert Delay from TENA

t

137

1.5V

+585mV

1.5V

MOTOROLA ANALOG IC DEVICE DATA

19

MC68160A

g

Deassertion from last ositive TPTX edge

t

171

3.1

Figure 27. TPTX+/– Link Pulse Timing

t

142

t

t

140

t

139

TP TRANSMIT JABBER SWITCHING

Characteristic

Max Length of Transmission before Assertion

of TPJABB to indicate Jabber Condition
CLSN to indicate Jabber Condition

Time from End of Jabber Condition to Deassertion:

of TPJABB
of CLSN

TP TRANSMIT SIGNAL QUALITY ERROR TEST SWITCHING

CLSN (Signal Quality Error Test) (See Figure 29)

Assertion from last positive TPTX edge
Deassertion from last positive TPTX ed
Pulse Width

TPSQEL Disable Delay Time (See Figure 29) t

NOTE: The load attached to the specified output is a 20 pF capacitor connected to ground, unless otherwise noted.

e

141

585mV585mV 585mV

±50mV

Symbol Min Max Unit

t

160

t

161

t

162

t

163

t

170

t
t

172
173

20
20

500
500

0.6
–

0.5
– 40 ns

60
60

750
750

1.6

3.1

1.5

ms

ms

µs

TPTX

(Differential)

TPJABB

CLSN

20

–585mV

Figure 28. TPJABB Switching

585mV

t

160

1.5V

t

161

t

162

t

163

1.5V

MOTOROLA ANALOG IC DEVICE DATA

1.5V

1.5V

TPTX+/–

TPSQEL

MC68160A

Figure 29. TPTX SQE (CLSN) Timing (End of Frame)

2V

t

171

1.5V
t

173

t

170

CLSN

TP RECEIVE SWITCHING

Characteristic

Differential Input Voltage Range Unconditional Squelch (Note 1)

(1.8 V < Input Common Mode Voltage < 3.2 V)

Positive or Negative Differential Input Pulse Width for Conditional Receive Unsquelch

(See Figure 31)
TPRX to RCLK Bit Loss at start of packet (See Figure 32) t
TPRX to RCLK Steady State Propagation Delay (See Figure 32) t
TPRX to RX Start Up Delay (See Figure 32) t
TPRX held high from last valid positive transition (See Figure 33) t
RENA Deassertion Delay from last valid positive transition of TPRX Pair

(See Figure 33)

TP RECEIVE LINK INTEGRITY SWITCHING

Required Pulse Width Range to be recognized as a Link Pulse (Note 2) t
Last TPRX activity to high state TPLIL Output

(Receive Link Loss Timeout Interval)
Receive Link Beat Separation

Minimum Range (Note 3)

Maximum Range (Note 4)

NOTES: 1. Measured with T est Load H attached to the receive pins.

2. Measured at the receive pins.

3. Link beats closer in time to this range of values are considered noise, and are rejected.

4. Link beats further apart in time than this range of values are not considered consecutive, and are rejected.

t

172

1.5V

Symbol Min Max Unit

V

IDFSTP

t

180

181
182
183
186

t

187

200

t

201

t

202

t

203

0 |264| mV

20 30 ns

– 10 Bits
– 400 ns
– 1.5 µs

230 – ns

– 350 ns

50 200 ns

100 150 ms

3.0

100

1.5V

7.0

150

ms

Figure 30. T est Load H Figure 31. TPRX Input Switching

100Ω

1.0µH

100pF 100pF Line

1.0µH

200µH

MOTOROLA ANALOG IC DEVICE DATA

TPRX

0mV

–330mV

t

180

t

+330mV

180

21

TPRX+/–

RENA

RCLK

RX

0V

MC68160A

Figure 32. TPRX Receive Timing (Start of Frame)

Bit n Bit n+1 Bit n+2 Bit n+3 Bit n+4

1 01011

–300mV

t

181

0V

t

1.5V

183

t

182

1.5V

TPRX+/–

RENA

Bit n Bit n+1

Bit n+2

Figure 33. RENA Deassertion Delay from Last Valid Positive Transition of TPRX Pair

t

186

t

+300mV

187

+300mV

Figure 34. TP Receive Link Integrity Switching

t

202/t203

t

200

0V

1.5V

22

TPRX

TPLIL

t

300mV300mV

201

50%

MOTOROLA ANALOG IC DEVICE DATA

MC68160A

TP COLLISION SWITCHING

Characteristic

Time from collision (TPRX activity caused assertion of RENA followed by assertion of

TENA) to assertion of CLSN
Time from end of collision (Deassertion of TENA with uninterrupted TPRX pair

activity) to deassertion of CLSN

TP FULL DUPLEX SWITCHING

TPFULDL assert to collision detect disable (See Figure 36)
TPFULDL deassert to collision detect enable

TPFULDL assert to data loop back disable (See Figure 37)
TPFULDL deassert to data loop back enable

NOTE: Load on specified output is 20 pF to ground, unless otherwise noted.

Figure 35. TPTX Collision Timing

RENA

Symbol Min Max Unit

t

210

t

211

t

220

t

221

t

222

t

223

–

350

–
–

–
–

300

900

50
50

350
150

ns

ns

ns

TENA

CLSN

TPFULDL

CLSN

1.5V

t

210

1.5V

Figure 36. TPTX Full Duplex Timing

1.5V 1.5V

t

220

1.5V

t

221

Figure 37. TPTX Full Duplex Timing

1.5V

1.5V

t

211

1.5V

TPFULDL

RENA

1.5V 1.5V

t

MOTOROLA ANALOG IC DEVICE DATA

223

1.5V

t

222

1.5V

23

MC68160A

AUI TRANSMIT SWITCHING

Characteristic

TCLK to ATX Pair Steady State Propagation Delay t
Output Differential Rise and Fall Times (Measured directly at device pins) t
ATX Bit Cell Duration center–to–center (Measured directly at device pins) t
ATX Half–Bit Cell Duration center–to–boundary (Measured directly at device pins) t
ATX Pair Held at Positive Differential at start of Idle (Measured through

transformer)

NOTE: Load on specified output is a shunt 27 µH inductor and 83 Ω resistor.

Figure 38. ATX Transmit Timings

Symbol Min Typ Max Unit

– – 100 ns

1.0 – 5.0 ns
– 99.5–100.5 – ns
– 49.5–50.5 – ns

200 – – ns

t

240
241
242
243
244

TCLK

TENA

TX

ATX+/–

Differential

(Logic Levels)

AUI RECEIVE SWITCHING

ARX/ACX Differential Input Voltage Range – ±318 ±1315 mV
ARX/ACX Differential Input Pulse Width to:

Initiate Data Reception
Inhibit Data Reception

RENA Assertion Delay
RENA Deassertion Delay

Squelching Characteristics

The receive data pairs and the collision pairs should have the following squelch characteristics:

1. The squelch circuits are on at idle (with input voltage at approximately 0 V differential).

2. If an input is in squelch, pulse is rejected if the peak differential voltage is more positive than –175 mV, regardless of pulse width.

3. A pulse is considered valid if its peak differential voltage is more negative than –300 mV and its width, measured at –285 mV, is > 25 ns.

4. The squelch circuits are disabled by the first valid negative differential pulse on either the AUI receive data or collision pair .

5. If a positive differential pulse occurs on either the AUI receive data or collision pair > 175 ns, end of frame is assumed and squelch circuitry is turned on.

1.5V

11 11000

t

240

0V

10 1

t

242

Characteristic Symbol Min Max Unit

t

241

90%

0011

10%

t

243

t

261

t

262

t

266

t

267

90%

10%

t

241

0V

30

t

244

70%

–
–

–

–

18

100
450

ns

ns

24

Figure 39. ARX/ACX Timing

ARX+/–
ACX+/–

Differential

Input Voltage

+175mV

–175mV

t

261/ t262

MOTOROLA ANALOG IC DEVICE DATA

MC68160A

Figure 40. ARX/ACX Timing

ARX+/–/

ACX+/–

Differential

Input Voltage

–300mV

RENA/CLSN

RCLK

RX

t

261

Bit U Bit V Bit W Bit X Bit Z

t

260

–40mV

10 1 0 0 1 1
–275mV

t

266

1.5V 1.5V

90%

10%

Bit VBit UBit Q

Bit YBit Q

90%

10%

t

260

Bit X Bit Y Bit ZBit U

0V

t

267

+300mV

FUNCTIONAL DESCRIPTION

Introduction

The MC68160A was designed to perform the physical
connection to the Ethernet media. This is done through two
separate media dependent interfaces and a SIA interface.
The media dependent interfaces are the Attachment Unit
Interface(AUI) and the 10BASE–T Twisted Pair(TP) port. The
MC68160A’s SIA interface is compatible with most industry
controllers and selected by three mode control pins. Chip
status is supported indicated by the condition of 6 status
indicator pins. All but one are open collector outputs.

If the EEST isn’t receiving data, the controller may initiate
transmission. NRZ data from the communications controller
SIA interface is encoded by the MC68160A into Manchester
Code in preparation for transmission on the media. The data
is then applied to either the AUI or TP port. If the data was
transmitted using the 10BASE–T port, this data is also
looped back to the receive data interface SIA pins
connected to the controller. This allows detection of a
collision condition in the event that another station on the
media attempted transmission at the same time. After the
entire data frame has been transmitted, the EEST must
force the media idle signal. The idle signal frees the media
for other stations that have deferred transmission. If no
other transmissions are required the link enters an idle
state. During this idle state the 10BASE–T transmitter
issues idle pulses which communicates to the receiver
connected to the other side that the link is valid. If the

transmitter connected at the other end begins transmission,
the EEST will assert a receive enable signal, and forward
the received data to the controller.

Upon reception of data at the 10BASE–T port, the data is
screened for proper sequence and pulse width requirements.
If the preamble of the received frame meets the
requirements, the PLL locks onto the 64–bit preamble and
begins to decode the Manchester Code to NRZ code. This
code is then presented to the communications controller at
the receive data pins at the SIA interface. If data is received
at the AUI port, it is sent directly to the communications
controller via the SIA interface.

Data Transmission

To have properly encoded transmit data, the com–
munications controller must be synchronized to TCLK.
Transmission to the 10BASE–T or AUI media occurs when
TENA is asserted and data is applied to the TX pin. Finally , to
signify transmission, the TXLED in will cycle on and off at a
100 ms period. Data transmission for EEST is accomplished
either over the 10BASE–T port or the AUI port. Both
connections to the media are made with industry standard
media interface components. The 10BASE–T interface
requires a filter and transformer, the AUI interface requires
only a transformer. The filter for the 10BASE–T transmit
circuit will have to be chosen for each application.

MOTOROLA ANALOG IC DEVICE DATA

25

MC68160A

If after approximately 40 ms after a TP or AUI transmission
has begun, the EEST is still transmitting, the TPJABB pin will
assert to signify a jabber condition. Also, the CLLED pin will
transition high and low alternately with a 100 ms period. The
transmit circuitry is, however, unaffected by the jabber
condition, so the communications controller has the
responsibility of monitoring and stopping transmission.

When transmission is complete, the transmit circuitry will
begin the end of transmit and decay to idle responses
necessary to meet requirements of the 802.3 standard for the
TP and AUI port.

Data Reception

Other than the case of being in Loop Back mode, data
reception to the RX pin of the EEST is initiated by signaling at
the RX+/– or AUI ARX+/– pins. If at the TP port, the data is
screened for validity by checking for sequence and pulse
width requirements, then passed to the decode and receive
circuitry. The RENA pin asserts and the data and
corresponding clock is passed to the communications
controller. After the frame has been transmitted, the
MC68160A detects the ending transmission and negates
RENA. If at the AUI port, the data is checked for proper pulse
width requirements before being passed to the decode
circuitry. If the data pulses are longer than at least 20 ns,
RENA gets asserted and the frame is decoded to RX with
and accompanying RCLK output.

Collision

Collision is the occurrence of simultaneous transmit
activity by two or more stations on the network. In the event of
collision, the data transfer paths are unaffected. If the
MC68160A is in the twisted pair mode, collision is detect by
simultaneous receive and transmit activity. If in the AUI
mode, collision is detected by activity on the ACX+/– pins. In
either case, if collision is detected, the CLSN pin will assert to
notify the communications controller.

Jabber

The EEST has a jabber timer to detect the jabber condition.
In the event that the transmitting station continues to transmit
beyond the allowable transmit time, a jabber timer (40 ms) will

expire and assert the TPJABB pin to alert the communications
controller of the situation. The TPJABB pin can source or sink
up to 10 mA, and so, is capable of driving a status LED. In the
AUI mode, the pin is driven to high impedance since the
transceiver connected to the AUI port must alert the
communications controller of the jabber condition.

Full Duplex

A feature unique to the MC68160A is the Full Duplex
mode. In this mode the EEST is capable of transmitting and
receiving simultaneously. Collision conditions are not
announced and internal loop back is disabled. The remainder
of the EEST functionality remains unchanged from the
non–Full Duplex mode. Full Duplex mode is enabled by
asserting the TPFULDL pin.

Auto Port Selection

If the APORT pin is asserted, the MC68160A will
automatically select the TP or AUI port depending on the
presence of valid link beats or frames at the TP RX+/– pins. If
the AUI port is automatically selected by another transmitting
station or by setting TPEN low, the TP transmit port of the
EEST continues to transmit link beats to keep the link active.

Auto Polarity Selection

If the RX+ and the RX– wires happen to get reversed, the
MC68160A has the ability to automatically reverse the pins
internally so that the received data is valid. In addition, an open
collector status pin (TPPLR) is driven low to indicate the fault.
In the AUI or reset mode this pin presents a high impedance.

Loop Back Mode

To test the transmit and receive circuitry without disturbing
the connected network, the EEST has a Loop Back mode.
Loop Back mode routes transmit data and clock to the
receive data and clock pins using as much of the transmit and
receive circuitry as possible. This gives a test of the
MC68160A Manchester encode and decode function. LOOP
must not be asserted when TPFULDL pin is asserted. This
causes the MC68160A to enter a test mode. This test mode
is used during final test and is not intended to be entered
under normal operation (see Application Notes section).

26

MOTOROLA ANALOG IC DEVICE DATA

MC68160A

X1 X2

78Z1122 F–01

a o ec o cs

38 , 0 , 066

APPLICATIONS INFORMATION

Selection of Crystal and External Components

Accuracy of frequency and stability over temperature are
the main determinants of crystal choice. Specifications for a
suitable crystal are tabulated below.

Frequency
Mode
Tolerance
Stability
Aging
Shunt Capacitance
Load Capacitance
Series Fundamental Resistance (ESR)
Drive Level

A suitable crystal is the MTRON
HC49 MP–1, 20.000 MHz crystal.
20 pF for C4 and C5 have been
shown to work reliably.

PLL Filter Components

The filter components at Pin 12 were chosen to assure
adequate pull–range but with a emphasis on stability . It is not
foreseeable that a design would need to change the
components, but for the sake of completeness, relevant
values are provided here.

MHz

VCO Gain+24

Phase Detector Gain

filter impedance function is;

Z(jw)

[

jw• C5 • (jw)1ń

10BASE–T Filter and Transformer Choice

The MC68160A differential outputs are low impedance
voltage sources. Therefore, external series resistors must be
used in order to match the characteristic impedance of
twisted pair. Since the output resistance of each leg of the
transmitter is about 10 Ω, a 39 Ω resistor is used in series as
shown in the applications schematic. So the impedance
presented from the source to the isolation transformer is then
very nearly 100 Ω. The following is a list of some 10BASE–T
filter module vendors and their products.

ǒ

Volt • sec

(jw)1ń

+

100

pń2

C6)

C5)

Ǔ

ǒ

and,

m

A

rad

(for C6

C

5

Ǔ

and the

uu

20.000 MHz

Fundamental

± 100 ppm
± 100 ppm
± 5 ppm/yr

7.0 pF

18–20 pF

25 Ω

500 µW

12

C

C5)

Vendor Part #

FEE Fil–Mag 78Z1 120B–01, 78Z1122B/D–01,

Valor Electronics
Pulse Engineering
TOKO PM01–00, PM02–00, PM05–00

AUI Transformer Choice

Like the 10BASE–T outputs, the AUI differential outputs

are low impedance sources and capable of meeting the IEEE

802.3 waveform requirements when a coupling transformer
is used. Some AUI transformer vendors and their products
are provided below.

Vendor Part #

Coilcraft LAX–ET304
FEE Fil–Mag 23Z90, 23Z91/ 23Z92
Valor Electronics LT6032, LT6033

4

Pulse Engineering PE64502, PE6103
TOKO Q30ALQ8–1AA3, Q30ALQ9–1AA3

Application Notes:

Resetting the MC68160A after power up.

In some applications, after initial power up, the MC68160A
may not be able to transmit or receive data. This is usually
caused by the LOOP and TPFULDL control lines being active
at the same time. This is an illegal condition during normal
operation, it places the MC68160A into the production test
mode.

To exit the test mode and return to normal: Set LOOP low,
TPFULDL high and TPSQEL low. Then, while keeping
TPSQEL low, raise LOOP after 300 ms lower TPFULDL. This
will put the MC68160A into test mode but also resets the
MC68160A. After 500 ms lower LOOP to get out of the test
mode. TPFULDL may then be de–asserted if desired.

The MC68160A is now ready for operation.

A hardware implementation of this fix would be to place a
pull down resistor on the TPSQEL pin. Even if test mode is
entered by accident, this ensures that zero’s will be written to
the test register. The hardware implementation will solve the
problem if the test mode is entered because of noise on the
TPSQEL pin. If the controller is toggling the MC68160A lines
while it is booting up, the reset procedure must be followed.

PT3877, FL1012, FL1066
PE–65434, PE65424, PE65433

MOTOROLA ANALOG IC DEVICE DATA

27

MC68160A

Figure 41.

14

R

330Ω

13

R

330Ω

11

R

330Ω

LED5 LED4

LED3 LED2 LED1

LED6

9

R

330Ω

8

R

330Ω

33

R

330Ω

DD

V

Figure 41. T ypical Application Diagram

TD +

RJ45

TD –

RD +

RD –

1

263

16

15

Valor (PT3877, PT3882, FL1012, FL1066)

41 404252 51 50 49 48 47 46 45 44 43

123

TOKO (PM01, PM02, PM05)

Pulse Engineering (PE–65433, PE–65434, PE–65424)

CTP2

1

R

39Ω

DD

V

39383736353433323130292827

TPTX–

TPTX+

VDDPWR

GNDPWR

TXLED
RXLED

CLLED

TPLIL

TPPLR

TPJABB

TPEN

GNDCTL

TCLK
TENA

RCLK
CLSN

TX

14

0.01 Fµ

V

13

4

R

DD

VDDPWR

12

567

2

39Ω

GNDPWR

11109

(Example of PE-65424)

8

CTP3

0.01 Fµ

3

R

100Ω

CC

V

TPRX–

TPRX+

GNDANA

VDDANA

MC68160AFB

TPAPCE

TPSQEL

TPFULDL

ATX+
ATX–

25 262414 16 18 19 20 21 22 23

ARX+
ARX–
ACX+
ACX–
GNDSUB

GNDDIG
VDDDIG

X2

1715

X1
VDDVCO
GNDVCO

15

R

10 KΩ

20MHz

CC

V

DD

V

4

C

20pF

1

X

3

C

20pF

+12V

Coilcraft (LAX–ET30*)

Pulse Engineering (PE–64***)

1

9

16

15

Valor (L T600*/LT603*)

TOKO (Q30ALQ*–1AA3)

1

2

4

R

8

7

6

5

4

3

2

11

12

10

13

14

13

10912

AUI XFMR

5

7

4

R

39Ω

1

C

0.1 Fµ

8

6

R

5

39Ω

39Ω

0.1 Fµ

AUI

15

14
1163

7

R

39Ω

2

C

28

TP Enable

Transmit Clock

TPEN

TCLK

Transmit Enable

Transmit Data

Collision Int

Receive Clock

TENATXCLSN

RCLK

CONTROLLER

COMMUNICATIONS

Receive Enable

Receive Data

RENARXLOOP

MC68360

RENARXCS0

1

2

LoopBack

AutoPort En

APOR

AMD (7990/79C900)

CS1

CS2

345

Intel (825** –86/90/93/96)

Fujitsu (869** –50/60)

LOOP

6

+5.0V

National (8390/83C90/83932B)

DD

V

VDDDIG

7

GNDDIG

8

APORT

9

V

VDDDIV

VDDFM

101112
CC

MFILT

GNDFM

13

Bypassing

Power Supply

CC

V

3900pF

6

12

C5C

R

300Ω

0.039 Fµ

TPSQEL

TPFULDL

TPAPCE

0.1 Fµ

10 Fµ

802.3 Communication Controller
Motorola MC68360, AMD 7990 & 79C900

Intel 82586, 82590, 82593, 82596

Fujitsu MB86950, MB86960

National 8390, 83C690, 83932B

Standby Low Current Mode

00001

CS2

11001

CS1

Communications Controller Selection

10101

CS0

0.1 Fµ

DD

V

10 Fµ

1

1. For Suitable Crystal (X ) see applications text on previous page.

2. Decoupling capacitors should be placed as close to supply pins as possible.

MOTOROLA ANALOG IC DEVICE DATA

MC68160A

OUTLINE DIMENSIONS

FB SUFFIX

PLASTIC PACKAGE

CASE 848D-03

(LQFP–52)

ISSUE C

–L–

–H–

–T–

SEATING
PLANE

4X

N0.20 (0.008) H L–M N0.20 (0.008) T L–M

1

3X VIEW Y

4X TIPS

–X–

X=L, M, N

C

4052

39

L

AB

G

AB

–M–

VIEW Y

B V

PLATING

B1

V1

13

14

27

26

J

F

BASE METAL

U

D

S

L–M

T

S

S1

A1

–N–

0.13 (0.005) N

ROTATED 90_ CLOCKWISE

M

SECTION AB–AB

A

S

C

4X θ2

0.10 (0.004) T

4X θ3

VIEW AA

NOTES:

1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND

IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS
THE PLASTIC BODY AT THE BOTTOM OF THE PARTING
LINE.

4 DATUMS –L–, –M– AND –N– TO BE DETERMINED AT DATUM

PLANE –H–.

5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING

PLANE –T–.

6 DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010)
PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-.

7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION.

DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07
(0.003).

0.05 (0.002)

S

C2

C1

VIEW AA

MOTOROLA ANALOG IC DEVICE DATA

MILLIMETERS

DIMAMIN MAX MIN MAX

10.00 BSC 0.394 BSC

A1 5.00 BSC 0.197 BSC

B 10.00 BSC 0.394 BSC

W

θ1

2 X R R1

0.25 (0.010)

θ

GAGE PLANE

K
E

Z

B1 5.00 BSC 0.197 BSC

C ––– 1.70 ––– 0.067
C1 0.05 0.20 0.002 0.008
C2 1.30 1.50 0.051 0.059

D 0.20 0.40 0.008 0.016

E 0.45 0.030

F 0.22 0.35 0.009 0.014

G 0.65 BSC

J 0.07 0.20 0.003 0.008

K 0.50 REF 0.020 REF
R1 0.08 0.20 0.003 0.008

S 12.00 BSC 0.472 BSC
S1 6.00 BSC 0.236 BSC

U 0.09 0.16 0.004 0.006

V 12.00 BSC 0.472 BSC
V1 6.00 BSC 0.236 BSC
W 0.20 REF 0.008 REF

Z 1.00 REF 0.039 REF

θ

0

__

θ1

0

_

12

θ2

θ3

REF

513

___

INCHES

0.75 0.018

0.026 BSC

0

7

__

––– –––

0

_

12

REF

_

5

13

_

7

_

29

MC68160A

NOTES

30

MOTOROLA ANALOG IC DEVICE DATA

MC68160A

NOTES

MOTOROLA ANALOG IC DEVICE DATA

31

MC68160A

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
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32

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MOTOROLA ANALOG IC DEVICE DATA

Mfax is a trademark of Motorola, Inc.

MC68160A/D